//
// Copyright (c) 2021 NVIDIA Corporation.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// Neither the name of the NVIDIA Corporation nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//

//
// DO NOT EDIT - generated by simspec!
//

#ifndef ARGPIO_H_INC
#define ARGPIO_H_INC
#define NV_MOBILE_ARGPIO_H_UNIT_OF_OFFSET 1B

#define NV_MOBILE_ARGPIO_H_SCRREG_NOMENCLATURE EXACT


// Register GPIO_A_VM_00_0
#define GPIO_A_VM_00_0                  MK_ADDR_CONST(0x0)
#define GPIO_A_VM_00_0_SECURE                   0x0
#define GPIO_A_VM_00_0_DUAL                     0x0
#define GPIO_A_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_00_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_00_0_WORD_COUNT                       0x1
#define GPIO_A_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM1_SHIFT)
#define GPIO_A_VM_00_0_VM1_RANGE                        1:0
#define GPIO_A_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_A_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_A_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM2_SHIFT)
#define GPIO_A_VM_00_0_VM2_RANGE                        3:2
#define GPIO_A_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_A_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_A_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_A_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM3_SHIFT)
#define GPIO_A_VM_00_0_VM3_RANGE                        5:4
#define GPIO_A_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_A_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_A_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_A_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM4_SHIFT)
#define GPIO_A_VM_00_0_VM4_RANGE                        7:6
#define GPIO_A_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_A_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_A_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM5_SHIFT)
#define GPIO_A_VM_00_0_VM5_RANGE                        9:8
#define GPIO_A_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_A_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_A_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_A_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM6_SHIFT)
#define GPIO_A_VM_00_0_VM6_RANGE                        11:10
#define GPIO_A_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_A_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_A_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_A_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM7_SHIFT)
#define GPIO_A_VM_00_0_VM7_RANGE                        13:12
#define GPIO_A_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_A_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_A_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_A_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM8_SHIFT)
#define GPIO_A_VM_00_0_VM8_RANGE                        15:14
#define GPIO_A_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_A_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_A_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_00_0
#define GPIO_A_SCR_00_0                 MK_ADDR_CONST(0x4)
#define GPIO_A_SCR_00_0_SECURE                  0x0
#define GPIO_A_SCR_00_0_DUAL                    0x0
#define GPIO_A_SCR_00_0_SCR                     0
#define GPIO_A_SCR_00_0_SCRREG                  0
#define GPIO_A_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_A_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_A_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_A_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_A_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_A_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_A_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_A_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_A_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR7_SHIFT)
#define GPIO_A_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_A_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR6_SHIFT)
#define GPIO_A_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_A_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR5_SHIFT)
#define GPIO_A_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_A_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR4_SHIFT)
#define GPIO_A_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_A_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR3_SHIFT)
#define GPIO_A_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_A_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR2_SHIFT)
#define GPIO_A_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_A_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR1_SHIFT)
#define GPIO_A_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_A_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR0_SHIFT)
#define GPIO_A_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_A_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G7W_SHIFT)
#define GPIO_A_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_A_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G6W_SHIFT)
#define GPIO_A_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_A_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G5W_SHIFT)
#define GPIO_A_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_A_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G4W_SHIFT)
#define GPIO_A_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_A_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G3W_SHIFT)
#define GPIO_A_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_A_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G2W_SHIFT)
#define GPIO_A_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_A_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G1W_SHIFT)
#define GPIO_A_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_A_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G0W_SHIFT)
#define GPIO_A_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_A_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G7R_SHIFT)
#define GPIO_A_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_A_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G6R_SHIFT)
#define GPIO_A_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G5R_SHIFT)
#define GPIO_A_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_A_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G4R_SHIFT)
#define GPIO_A_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_A_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G3R_SHIFT)
#define GPIO_A_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_A_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G2R_SHIFT)
#define GPIO_A_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_A_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G1R_SHIFT)
#define GPIO_A_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G0R_SHIFT)
#define GPIO_A_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_A_VM_01_0
#define GPIO_A_VM_01_0                  MK_ADDR_CONST(0x8)
#define GPIO_A_VM_01_0_SECURE                   0x0
#define GPIO_A_VM_01_0_DUAL                     0x0
#define GPIO_A_VM_01_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_01_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_01_0_WORD_COUNT                       0x1
#define GPIO_A_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM1_SHIFT)
#define GPIO_A_VM_01_0_VM1_RANGE                        1:0
#define GPIO_A_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_A_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_A_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM2_SHIFT)
#define GPIO_A_VM_01_0_VM2_RANGE                        3:2
#define GPIO_A_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_A_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_A_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_A_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM3_SHIFT)
#define GPIO_A_VM_01_0_VM3_RANGE                        5:4
#define GPIO_A_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_A_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_A_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_A_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM4_SHIFT)
#define GPIO_A_VM_01_0_VM4_RANGE                        7:6
#define GPIO_A_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_A_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_A_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM5_SHIFT)
#define GPIO_A_VM_01_0_VM5_RANGE                        9:8
#define GPIO_A_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_A_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_A_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_A_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM6_SHIFT)
#define GPIO_A_VM_01_0_VM6_RANGE                        11:10
#define GPIO_A_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_A_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_A_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_A_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM7_SHIFT)
#define GPIO_A_VM_01_0_VM7_RANGE                        13:12
#define GPIO_A_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_A_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_A_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_A_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM8_SHIFT)
#define GPIO_A_VM_01_0_VM8_RANGE                        15:14
#define GPIO_A_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_A_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_A_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_01_0
#define GPIO_A_SCR_01_0                 MK_ADDR_CONST(0xc)
#define GPIO_A_SCR_01_0_SECURE                  0x0
#define GPIO_A_SCR_01_0_DUAL                    0x0
#define GPIO_A_SCR_01_0_SCR                     0
#define GPIO_A_SCR_01_0_SCRREG                  0
#define GPIO_A_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_A_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_A_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_A_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_A_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_A_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_A_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_A_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_A_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR7_SHIFT)
#define GPIO_A_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_A_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR6_SHIFT)
#define GPIO_A_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_A_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR5_SHIFT)
#define GPIO_A_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_A_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR4_SHIFT)
#define GPIO_A_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_A_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR3_SHIFT)
#define GPIO_A_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_A_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR2_SHIFT)
#define GPIO_A_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_A_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR1_SHIFT)
#define GPIO_A_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_A_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR0_SHIFT)
#define GPIO_A_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_A_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G7W_SHIFT)
#define GPIO_A_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_A_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G6W_SHIFT)
#define GPIO_A_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_A_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G5W_SHIFT)
#define GPIO_A_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_A_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G4W_SHIFT)
#define GPIO_A_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_A_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G3W_SHIFT)
#define GPIO_A_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_A_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G2W_SHIFT)
#define GPIO_A_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_A_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G1W_SHIFT)
#define GPIO_A_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_A_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G0W_SHIFT)
#define GPIO_A_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_A_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G7R_SHIFT)
#define GPIO_A_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_A_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G6R_SHIFT)
#define GPIO_A_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G5R_SHIFT)
#define GPIO_A_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_A_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G4R_SHIFT)
#define GPIO_A_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_A_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G3R_SHIFT)
#define GPIO_A_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_A_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G2R_SHIFT)
#define GPIO_A_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_A_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G1R_SHIFT)
#define GPIO_A_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G0R_SHIFT)
#define GPIO_A_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_A_VM_02_0
#define GPIO_A_VM_02_0                  MK_ADDR_CONST(0x10)
#define GPIO_A_VM_02_0_SECURE                   0x0
#define GPIO_A_VM_02_0_DUAL                     0x0
#define GPIO_A_VM_02_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_02_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_02_0_WORD_COUNT                       0x1
#define GPIO_A_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM1_SHIFT)
#define GPIO_A_VM_02_0_VM1_RANGE                        1:0
#define GPIO_A_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_A_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_A_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM2_SHIFT)
#define GPIO_A_VM_02_0_VM2_RANGE                        3:2
#define GPIO_A_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_A_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_A_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_A_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM3_SHIFT)
#define GPIO_A_VM_02_0_VM3_RANGE                        5:4
#define GPIO_A_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_A_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_A_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_A_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM4_SHIFT)
#define GPIO_A_VM_02_0_VM4_RANGE                        7:6
#define GPIO_A_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_A_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_A_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM5_SHIFT)
#define GPIO_A_VM_02_0_VM5_RANGE                        9:8
#define GPIO_A_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_A_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_A_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_A_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM6_SHIFT)
#define GPIO_A_VM_02_0_VM6_RANGE                        11:10
#define GPIO_A_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_A_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_A_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_A_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM7_SHIFT)
#define GPIO_A_VM_02_0_VM7_RANGE                        13:12
#define GPIO_A_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_A_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_A_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_A_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM8_SHIFT)
#define GPIO_A_VM_02_0_VM8_RANGE                        15:14
#define GPIO_A_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_A_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_A_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_02_0
#define GPIO_A_SCR_02_0                 MK_ADDR_CONST(0x14)
#define GPIO_A_SCR_02_0_SECURE                  0x0
#define GPIO_A_SCR_02_0_DUAL                    0x0
#define GPIO_A_SCR_02_0_SCR                     0
#define GPIO_A_SCR_02_0_SCRREG                  0
#define GPIO_A_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_A_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_A_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_A_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_A_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_A_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_A_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_A_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_A_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR7_SHIFT)
#define GPIO_A_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_A_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR6_SHIFT)
#define GPIO_A_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_A_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR5_SHIFT)
#define GPIO_A_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_A_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR4_SHIFT)
#define GPIO_A_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_A_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR3_SHIFT)
#define GPIO_A_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_A_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR2_SHIFT)
#define GPIO_A_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_A_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR1_SHIFT)
#define GPIO_A_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_A_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR0_SHIFT)
#define GPIO_A_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_A_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G7W_SHIFT)
#define GPIO_A_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_A_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G6W_SHIFT)
#define GPIO_A_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_A_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G5W_SHIFT)
#define GPIO_A_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_A_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G4W_SHIFT)
#define GPIO_A_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_A_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G3W_SHIFT)
#define GPIO_A_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_A_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G2W_SHIFT)
#define GPIO_A_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_A_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G1W_SHIFT)
#define GPIO_A_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_A_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G0W_SHIFT)
#define GPIO_A_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_A_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G7R_SHIFT)
#define GPIO_A_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_A_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G6R_SHIFT)
#define GPIO_A_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G5R_SHIFT)
#define GPIO_A_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_A_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G4R_SHIFT)
#define GPIO_A_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_A_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G3R_SHIFT)
#define GPIO_A_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_A_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G2R_SHIFT)
#define GPIO_A_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_A_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G1R_SHIFT)
#define GPIO_A_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G0R_SHIFT)
#define GPIO_A_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_A_VM_03_0
#define GPIO_A_VM_03_0                  MK_ADDR_CONST(0x18)
#define GPIO_A_VM_03_0_SECURE                   0x0
#define GPIO_A_VM_03_0_DUAL                     0x0
#define GPIO_A_VM_03_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_03_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_03_0_WORD_COUNT                       0x1
#define GPIO_A_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM1_SHIFT)
#define GPIO_A_VM_03_0_VM1_RANGE                        1:0
#define GPIO_A_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_A_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_A_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM2_SHIFT)
#define GPIO_A_VM_03_0_VM2_RANGE                        3:2
#define GPIO_A_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_A_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_A_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_A_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM3_SHIFT)
#define GPIO_A_VM_03_0_VM3_RANGE                        5:4
#define GPIO_A_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_A_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_A_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_A_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM4_SHIFT)
#define GPIO_A_VM_03_0_VM4_RANGE                        7:6
#define GPIO_A_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_A_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_A_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM5_SHIFT)
#define GPIO_A_VM_03_0_VM5_RANGE                        9:8
#define GPIO_A_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_A_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_A_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_A_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM6_SHIFT)
#define GPIO_A_VM_03_0_VM6_RANGE                        11:10
#define GPIO_A_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_A_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_A_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_A_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM7_SHIFT)
#define GPIO_A_VM_03_0_VM7_RANGE                        13:12
#define GPIO_A_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_A_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_A_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_A_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM8_SHIFT)
#define GPIO_A_VM_03_0_VM8_RANGE                        15:14
#define GPIO_A_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_A_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_A_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_03_0
#define GPIO_A_SCR_03_0                 MK_ADDR_CONST(0x1c)
#define GPIO_A_SCR_03_0_SECURE                  0x0
#define GPIO_A_SCR_03_0_DUAL                    0x0
#define GPIO_A_SCR_03_0_SCR                     0
#define GPIO_A_SCR_03_0_SCRREG                  0
#define GPIO_A_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_A_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_A_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_A_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_A_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_A_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_A_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_A_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_A_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR7_SHIFT)
#define GPIO_A_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_A_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR6_SHIFT)
#define GPIO_A_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_A_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR5_SHIFT)
#define GPIO_A_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_A_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR4_SHIFT)
#define GPIO_A_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_A_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR3_SHIFT)
#define GPIO_A_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_A_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR2_SHIFT)
#define GPIO_A_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_A_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR1_SHIFT)
#define GPIO_A_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_A_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR0_SHIFT)
#define GPIO_A_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_A_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G7W_SHIFT)
#define GPIO_A_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_A_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G6W_SHIFT)
#define GPIO_A_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_A_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G5W_SHIFT)
#define GPIO_A_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_A_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G4W_SHIFT)
#define GPIO_A_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_A_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G3W_SHIFT)
#define GPIO_A_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_A_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G2W_SHIFT)
#define GPIO_A_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_A_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G1W_SHIFT)
#define GPIO_A_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_A_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G0W_SHIFT)
#define GPIO_A_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_A_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G7R_SHIFT)
#define GPIO_A_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_A_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G6R_SHIFT)
#define GPIO_A_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G5R_SHIFT)
#define GPIO_A_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_A_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G4R_SHIFT)
#define GPIO_A_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_A_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G3R_SHIFT)
#define GPIO_A_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_A_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G2R_SHIFT)
#define GPIO_A_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_A_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G1R_SHIFT)
#define GPIO_A_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G0R_SHIFT)
#define GPIO_A_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_A_VM_04_0
#define GPIO_A_VM_04_0                  MK_ADDR_CONST(0x20)
#define GPIO_A_VM_04_0_SECURE                   0x0
#define GPIO_A_VM_04_0_DUAL                     0x0
#define GPIO_A_VM_04_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_04_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_04_0_WORD_COUNT                       0x1
#define GPIO_A_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM1_SHIFT)
#define GPIO_A_VM_04_0_VM1_RANGE                        1:0
#define GPIO_A_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_A_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_A_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM2_SHIFT)
#define GPIO_A_VM_04_0_VM2_RANGE                        3:2
#define GPIO_A_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_A_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_A_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_A_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM3_SHIFT)
#define GPIO_A_VM_04_0_VM3_RANGE                        5:4
#define GPIO_A_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_A_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_A_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_A_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM4_SHIFT)
#define GPIO_A_VM_04_0_VM4_RANGE                        7:6
#define GPIO_A_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_A_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_A_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM5_SHIFT)
#define GPIO_A_VM_04_0_VM5_RANGE                        9:8
#define GPIO_A_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_A_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_A_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_A_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM6_SHIFT)
#define GPIO_A_VM_04_0_VM6_RANGE                        11:10
#define GPIO_A_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_A_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_A_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_A_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM7_SHIFT)
#define GPIO_A_VM_04_0_VM7_RANGE                        13:12
#define GPIO_A_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_A_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_A_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_A_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM8_SHIFT)
#define GPIO_A_VM_04_0_VM8_RANGE                        15:14
#define GPIO_A_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_A_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_A_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_04_0
#define GPIO_A_SCR_04_0                 MK_ADDR_CONST(0x24)
#define GPIO_A_SCR_04_0_SECURE                  0x0
#define GPIO_A_SCR_04_0_DUAL                    0x0
#define GPIO_A_SCR_04_0_SCR                     0
#define GPIO_A_SCR_04_0_SCRREG                  0
#define GPIO_A_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_A_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_A_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_A_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_A_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_A_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_A_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_A_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_A_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR7_SHIFT)
#define GPIO_A_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_A_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR6_SHIFT)
#define GPIO_A_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_A_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR5_SHIFT)
#define GPIO_A_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_A_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR4_SHIFT)
#define GPIO_A_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_A_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR3_SHIFT)
#define GPIO_A_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_A_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR2_SHIFT)
#define GPIO_A_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_A_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR1_SHIFT)
#define GPIO_A_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_A_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR0_SHIFT)
#define GPIO_A_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_A_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G7W_SHIFT)
#define GPIO_A_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_A_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G6W_SHIFT)
#define GPIO_A_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_A_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G5W_SHIFT)
#define GPIO_A_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_A_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G4W_SHIFT)
#define GPIO_A_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_A_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G3W_SHIFT)
#define GPIO_A_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_A_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G2W_SHIFT)
#define GPIO_A_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_A_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G1W_SHIFT)
#define GPIO_A_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_A_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G0W_SHIFT)
#define GPIO_A_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_A_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G7R_SHIFT)
#define GPIO_A_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_A_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G6R_SHIFT)
#define GPIO_A_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G5R_SHIFT)
#define GPIO_A_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_A_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G4R_SHIFT)
#define GPIO_A_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_A_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G3R_SHIFT)
#define GPIO_A_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_A_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G2R_SHIFT)
#define GPIO_A_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_A_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G1R_SHIFT)
#define GPIO_A_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G0R_SHIFT)
#define GPIO_A_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_A_VM_05_0
#define GPIO_A_VM_05_0                  MK_ADDR_CONST(0x28)
#define GPIO_A_VM_05_0_SECURE                   0x0
#define GPIO_A_VM_05_0_DUAL                     0x0
#define GPIO_A_VM_05_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_05_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_05_0_WORD_COUNT                       0x1
#define GPIO_A_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM1_SHIFT)
#define GPIO_A_VM_05_0_VM1_RANGE                        1:0
#define GPIO_A_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_A_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_A_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM2_SHIFT)
#define GPIO_A_VM_05_0_VM2_RANGE                        3:2
#define GPIO_A_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_A_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_A_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_A_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM3_SHIFT)
#define GPIO_A_VM_05_0_VM3_RANGE                        5:4
#define GPIO_A_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_A_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_A_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_A_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM4_SHIFT)
#define GPIO_A_VM_05_0_VM4_RANGE                        7:6
#define GPIO_A_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_A_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_A_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM5_SHIFT)
#define GPIO_A_VM_05_0_VM5_RANGE                        9:8
#define GPIO_A_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_A_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_A_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_A_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM6_SHIFT)
#define GPIO_A_VM_05_0_VM6_RANGE                        11:10
#define GPIO_A_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_A_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_A_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_A_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM7_SHIFT)
#define GPIO_A_VM_05_0_VM7_RANGE                        13:12
#define GPIO_A_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_A_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_A_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_A_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM8_SHIFT)
#define GPIO_A_VM_05_0_VM8_RANGE                        15:14
#define GPIO_A_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_A_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_A_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_05_0
#define GPIO_A_SCR_05_0                 MK_ADDR_CONST(0x2c)
#define GPIO_A_SCR_05_0_SECURE                  0x0
#define GPIO_A_SCR_05_0_DUAL                    0x0
#define GPIO_A_SCR_05_0_SCR                     0
#define GPIO_A_SCR_05_0_SCRREG                  0
#define GPIO_A_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_A_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_A_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_A_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_A_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_A_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_A_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_A_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_A_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR7_SHIFT)
#define GPIO_A_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_A_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR6_SHIFT)
#define GPIO_A_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_A_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR5_SHIFT)
#define GPIO_A_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_A_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR4_SHIFT)
#define GPIO_A_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_A_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR3_SHIFT)
#define GPIO_A_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_A_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR2_SHIFT)
#define GPIO_A_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_A_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR1_SHIFT)
#define GPIO_A_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_A_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR0_SHIFT)
#define GPIO_A_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_A_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G7W_SHIFT)
#define GPIO_A_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_A_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G6W_SHIFT)
#define GPIO_A_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_A_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G5W_SHIFT)
#define GPIO_A_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_A_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G4W_SHIFT)
#define GPIO_A_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_A_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G3W_SHIFT)
#define GPIO_A_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_A_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G2W_SHIFT)
#define GPIO_A_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_A_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G1W_SHIFT)
#define GPIO_A_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_A_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G0W_SHIFT)
#define GPIO_A_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_A_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G7R_SHIFT)
#define GPIO_A_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_A_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G6R_SHIFT)
#define GPIO_A_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G5R_SHIFT)
#define GPIO_A_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_A_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G4R_SHIFT)
#define GPIO_A_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_A_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G3R_SHIFT)
#define GPIO_A_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_A_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G2R_SHIFT)
#define GPIO_A_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_A_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G1R_SHIFT)
#define GPIO_A_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G0R_SHIFT)
#define GPIO_A_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_A_VM_06_0
#define GPIO_A_VM_06_0                  MK_ADDR_CONST(0x30)
#define GPIO_A_VM_06_0_SECURE                   0x0
#define GPIO_A_VM_06_0_DUAL                     0x0
#define GPIO_A_VM_06_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_06_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_06_0_WORD_COUNT                       0x1
#define GPIO_A_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM1_SHIFT)
#define GPIO_A_VM_06_0_VM1_RANGE                        1:0
#define GPIO_A_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_A_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_A_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM2_SHIFT)
#define GPIO_A_VM_06_0_VM2_RANGE                        3:2
#define GPIO_A_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_A_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_A_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_A_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM3_SHIFT)
#define GPIO_A_VM_06_0_VM3_RANGE                        5:4
#define GPIO_A_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_A_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_A_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_A_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM4_SHIFT)
#define GPIO_A_VM_06_0_VM4_RANGE                        7:6
#define GPIO_A_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_A_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_A_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM5_SHIFT)
#define GPIO_A_VM_06_0_VM5_RANGE                        9:8
#define GPIO_A_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_A_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_A_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_A_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM6_SHIFT)
#define GPIO_A_VM_06_0_VM6_RANGE                        11:10
#define GPIO_A_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_A_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_A_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_A_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM7_SHIFT)
#define GPIO_A_VM_06_0_VM7_RANGE                        13:12
#define GPIO_A_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_A_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_A_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_A_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM8_SHIFT)
#define GPIO_A_VM_06_0_VM8_RANGE                        15:14
#define GPIO_A_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_A_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_A_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_06_0
#define GPIO_A_SCR_06_0                 MK_ADDR_CONST(0x34)
#define GPIO_A_SCR_06_0_SECURE                  0x0
#define GPIO_A_SCR_06_0_DUAL                    0x0
#define GPIO_A_SCR_06_0_SCR                     0
#define GPIO_A_SCR_06_0_SCRREG                  0
#define GPIO_A_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_A_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_A_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_A_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_A_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_A_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_A_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_A_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_A_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR7_SHIFT)
#define GPIO_A_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_A_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR6_SHIFT)
#define GPIO_A_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_A_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR5_SHIFT)
#define GPIO_A_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_A_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR4_SHIFT)
#define GPIO_A_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_A_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR3_SHIFT)
#define GPIO_A_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_A_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR2_SHIFT)
#define GPIO_A_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_A_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR1_SHIFT)
#define GPIO_A_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_A_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR0_SHIFT)
#define GPIO_A_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_A_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G7W_SHIFT)
#define GPIO_A_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_A_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G6W_SHIFT)
#define GPIO_A_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_A_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G5W_SHIFT)
#define GPIO_A_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_A_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G4W_SHIFT)
#define GPIO_A_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_A_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G3W_SHIFT)
#define GPIO_A_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_A_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G2W_SHIFT)
#define GPIO_A_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_A_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G1W_SHIFT)
#define GPIO_A_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_A_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G0W_SHIFT)
#define GPIO_A_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_A_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G7R_SHIFT)
#define GPIO_A_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_A_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G6R_SHIFT)
#define GPIO_A_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G5R_SHIFT)
#define GPIO_A_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_A_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G4R_SHIFT)
#define GPIO_A_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_A_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G3R_SHIFT)
#define GPIO_A_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_A_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G2R_SHIFT)
#define GPIO_A_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_A_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G1R_SHIFT)
#define GPIO_A_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G0R_SHIFT)
#define GPIO_A_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_A_VM_07_0
#define GPIO_A_VM_07_0                  MK_ADDR_CONST(0x38)
#define GPIO_A_VM_07_0_SECURE                   0x0
#define GPIO_A_VM_07_0_DUAL                     0x0
#define GPIO_A_VM_07_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_07_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_A_VM_07_0_WORD_COUNT                       0x1
#define GPIO_A_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_A_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_A_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM1_SHIFT)
#define GPIO_A_VM_07_0_VM1_RANGE                        1:0
#define GPIO_A_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_A_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_A_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM2_SHIFT)
#define GPIO_A_VM_07_0_VM2_RANGE                        3:2
#define GPIO_A_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_A_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_A_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_A_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM3_SHIFT)
#define GPIO_A_VM_07_0_VM3_RANGE                        5:4
#define GPIO_A_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_A_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_A_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_A_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM4_SHIFT)
#define GPIO_A_VM_07_0_VM4_RANGE                        7:6
#define GPIO_A_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_A_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_A_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM5_SHIFT)
#define GPIO_A_VM_07_0_VM5_RANGE                        9:8
#define GPIO_A_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_A_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_A_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_A_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM6_SHIFT)
#define GPIO_A_VM_07_0_VM6_RANGE                        11:10
#define GPIO_A_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_A_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_A_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_A_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM7_SHIFT)
#define GPIO_A_VM_07_0_VM7_RANGE                        13:12
#define GPIO_A_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_A_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_A_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_A_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_A_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM8_SHIFT)
#define GPIO_A_VM_07_0_VM8_RANGE                        15:14
#define GPIO_A_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_A_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_A_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_A_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_A_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_SCR_07_0
#define GPIO_A_SCR_07_0                 MK_ADDR_CONST(0x3c)
#define GPIO_A_SCR_07_0_SECURE                  0x0
#define GPIO_A_SCR_07_0_DUAL                    0x0
#define GPIO_A_SCR_07_0_SCR                     0
#define GPIO_A_SCR_07_0_SCRREG                  0
#define GPIO_A_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_A_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_A_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_A_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_A_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_A_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_A_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_A_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_A_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_A_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_A_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_A_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_A_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_A_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_A_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_A_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_A_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_A_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_A_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_A_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_A_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_A_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_A_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_A_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_A_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_A_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR7_SHIFT)
#define GPIO_A_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_A_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_A_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_A_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR6_SHIFT)
#define GPIO_A_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_A_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_A_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_A_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR5_SHIFT)
#define GPIO_A_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_A_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_A_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_A_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR4_SHIFT)
#define GPIO_A_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_A_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_A_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_A_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR3_SHIFT)
#define GPIO_A_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_A_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_A_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_A_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR2_SHIFT)
#define GPIO_A_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_A_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_A_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_A_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR1_SHIFT)
#define GPIO_A_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_A_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_A_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_A_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR0_SHIFT)
#define GPIO_A_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_A_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_A_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_A_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G7W_SHIFT)
#define GPIO_A_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_A_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_A_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_A_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G6W_SHIFT)
#define GPIO_A_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_A_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_A_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_A_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G5W_SHIFT)
#define GPIO_A_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_A_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_A_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_A_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G4W_SHIFT)
#define GPIO_A_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_A_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_A_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_A_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G3W_SHIFT)
#define GPIO_A_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_A_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_A_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_A_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G2W_SHIFT)
#define GPIO_A_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_A_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_A_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_A_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G1W_SHIFT)
#define GPIO_A_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_A_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_A_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_A_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G0W_SHIFT)
#define GPIO_A_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_A_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_A_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_A_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G7R_SHIFT)
#define GPIO_A_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_A_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_A_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_A_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G6R_SHIFT)
#define GPIO_A_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_A_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_A_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G5R_SHIFT)
#define GPIO_A_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_A_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_A_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G4R_SHIFT)
#define GPIO_A_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_A_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_A_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_A_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G3R_SHIFT)
#define GPIO_A_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_A_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_A_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_A_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G2R_SHIFT)
#define GPIO_A_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_A_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_A_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_A_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G1R_SHIFT)
#define GPIO_A_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_A_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_A_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_A_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G0R_SHIFT)
#define GPIO_A_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_A_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_A_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_A_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_VM_00_0
#define GPIO_AC_VM_00_0                 MK_ADDR_CONST(0x40)
#define GPIO_AC_VM_00_0_SECURE                  0x0
#define GPIO_AC_VM_00_0_DUAL                    0x0
#define GPIO_AC_VM_00_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_00_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_00_0_WORD_COUNT                      0x1
#define GPIO_AC_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM1_SHIFT)
#define GPIO_AC_VM_00_0_VM1_RANGE                       1:0
#define GPIO_AC_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AC_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_AC_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AC_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM2_SHIFT)
#define GPIO_AC_VM_00_0_VM2_RANGE                       3:2
#define GPIO_AC_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AC_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AC_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_AC_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AC_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM3_SHIFT)
#define GPIO_AC_VM_00_0_VM3_RANGE                       5:4
#define GPIO_AC_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AC_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AC_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_AC_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AC_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM4_SHIFT)
#define GPIO_AC_VM_00_0_VM4_RANGE                       7:6
#define GPIO_AC_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AC_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_AC_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AC_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM5_SHIFT)
#define GPIO_AC_VM_00_0_VM5_RANGE                       9:8
#define GPIO_AC_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AC_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AC_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_AC_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AC_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM6_SHIFT)
#define GPIO_AC_VM_00_0_VM6_RANGE                       11:10
#define GPIO_AC_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AC_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AC_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_AC_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AC_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM7_SHIFT)
#define GPIO_AC_VM_00_0_VM7_RANGE                       13:12
#define GPIO_AC_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AC_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AC_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_AC_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AC_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM8_SHIFT)
#define GPIO_AC_VM_00_0_VM8_RANGE                       15:14
#define GPIO_AC_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AC_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AC_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_AC_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_SCR_00_0
#define GPIO_AC_SCR_00_0                        MK_ADDR_CONST(0x44)
#define GPIO_AC_SCR_00_0_SECURE                         0x0
#define GPIO_AC_SCR_00_0_DUAL                   0x0
#define GPIO_AC_SCR_00_0_SCR                    0
#define GPIO_AC_SCR_00_0_SCRREG                         0
#define GPIO_AC_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_AC_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_AC_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_AC_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AC_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_AC_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_AC_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AC_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_AC_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_AC_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AC_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_AC_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AC_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AC_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AC_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AC_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR7_SHIFT)
#define GPIO_AC_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_AC_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR6_SHIFT)
#define GPIO_AC_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_AC_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR5_SHIFT)
#define GPIO_AC_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_AC_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR4_SHIFT)
#define GPIO_AC_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_AC_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR3_SHIFT)
#define GPIO_AC_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_AC_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR2_SHIFT)
#define GPIO_AC_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_AC_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR1_SHIFT)
#define GPIO_AC_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_AC_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR0_SHIFT)
#define GPIO_AC_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_AC_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G7W_SHIFT)
#define GPIO_AC_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_AC_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G6W_SHIFT)
#define GPIO_AC_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_AC_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G5W_SHIFT)
#define GPIO_AC_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_AC_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G4W_SHIFT)
#define GPIO_AC_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_AC_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G3W_SHIFT)
#define GPIO_AC_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_AC_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G2W_SHIFT)
#define GPIO_AC_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_AC_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G1W_SHIFT)
#define GPIO_AC_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_AC_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G0W_SHIFT)
#define GPIO_AC_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_AC_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G7R_SHIFT)
#define GPIO_AC_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_AC_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G6R_SHIFT)
#define GPIO_AC_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_AC_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G5R_SHIFT)
#define GPIO_AC_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_AC_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G4R_SHIFT)
#define GPIO_AC_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_AC_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G3R_SHIFT)
#define GPIO_AC_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_AC_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G2R_SHIFT)
#define GPIO_AC_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_AC_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G1R_SHIFT)
#define GPIO_AC_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_AC_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G0R_SHIFT)
#define GPIO_AC_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_AC_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_AC_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AC_VM_01_0
#define GPIO_AC_VM_01_0                 MK_ADDR_CONST(0x48)
#define GPIO_AC_VM_01_0_SECURE                  0x0
#define GPIO_AC_VM_01_0_DUAL                    0x0
#define GPIO_AC_VM_01_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_01_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_01_0_WORD_COUNT                      0x1
#define GPIO_AC_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM1_SHIFT)
#define GPIO_AC_VM_01_0_VM1_RANGE                       1:0
#define GPIO_AC_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AC_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_AC_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AC_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM2_SHIFT)
#define GPIO_AC_VM_01_0_VM2_RANGE                       3:2
#define GPIO_AC_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AC_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AC_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_AC_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AC_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM3_SHIFT)
#define GPIO_AC_VM_01_0_VM3_RANGE                       5:4
#define GPIO_AC_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AC_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AC_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_AC_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AC_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM4_SHIFT)
#define GPIO_AC_VM_01_0_VM4_RANGE                       7:6
#define GPIO_AC_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AC_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_AC_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AC_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM5_SHIFT)
#define GPIO_AC_VM_01_0_VM5_RANGE                       9:8
#define GPIO_AC_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AC_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AC_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_AC_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AC_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM6_SHIFT)
#define GPIO_AC_VM_01_0_VM6_RANGE                       11:10
#define GPIO_AC_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AC_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AC_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_AC_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AC_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM7_SHIFT)
#define GPIO_AC_VM_01_0_VM7_RANGE                       13:12
#define GPIO_AC_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AC_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AC_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_AC_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AC_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM8_SHIFT)
#define GPIO_AC_VM_01_0_VM8_RANGE                       15:14
#define GPIO_AC_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AC_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AC_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_AC_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_SCR_01_0
#define GPIO_AC_SCR_01_0                        MK_ADDR_CONST(0x4c)
#define GPIO_AC_SCR_01_0_SECURE                         0x0
#define GPIO_AC_SCR_01_0_DUAL                   0x0
#define GPIO_AC_SCR_01_0_SCR                    0
#define GPIO_AC_SCR_01_0_SCRREG                         0
#define GPIO_AC_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_AC_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_AC_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_AC_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AC_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_AC_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_AC_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AC_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_AC_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_AC_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AC_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_AC_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AC_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AC_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AC_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AC_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR7_SHIFT)
#define GPIO_AC_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_AC_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR6_SHIFT)
#define GPIO_AC_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_AC_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR5_SHIFT)
#define GPIO_AC_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_AC_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR4_SHIFT)
#define GPIO_AC_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_AC_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR3_SHIFT)
#define GPIO_AC_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_AC_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR2_SHIFT)
#define GPIO_AC_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_AC_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR1_SHIFT)
#define GPIO_AC_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_AC_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR0_SHIFT)
#define GPIO_AC_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_AC_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G7W_SHIFT)
#define GPIO_AC_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_AC_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G6W_SHIFT)
#define GPIO_AC_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_AC_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G5W_SHIFT)
#define GPIO_AC_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_AC_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G4W_SHIFT)
#define GPIO_AC_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_AC_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G3W_SHIFT)
#define GPIO_AC_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_AC_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G2W_SHIFT)
#define GPIO_AC_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_AC_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G1W_SHIFT)
#define GPIO_AC_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_AC_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G0W_SHIFT)
#define GPIO_AC_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_AC_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G7R_SHIFT)
#define GPIO_AC_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_AC_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G6R_SHIFT)
#define GPIO_AC_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_AC_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G5R_SHIFT)
#define GPIO_AC_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_AC_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G4R_SHIFT)
#define GPIO_AC_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_AC_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G3R_SHIFT)
#define GPIO_AC_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_AC_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G2R_SHIFT)
#define GPIO_AC_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_AC_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G1R_SHIFT)
#define GPIO_AC_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_AC_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G0R_SHIFT)
#define GPIO_AC_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_AC_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_AC_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AC_VM_02_0
#define GPIO_AC_VM_02_0                 MK_ADDR_CONST(0x50)
#define GPIO_AC_VM_02_0_SECURE                  0x0
#define GPIO_AC_VM_02_0_DUAL                    0x0
#define GPIO_AC_VM_02_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_02_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_02_0_WORD_COUNT                      0x1
#define GPIO_AC_VM_02_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_02_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_02_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_02_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_VM_02_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM1_SHIFT)
#define GPIO_AC_VM_02_0_VM1_RANGE                       1:0
#define GPIO_AC_VM_02_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AC_VM_02_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_VM_02_0_VM1_WOFFSET                     0x0
#define GPIO_AC_VM_02_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_02_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AC_VM_02_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM2_SHIFT)
#define GPIO_AC_VM_02_0_VM2_RANGE                       3:2
#define GPIO_AC_VM_02_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AC_VM_02_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AC_VM_02_0_VM2_WOFFSET                     0x0
#define GPIO_AC_VM_02_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_02_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AC_VM_02_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM3_SHIFT)
#define GPIO_AC_VM_02_0_VM3_RANGE                       5:4
#define GPIO_AC_VM_02_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AC_VM_02_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AC_VM_02_0_VM3_WOFFSET                     0x0
#define GPIO_AC_VM_02_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_02_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AC_VM_02_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM4_SHIFT)
#define GPIO_AC_VM_02_0_VM4_RANGE                       7:6
#define GPIO_AC_VM_02_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_VM_02_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AC_VM_02_0_VM4_WOFFSET                     0x0
#define GPIO_AC_VM_02_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_02_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AC_VM_02_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM5_SHIFT)
#define GPIO_AC_VM_02_0_VM5_RANGE                       9:8
#define GPIO_AC_VM_02_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AC_VM_02_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AC_VM_02_0_VM5_WOFFSET                     0x0
#define GPIO_AC_VM_02_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_02_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AC_VM_02_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM6_SHIFT)
#define GPIO_AC_VM_02_0_VM6_RANGE                       11:10
#define GPIO_AC_VM_02_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AC_VM_02_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AC_VM_02_0_VM6_WOFFSET                     0x0
#define GPIO_AC_VM_02_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_02_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AC_VM_02_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM7_SHIFT)
#define GPIO_AC_VM_02_0_VM7_RANGE                       13:12
#define GPIO_AC_VM_02_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AC_VM_02_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AC_VM_02_0_VM7_WOFFSET                     0x0
#define GPIO_AC_VM_02_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_02_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AC_VM_02_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM8_SHIFT)
#define GPIO_AC_VM_02_0_VM8_RANGE                       15:14
#define GPIO_AC_VM_02_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AC_VM_02_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AC_VM_02_0_VM8_WOFFSET                     0x0
#define GPIO_AC_VM_02_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_02_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_02_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_SCR_02_0
#define GPIO_AC_SCR_02_0                        MK_ADDR_CONST(0x54)
#define GPIO_AC_SCR_02_0_SECURE                         0x0
#define GPIO_AC_SCR_02_0_DUAL                   0x0
#define GPIO_AC_SCR_02_0_SCR                    0
#define GPIO_AC_SCR_02_0_SCRREG                         0
#define GPIO_AC_SCR_02_0_WORD_COUNT                     0x1
#define GPIO_AC_SCR_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_02_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_02_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_02_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_AC_SCR_02_0_SEC_LCK_RANGE                  29:29
#define GPIO_AC_SCR_02_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_02_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_02_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AC_SCR_02_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_02_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_AC_SCR_02_0_SEC_WEN_RANGE                  28:28
#define GPIO_AC_SCR_02_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_02_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_02_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AC_SCR_02_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_02_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_AC_SCR_02_0_SEC_REN_RANGE                  27:27
#define GPIO_AC_SCR_02_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_02_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_02_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AC_SCR_02_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_02_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_AC_SCR_02_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AC_SCR_02_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AC_SCR_02_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AC_SCR_02_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AC_SCR_02_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_02_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR7_SHIFT)
#define GPIO_AC_SCR_02_0_PR7_RANGE                      23:23
#define GPIO_AC_SCR_02_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_02_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_02_0_PR7_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_02_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR6_SHIFT)
#define GPIO_AC_SCR_02_0_PR6_RANGE                      22:22
#define GPIO_AC_SCR_02_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_02_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_02_0_PR6_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_02_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR5_SHIFT)
#define GPIO_AC_SCR_02_0_PR5_RANGE                      21:21
#define GPIO_AC_SCR_02_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_02_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_02_0_PR5_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_02_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR4_SHIFT)
#define GPIO_AC_SCR_02_0_PR4_RANGE                      20:20
#define GPIO_AC_SCR_02_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_02_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_02_0_PR4_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_02_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR3_SHIFT)
#define GPIO_AC_SCR_02_0_PR3_RANGE                      19:19
#define GPIO_AC_SCR_02_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_02_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_02_0_PR3_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_02_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR2_SHIFT)
#define GPIO_AC_SCR_02_0_PR2_RANGE                      18:18
#define GPIO_AC_SCR_02_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_02_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_02_0_PR2_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_02_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR1_SHIFT)
#define GPIO_AC_SCR_02_0_PR1_RANGE                      17:17
#define GPIO_AC_SCR_02_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_02_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_02_0_PR1_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_02_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR0_SHIFT)
#define GPIO_AC_SCR_02_0_PR0_RANGE                      16:16
#define GPIO_AC_SCR_02_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_02_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_02_0_PR0_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_02_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G7W_SHIFT)
#define GPIO_AC_SCR_02_0_G7W_RANGE                      15:15
#define GPIO_AC_SCR_02_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_02_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_02_0_G7W_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_02_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G6W_SHIFT)
#define GPIO_AC_SCR_02_0_G6W_RANGE                      14:14
#define GPIO_AC_SCR_02_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_02_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_02_0_G6W_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_02_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G5W_SHIFT)
#define GPIO_AC_SCR_02_0_G5W_RANGE                      13:13
#define GPIO_AC_SCR_02_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_02_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_02_0_G5W_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_02_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G4W_SHIFT)
#define GPIO_AC_SCR_02_0_G4W_RANGE                      12:12
#define GPIO_AC_SCR_02_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_02_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_02_0_G4W_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_02_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G3W_SHIFT)
#define GPIO_AC_SCR_02_0_G3W_RANGE                      11:11
#define GPIO_AC_SCR_02_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_02_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_02_0_G3W_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_02_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G2W_SHIFT)
#define GPIO_AC_SCR_02_0_G2W_RANGE                      10:10
#define GPIO_AC_SCR_02_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_02_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_02_0_G2W_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_02_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G1W_SHIFT)
#define GPIO_AC_SCR_02_0_G1W_RANGE                      9:9
#define GPIO_AC_SCR_02_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_02_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_02_0_G1W_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_02_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G0W_SHIFT)
#define GPIO_AC_SCR_02_0_G0W_RANGE                      8:8
#define GPIO_AC_SCR_02_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_02_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_02_0_G0W_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_02_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G7R_SHIFT)
#define GPIO_AC_SCR_02_0_G7R_RANGE                      7:7
#define GPIO_AC_SCR_02_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_02_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_02_0_G7R_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_02_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G6R_SHIFT)
#define GPIO_AC_SCR_02_0_G6R_RANGE                      6:6
#define GPIO_AC_SCR_02_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_02_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_02_0_G6R_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_02_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G5R_SHIFT)
#define GPIO_AC_SCR_02_0_G5R_RANGE                      5:5
#define GPIO_AC_SCR_02_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_02_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_02_0_G5R_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_02_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G4R_SHIFT)
#define GPIO_AC_SCR_02_0_G4R_RANGE                      4:4
#define GPIO_AC_SCR_02_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_02_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_02_0_G4R_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_02_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G3R_SHIFT)
#define GPIO_AC_SCR_02_0_G3R_RANGE                      3:3
#define GPIO_AC_SCR_02_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_02_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_02_0_G3R_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_02_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G2R_SHIFT)
#define GPIO_AC_SCR_02_0_G2R_RANGE                      2:2
#define GPIO_AC_SCR_02_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_02_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_02_0_G2R_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_02_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G1R_SHIFT)
#define GPIO_AC_SCR_02_0_G1R_RANGE                      1:1
#define GPIO_AC_SCR_02_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_02_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_02_0_G1R_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_02_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_02_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G0R_SHIFT)
#define GPIO_AC_SCR_02_0_G0R_RANGE                      0:0
#define GPIO_AC_SCR_02_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_02_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_02_0_G0R_WOFFSET                    0x0
#define GPIO_AC_SCR_02_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_02_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_02_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AC_VM_03_0
#define GPIO_AC_VM_03_0                 MK_ADDR_CONST(0x58)
#define GPIO_AC_VM_03_0_SECURE                  0x0
#define GPIO_AC_VM_03_0_DUAL                    0x0
#define GPIO_AC_VM_03_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_03_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_03_0_WORD_COUNT                      0x1
#define GPIO_AC_VM_03_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_03_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_03_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_03_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_VM_03_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM1_SHIFT)
#define GPIO_AC_VM_03_0_VM1_RANGE                       1:0
#define GPIO_AC_VM_03_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AC_VM_03_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_VM_03_0_VM1_WOFFSET                     0x0
#define GPIO_AC_VM_03_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_03_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AC_VM_03_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM2_SHIFT)
#define GPIO_AC_VM_03_0_VM2_RANGE                       3:2
#define GPIO_AC_VM_03_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AC_VM_03_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AC_VM_03_0_VM2_WOFFSET                     0x0
#define GPIO_AC_VM_03_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_03_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AC_VM_03_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM3_SHIFT)
#define GPIO_AC_VM_03_0_VM3_RANGE                       5:4
#define GPIO_AC_VM_03_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AC_VM_03_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AC_VM_03_0_VM3_WOFFSET                     0x0
#define GPIO_AC_VM_03_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_03_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AC_VM_03_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM4_SHIFT)
#define GPIO_AC_VM_03_0_VM4_RANGE                       7:6
#define GPIO_AC_VM_03_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_VM_03_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AC_VM_03_0_VM4_WOFFSET                     0x0
#define GPIO_AC_VM_03_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_03_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AC_VM_03_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM5_SHIFT)
#define GPIO_AC_VM_03_0_VM5_RANGE                       9:8
#define GPIO_AC_VM_03_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AC_VM_03_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AC_VM_03_0_VM5_WOFFSET                     0x0
#define GPIO_AC_VM_03_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_03_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AC_VM_03_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM6_SHIFT)
#define GPIO_AC_VM_03_0_VM6_RANGE                       11:10
#define GPIO_AC_VM_03_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AC_VM_03_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AC_VM_03_0_VM6_WOFFSET                     0x0
#define GPIO_AC_VM_03_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_03_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AC_VM_03_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM7_SHIFT)
#define GPIO_AC_VM_03_0_VM7_RANGE                       13:12
#define GPIO_AC_VM_03_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AC_VM_03_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AC_VM_03_0_VM7_WOFFSET                     0x0
#define GPIO_AC_VM_03_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_03_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AC_VM_03_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM8_SHIFT)
#define GPIO_AC_VM_03_0_VM8_RANGE                       15:14
#define GPIO_AC_VM_03_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AC_VM_03_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AC_VM_03_0_VM8_WOFFSET                     0x0
#define GPIO_AC_VM_03_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_03_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_03_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_SCR_03_0
#define GPIO_AC_SCR_03_0                        MK_ADDR_CONST(0x5c)
#define GPIO_AC_SCR_03_0_SECURE                         0x0
#define GPIO_AC_SCR_03_0_DUAL                   0x0
#define GPIO_AC_SCR_03_0_SCR                    0
#define GPIO_AC_SCR_03_0_SCRREG                         0
#define GPIO_AC_SCR_03_0_WORD_COUNT                     0x1
#define GPIO_AC_SCR_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_03_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_03_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_03_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_AC_SCR_03_0_SEC_LCK_RANGE                  29:29
#define GPIO_AC_SCR_03_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_03_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_03_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AC_SCR_03_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_03_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_AC_SCR_03_0_SEC_WEN_RANGE                  28:28
#define GPIO_AC_SCR_03_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_03_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_03_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AC_SCR_03_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_03_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_AC_SCR_03_0_SEC_REN_RANGE                  27:27
#define GPIO_AC_SCR_03_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_03_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_03_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AC_SCR_03_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_03_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_AC_SCR_03_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AC_SCR_03_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AC_SCR_03_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AC_SCR_03_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AC_SCR_03_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_03_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR7_SHIFT)
#define GPIO_AC_SCR_03_0_PR7_RANGE                      23:23
#define GPIO_AC_SCR_03_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_03_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_03_0_PR7_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_03_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR6_SHIFT)
#define GPIO_AC_SCR_03_0_PR6_RANGE                      22:22
#define GPIO_AC_SCR_03_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_03_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_03_0_PR6_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_03_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR5_SHIFT)
#define GPIO_AC_SCR_03_0_PR5_RANGE                      21:21
#define GPIO_AC_SCR_03_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_03_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_03_0_PR5_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_03_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR4_SHIFT)
#define GPIO_AC_SCR_03_0_PR4_RANGE                      20:20
#define GPIO_AC_SCR_03_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_03_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_03_0_PR4_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_03_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR3_SHIFT)
#define GPIO_AC_SCR_03_0_PR3_RANGE                      19:19
#define GPIO_AC_SCR_03_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_03_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_03_0_PR3_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_03_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR2_SHIFT)
#define GPIO_AC_SCR_03_0_PR2_RANGE                      18:18
#define GPIO_AC_SCR_03_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_03_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_03_0_PR2_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_03_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR1_SHIFT)
#define GPIO_AC_SCR_03_0_PR1_RANGE                      17:17
#define GPIO_AC_SCR_03_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_03_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_03_0_PR1_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_03_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR0_SHIFT)
#define GPIO_AC_SCR_03_0_PR0_RANGE                      16:16
#define GPIO_AC_SCR_03_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_03_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_03_0_PR0_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_03_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G7W_SHIFT)
#define GPIO_AC_SCR_03_0_G7W_RANGE                      15:15
#define GPIO_AC_SCR_03_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_03_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_03_0_G7W_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_03_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G6W_SHIFT)
#define GPIO_AC_SCR_03_0_G6W_RANGE                      14:14
#define GPIO_AC_SCR_03_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_03_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_03_0_G6W_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_03_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G5W_SHIFT)
#define GPIO_AC_SCR_03_0_G5W_RANGE                      13:13
#define GPIO_AC_SCR_03_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_03_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_03_0_G5W_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_03_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G4W_SHIFT)
#define GPIO_AC_SCR_03_0_G4W_RANGE                      12:12
#define GPIO_AC_SCR_03_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_03_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_03_0_G4W_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_03_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G3W_SHIFT)
#define GPIO_AC_SCR_03_0_G3W_RANGE                      11:11
#define GPIO_AC_SCR_03_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_03_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_03_0_G3W_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_03_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G2W_SHIFT)
#define GPIO_AC_SCR_03_0_G2W_RANGE                      10:10
#define GPIO_AC_SCR_03_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_03_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_03_0_G2W_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_03_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G1W_SHIFT)
#define GPIO_AC_SCR_03_0_G1W_RANGE                      9:9
#define GPIO_AC_SCR_03_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_03_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_03_0_G1W_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_03_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G0W_SHIFT)
#define GPIO_AC_SCR_03_0_G0W_RANGE                      8:8
#define GPIO_AC_SCR_03_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_03_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_03_0_G0W_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_03_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G7R_SHIFT)
#define GPIO_AC_SCR_03_0_G7R_RANGE                      7:7
#define GPIO_AC_SCR_03_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_03_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_03_0_G7R_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_03_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G6R_SHIFT)
#define GPIO_AC_SCR_03_0_G6R_RANGE                      6:6
#define GPIO_AC_SCR_03_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_03_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_03_0_G6R_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_03_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G5R_SHIFT)
#define GPIO_AC_SCR_03_0_G5R_RANGE                      5:5
#define GPIO_AC_SCR_03_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_03_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_03_0_G5R_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_03_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G4R_SHIFT)
#define GPIO_AC_SCR_03_0_G4R_RANGE                      4:4
#define GPIO_AC_SCR_03_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_03_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_03_0_G4R_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_03_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G3R_SHIFT)
#define GPIO_AC_SCR_03_0_G3R_RANGE                      3:3
#define GPIO_AC_SCR_03_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_03_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_03_0_G3R_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_03_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G2R_SHIFT)
#define GPIO_AC_SCR_03_0_G2R_RANGE                      2:2
#define GPIO_AC_SCR_03_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_03_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_03_0_G2R_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_03_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G1R_SHIFT)
#define GPIO_AC_SCR_03_0_G1R_RANGE                      1:1
#define GPIO_AC_SCR_03_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_03_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_03_0_G1R_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_03_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_03_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G0R_SHIFT)
#define GPIO_AC_SCR_03_0_G0R_RANGE                      0:0
#define GPIO_AC_SCR_03_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_03_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_03_0_G0R_WOFFSET                    0x0
#define GPIO_AC_SCR_03_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_03_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_03_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AC_VM_04_0
#define GPIO_AC_VM_04_0                 MK_ADDR_CONST(0x60)
#define GPIO_AC_VM_04_0_SECURE                  0x0
#define GPIO_AC_VM_04_0_DUAL                    0x0
#define GPIO_AC_VM_04_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_04_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_04_0_WORD_COUNT                      0x1
#define GPIO_AC_VM_04_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_04_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_04_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_04_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_VM_04_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM1_SHIFT)
#define GPIO_AC_VM_04_0_VM1_RANGE                       1:0
#define GPIO_AC_VM_04_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AC_VM_04_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_VM_04_0_VM1_WOFFSET                     0x0
#define GPIO_AC_VM_04_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_04_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AC_VM_04_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM2_SHIFT)
#define GPIO_AC_VM_04_0_VM2_RANGE                       3:2
#define GPIO_AC_VM_04_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AC_VM_04_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AC_VM_04_0_VM2_WOFFSET                     0x0
#define GPIO_AC_VM_04_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_04_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AC_VM_04_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM3_SHIFT)
#define GPIO_AC_VM_04_0_VM3_RANGE                       5:4
#define GPIO_AC_VM_04_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AC_VM_04_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AC_VM_04_0_VM3_WOFFSET                     0x0
#define GPIO_AC_VM_04_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_04_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AC_VM_04_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM4_SHIFT)
#define GPIO_AC_VM_04_0_VM4_RANGE                       7:6
#define GPIO_AC_VM_04_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_VM_04_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AC_VM_04_0_VM4_WOFFSET                     0x0
#define GPIO_AC_VM_04_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_04_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AC_VM_04_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM5_SHIFT)
#define GPIO_AC_VM_04_0_VM5_RANGE                       9:8
#define GPIO_AC_VM_04_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AC_VM_04_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AC_VM_04_0_VM5_WOFFSET                     0x0
#define GPIO_AC_VM_04_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_04_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AC_VM_04_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM6_SHIFT)
#define GPIO_AC_VM_04_0_VM6_RANGE                       11:10
#define GPIO_AC_VM_04_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AC_VM_04_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AC_VM_04_0_VM6_WOFFSET                     0x0
#define GPIO_AC_VM_04_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_04_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AC_VM_04_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM7_SHIFT)
#define GPIO_AC_VM_04_0_VM7_RANGE                       13:12
#define GPIO_AC_VM_04_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AC_VM_04_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AC_VM_04_0_VM7_WOFFSET                     0x0
#define GPIO_AC_VM_04_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_04_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AC_VM_04_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM8_SHIFT)
#define GPIO_AC_VM_04_0_VM8_RANGE                       15:14
#define GPIO_AC_VM_04_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AC_VM_04_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AC_VM_04_0_VM8_WOFFSET                     0x0
#define GPIO_AC_VM_04_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_04_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_04_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_SCR_04_0
#define GPIO_AC_SCR_04_0                        MK_ADDR_CONST(0x64)
#define GPIO_AC_SCR_04_0_SECURE                         0x0
#define GPIO_AC_SCR_04_0_DUAL                   0x0
#define GPIO_AC_SCR_04_0_SCR                    0
#define GPIO_AC_SCR_04_0_SCRREG                         0
#define GPIO_AC_SCR_04_0_WORD_COUNT                     0x1
#define GPIO_AC_SCR_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_04_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_04_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_04_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_AC_SCR_04_0_SEC_LCK_RANGE                  29:29
#define GPIO_AC_SCR_04_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_04_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_04_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AC_SCR_04_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_04_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_AC_SCR_04_0_SEC_WEN_RANGE                  28:28
#define GPIO_AC_SCR_04_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_04_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_04_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AC_SCR_04_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_04_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_AC_SCR_04_0_SEC_REN_RANGE                  27:27
#define GPIO_AC_SCR_04_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_04_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_04_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AC_SCR_04_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_04_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_AC_SCR_04_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AC_SCR_04_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AC_SCR_04_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_04_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AC_SCR_04_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AC_SCR_04_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_04_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR7_SHIFT)
#define GPIO_AC_SCR_04_0_PR7_RANGE                      23:23
#define GPIO_AC_SCR_04_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_04_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_04_0_PR7_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_04_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR6_SHIFT)
#define GPIO_AC_SCR_04_0_PR6_RANGE                      22:22
#define GPIO_AC_SCR_04_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_04_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_04_0_PR6_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_04_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR5_SHIFT)
#define GPIO_AC_SCR_04_0_PR5_RANGE                      21:21
#define GPIO_AC_SCR_04_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_04_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_04_0_PR5_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_04_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR4_SHIFT)
#define GPIO_AC_SCR_04_0_PR4_RANGE                      20:20
#define GPIO_AC_SCR_04_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_04_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_04_0_PR4_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_04_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR3_SHIFT)
#define GPIO_AC_SCR_04_0_PR3_RANGE                      19:19
#define GPIO_AC_SCR_04_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_04_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_04_0_PR3_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_04_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR2_SHIFT)
#define GPIO_AC_SCR_04_0_PR2_RANGE                      18:18
#define GPIO_AC_SCR_04_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_04_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_04_0_PR2_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_04_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR1_SHIFT)
#define GPIO_AC_SCR_04_0_PR1_RANGE                      17:17
#define GPIO_AC_SCR_04_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_04_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_04_0_PR1_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_04_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR0_SHIFT)
#define GPIO_AC_SCR_04_0_PR0_RANGE                      16:16
#define GPIO_AC_SCR_04_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_04_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_04_0_PR0_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_04_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G7W_SHIFT)
#define GPIO_AC_SCR_04_0_G7W_RANGE                      15:15
#define GPIO_AC_SCR_04_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_04_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_04_0_G7W_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_04_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G6W_SHIFT)
#define GPIO_AC_SCR_04_0_G6W_RANGE                      14:14
#define GPIO_AC_SCR_04_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_04_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_04_0_G6W_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_04_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G5W_SHIFT)
#define GPIO_AC_SCR_04_0_G5W_RANGE                      13:13
#define GPIO_AC_SCR_04_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_04_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_04_0_G5W_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_04_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G4W_SHIFT)
#define GPIO_AC_SCR_04_0_G4W_RANGE                      12:12
#define GPIO_AC_SCR_04_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_04_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_04_0_G4W_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_04_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G3W_SHIFT)
#define GPIO_AC_SCR_04_0_G3W_RANGE                      11:11
#define GPIO_AC_SCR_04_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_04_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_04_0_G3W_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_04_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G2W_SHIFT)
#define GPIO_AC_SCR_04_0_G2W_RANGE                      10:10
#define GPIO_AC_SCR_04_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_04_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_04_0_G2W_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_04_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G1W_SHIFT)
#define GPIO_AC_SCR_04_0_G1W_RANGE                      9:9
#define GPIO_AC_SCR_04_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_04_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_04_0_G1W_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_04_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G0W_SHIFT)
#define GPIO_AC_SCR_04_0_G0W_RANGE                      8:8
#define GPIO_AC_SCR_04_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_04_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_04_0_G0W_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_04_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G7R_SHIFT)
#define GPIO_AC_SCR_04_0_G7R_RANGE                      7:7
#define GPIO_AC_SCR_04_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_04_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_04_0_G7R_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_04_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G6R_SHIFT)
#define GPIO_AC_SCR_04_0_G6R_RANGE                      6:6
#define GPIO_AC_SCR_04_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_04_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_04_0_G6R_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_04_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G5R_SHIFT)
#define GPIO_AC_SCR_04_0_G5R_RANGE                      5:5
#define GPIO_AC_SCR_04_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_04_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_04_0_G5R_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_04_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G4R_SHIFT)
#define GPIO_AC_SCR_04_0_G4R_RANGE                      4:4
#define GPIO_AC_SCR_04_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_04_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_04_0_G4R_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_04_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G3R_SHIFT)
#define GPIO_AC_SCR_04_0_G3R_RANGE                      3:3
#define GPIO_AC_SCR_04_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_04_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_04_0_G3R_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_04_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G2R_SHIFT)
#define GPIO_AC_SCR_04_0_G2R_RANGE                      2:2
#define GPIO_AC_SCR_04_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_04_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_04_0_G2R_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_04_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G1R_SHIFT)
#define GPIO_AC_SCR_04_0_G1R_RANGE                      1:1
#define GPIO_AC_SCR_04_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_04_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_04_0_G1R_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_04_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_04_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G0R_SHIFT)
#define GPIO_AC_SCR_04_0_G0R_RANGE                      0:0
#define GPIO_AC_SCR_04_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_04_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_04_0_G0R_WOFFSET                    0x0
#define GPIO_AC_SCR_04_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_04_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_04_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AC_VM_05_0
#define GPIO_AC_VM_05_0                 MK_ADDR_CONST(0x68)
#define GPIO_AC_VM_05_0_SECURE                  0x0
#define GPIO_AC_VM_05_0_DUAL                    0x0
#define GPIO_AC_VM_05_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_05_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_05_0_WORD_COUNT                      0x1
#define GPIO_AC_VM_05_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_05_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_05_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_05_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_VM_05_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM1_SHIFT)
#define GPIO_AC_VM_05_0_VM1_RANGE                       1:0
#define GPIO_AC_VM_05_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AC_VM_05_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_VM_05_0_VM1_WOFFSET                     0x0
#define GPIO_AC_VM_05_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_05_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AC_VM_05_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM2_SHIFT)
#define GPIO_AC_VM_05_0_VM2_RANGE                       3:2
#define GPIO_AC_VM_05_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AC_VM_05_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AC_VM_05_0_VM2_WOFFSET                     0x0
#define GPIO_AC_VM_05_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_05_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AC_VM_05_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM3_SHIFT)
#define GPIO_AC_VM_05_0_VM3_RANGE                       5:4
#define GPIO_AC_VM_05_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AC_VM_05_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AC_VM_05_0_VM3_WOFFSET                     0x0
#define GPIO_AC_VM_05_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_05_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AC_VM_05_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM4_SHIFT)
#define GPIO_AC_VM_05_0_VM4_RANGE                       7:6
#define GPIO_AC_VM_05_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_VM_05_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AC_VM_05_0_VM4_WOFFSET                     0x0
#define GPIO_AC_VM_05_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_05_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AC_VM_05_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM5_SHIFT)
#define GPIO_AC_VM_05_0_VM5_RANGE                       9:8
#define GPIO_AC_VM_05_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AC_VM_05_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AC_VM_05_0_VM5_WOFFSET                     0x0
#define GPIO_AC_VM_05_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_05_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AC_VM_05_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM6_SHIFT)
#define GPIO_AC_VM_05_0_VM6_RANGE                       11:10
#define GPIO_AC_VM_05_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AC_VM_05_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AC_VM_05_0_VM6_WOFFSET                     0x0
#define GPIO_AC_VM_05_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_05_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AC_VM_05_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM7_SHIFT)
#define GPIO_AC_VM_05_0_VM7_RANGE                       13:12
#define GPIO_AC_VM_05_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AC_VM_05_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AC_VM_05_0_VM7_WOFFSET                     0x0
#define GPIO_AC_VM_05_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_05_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AC_VM_05_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM8_SHIFT)
#define GPIO_AC_VM_05_0_VM8_RANGE                       15:14
#define GPIO_AC_VM_05_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AC_VM_05_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AC_VM_05_0_VM8_WOFFSET                     0x0
#define GPIO_AC_VM_05_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_05_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_05_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_SCR_05_0
#define GPIO_AC_SCR_05_0                        MK_ADDR_CONST(0x6c)
#define GPIO_AC_SCR_05_0_SECURE                         0x0
#define GPIO_AC_SCR_05_0_DUAL                   0x0
#define GPIO_AC_SCR_05_0_SCR                    0
#define GPIO_AC_SCR_05_0_SCRREG                         0
#define GPIO_AC_SCR_05_0_WORD_COUNT                     0x1
#define GPIO_AC_SCR_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_05_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_05_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_05_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_AC_SCR_05_0_SEC_LCK_RANGE                  29:29
#define GPIO_AC_SCR_05_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_05_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_05_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AC_SCR_05_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_05_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_AC_SCR_05_0_SEC_WEN_RANGE                  28:28
#define GPIO_AC_SCR_05_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_05_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_05_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AC_SCR_05_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_05_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_AC_SCR_05_0_SEC_REN_RANGE                  27:27
#define GPIO_AC_SCR_05_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_05_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_05_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AC_SCR_05_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_05_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_AC_SCR_05_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AC_SCR_05_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AC_SCR_05_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_05_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AC_SCR_05_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AC_SCR_05_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_05_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR7_SHIFT)
#define GPIO_AC_SCR_05_0_PR7_RANGE                      23:23
#define GPIO_AC_SCR_05_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_05_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_05_0_PR7_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_05_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR6_SHIFT)
#define GPIO_AC_SCR_05_0_PR6_RANGE                      22:22
#define GPIO_AC_SCR_05_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_05_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_05_0_PR6_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_05_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR5_SHIFT)
#define GPIO_AC_SCR_05_0_PR5_RANGE                      21:21
#define GPIO_AC_SCR_05_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_05_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_05_0_PR5_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_05_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR4_SHIFT)
#define GPIO_AC_SCR_05_0_PR4_RANGE                      20:20
#define GPIO_AC_SCR_05_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_05_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_05_0_PR4_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_05_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR3_SHIFT)
#define GPIO_AC_SCR_05_0_PR3_RANGE                      19:19
#define GPIO_AC_SCR_05_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_05_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_05_0_PR3_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_05_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR2_SHIFT)
#define GPIO_AC_SCR_05_0_PR2_RANGE                      18:18
#define GPIO_AC_SCR_05_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_05_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_05_0_PR2_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_05_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR1_SHIFT)
#define GPIO_AC_SCR_05_0_PR1_RANGE                      17:17
#define GPIO_AC_SCR_05_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_05_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_05_0_PR1_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_05_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR0_SHIFT)
#define GPIO_AC_SCR_05_0_PR0_RANGE                      16:16
#define GPIO_AC_SCR_05_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_05_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_05_0_PR0_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_05_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G7W_SHIFT)
#define GPIO_AC_SCR_05_0_G7W_RANGE                      15:15
#define GPIO_AC_SCR_05_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_05_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_05_0_G7W_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_05_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G6W_SHIFT)
#define GPIO_AC_SCR_05_0_G6W_RANGE                      14:14
#define GPIO_AC_SCR_05_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_05_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_05_0_G6W_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_05_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G5W_SHIFT)
#define GPIO_AC_SCR_05_0_G5W_RANGE                      13:13
#define GPIO_AC_SCR_05_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_05_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_05_0_G5W_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_05_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G4W_SHIFT)
#define GPIO_AC_SCR_05_0_G4W_RANGE                      12:12
#define GPIO_AC_SCR_05_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_05_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_05_0_G4W_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_05_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G3W_SHIFT)
#define GPIO_AC_SCR_05_0_G3W_RANGE                      11:11
#define GPIO_AC_SCR_05_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_05_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_05_0_G3W_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_05_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G2W_SHIFT)
#define GPIO_AC_SCR_05_0_G2W_RANGE                      10:10
#define GPIO_AC_SCR_05_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_05_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_05_0_G2W_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_05_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G1W_SHIFT)
#define GPIO_AC_SCR_05_0_G1W_RANGE                      9:9
#define GPIO_AC_SCR_05_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_05_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_05_0_G1W_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_05_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G0W_SHIFT)
#define GPIO_AC_SCR_05_0_G0W_RANGE                      8:8
#define GPIO_AC_SCR_05_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_05_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_05_0_G0W_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_05_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G7R_SHIFT)
#define GPIO_AC_SCR_05_0_G7R_RANGE                      7:7
#define GPIO_AC_SCR_05_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_05_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_05_0_G7R_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_05_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G6R_SHIFT)
#define GPIO_AC_SCR_05_0_G6R_RANGE                      6:6
#define GPIO_AC_SCR_05_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_05_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_05_0_G6R_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_05_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G5R_SHIFT)
#define GPIO_AC_SCR_05_0_G5R_RANGE                      5:5
#define GPIO_AC_SCR_05_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_05_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_05_0_G5R_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_05_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G4R_SHIFT)
#define GPIO_AC_SCR_05_0_G4R_RANGE                      4:4
#define GPIO_AC_SCR_05_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_05_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_05_0_G4R_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_05_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G3R_SHIFT)
#define GPIO_AC_SCR_05_0_G3R_RANGE                      3:3
#define GPIO_AC_SCR_05_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_05_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_05_0_G3R_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_05_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G2R_SHIFT)
#define GPIO_AC_SCR_05_0_G2R_RANGE                      2:2
#define GPIO_AC_SCR_05_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_05_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_05_0_G2R_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_05_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G1R_SHIFT)
#define GPIO_AC_SCR_05_0_G1R_RANGE                      1:1
#define GPIO_AC_SCR_05_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_05_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_05_0_G1R_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_05_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_05_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G0R_SHIFT)
#define GPIO_AC_SCR_05_0_G0R_RANGE                      0:0
#define GPIO_AC_SCR_05_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_05_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_05_0_G0R_WOFFSET                    0x0
#define GPIO_AC_SCR_05_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_05_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_05_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AC_VM_06_0
#define GPIO_AC_VM_06_0                 MK_ADDR_CONST(0x70)
#define GPIO_AC_VM_06_0_SECURE                  0x0
#define GPIO_AC_VM_06_0_DUAL                    0x0
#define GPIO_AC_VM_06_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_06_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_06_0_WORD_COUNT                      0x1
#define GPIO_AC_VM_06_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_06_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_06_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_06_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_VM_06_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM1_SHIFT)
#define GPIO_AC_VM_06_0_VM1_RANGE                       1:0
#define GPIO_AC_VM_06_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AC_VM_06_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_VM_06_0_VM1_WOFFSET                     0x0
#define GPIO_AC_VM_06_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_06_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AC_VM_06_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM2_SHIFT)
#define GPIO_AC_VM_06_0_VM2_RANGE                       3:2
#define GPIO_AC_VM_06_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AC_VM_06_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AC_VM_06_0_VM2_WOFFSET                     0x0
#define GPIO_AC_VM_06_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_06_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AC_VM_06_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM3_SHIFT)
#define GPIO_AC_VM_06_0_VM3_RANGE                       5:4
#define GPIO_AC_VM_06_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AC_VM_06_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AC_VM_06_0_VM3_WOFFSET                     0x0
#define GPIO_AC_VM_06_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_06_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AC_VM_06_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM4_SHIFT)
#define GPIO_AC_VM_06_0_VM4_RANGE                       7:6
#define GPIO_AC_VM_06_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_VM_06_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AC_VM_06_0_VM4_WOFFSET                     0x0
#define GPIO_AC_VM_06_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_06_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AC_VM_06_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM5_SHIFT)
#define GPIO_AC_VM_06_0_VM5_RANGE                       9:8
#define GPIO_AC_VM_06_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AC_VM_06_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AC_VM_06_0_VM5_WOFFSET                     0x0
#define GPIO_AC_VM_06_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_06_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AC_VM_06_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM6_SHIFT)
#define GPIO_AC_VM_06_0_VM6_RANGE                       11:10
#define GPIO_AC_VM_06_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AC_VM_06_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AC_VM_06_0_VM6_WOFFSET                     0x0
#define GPIO_AC_VM_06_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_06_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AC_VM_06_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM7_SHIFT)
#define GPIO_AC_VM_06_0_VM7_RANGE                       13:12
#define GPIO_AC_VM_06_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AC_VM_06_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AC_VM_06_0_VM7_WOFFSET                     0x0
#define GPIO_AC_VM_06_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_06_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AC_VM_06_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM8_SHIFT)
#define GPIO_AC_VM_06_0_VM8_RANGE                       15:14
#define GPIO_AC_VM_06_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AC_VM_06_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AC_VM_06_0_VM8_WOFFSET                     0x0
#define GPIO_AC_VM_06_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_06_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_06_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_SCR_06_0
#define GPIO_AC_SCR_06_0                        MK_ADDR_CONST(0x74)
#define GPIO_AC_SCR_06_0_SECURE                         0x0
#define GPIO_AC_SCR_06_0_DUAL                   0x0
#define GPIO_AC_SCR_06_0_SCR                    0
#define GPIO_AC_SCR_06_0_SCRREG                         0
#define GPIO_AC_SCR_06_0_WORD_COUNT                     0x1
#define GPIO_AC_SCR_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_06_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_06_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_06_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_AC_SCR_06_0_SEC_LCK_RANGE                  29:29
#define GPIO_AC_SCR_06_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_06_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_06_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AC_SCR_06_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_06_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_AC_SCR_06_0_SEC_WEN_RANGE                  28:28
#define GPIO_AC_SCR_06_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_06_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_06_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AC_SCR_06_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_06_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_AC_SCR_06_0_SEC_REN_RANGE                  27:27
#define GPIO_AC_SCR_06_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_06_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_06_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AC_SCR_06_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_06_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_AC_SCR_06_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AC_SCR_06_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AC_SCR_06_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_06_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AC_SCR_06_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AC_SCR_06_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_06_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR7_SHIFT)
#define GPIO_AC_SCR_06_0_PR7_RANGE                      23:23
#define GPIO_AC_SCR_06_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_06_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_06_0_PR7_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_06_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR6_SHIFT)
#define GPIO_AC_SCR_06_0_PR6_RANGE                      22:22
#define GPIO_AC_SCR_06_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_06_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_06_0_PR6_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_06_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR5_SHIFT)
#define GPIO_AC_SCR_06_0_PR5_RANGE                      21:21
#define GPIO_AC_SCR_06_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_06_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_06_0_PR5_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_06_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR4_SHIFT)
#define GPIO_AC_SCR_06_0_PR4_RANGE                      20:20
#define GPIO_AC_SCR_06_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_06_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_06_0_PR4_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_06_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR3_SHIFT)
#define GPIO_AC_SCR_06_0_PR3_RANGE                      19:19
#define GPIO_AC_SCR_06_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_06_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_06_0_PR3_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_06_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR2_SHIFT)
#define GPIO_AC_SCR_06_0_PR2_RANGE                      18:18
#define GPIO_AC_SCR_06_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_06_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_06_0_PR2_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_06_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR1_SHIFT)
#define GPIO_AC_SCR_06_0_PR1_RANGE                      17:17
#define GPIO_AC_SCR_06_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_06_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_06_0_PR1_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_06_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR0_SHIFT)
#define GPIO_AC_SCR_06_0_PR0_RANGE                      16:16
#define GPIO_AC_SCR_06_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_06_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_06_0_PR0_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_06_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G7W_SHIFT)
#define GPIO_AC_SCR_06_0_G7W_RANGE                      15:15
#define GPIO_AC_SCR_06_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_06_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_06_0_G7W_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_06_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G6W_SHIFT)
#define GPIO_AC_SCR_06_0_G6W_RANGE                      14:14
#define GPIO_AC_SCR_06_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_06_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_06_0_G6W_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_06_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G5W_SHIFT)
#define GPIO_AC_SCR_06_0_G5W_RANGE                      13:13
#define GPIO_AC_SCR_06_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_06_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_06_0_G5W_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_06_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G4W_SHIFT)
#define GPIO_AC_SCR_06_0_G4W_RANGE                      12:12
#define GPIO_AC_SCR_06_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_06_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_06_0_G4W_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_06_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G3W_SHIFT)
#define GPIO_AC_SCR_06_0_G3W_RANGE                      11:11
#define GPIO_AC_SCR_06_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_06_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_06_0_G3W_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_06_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G2W_SHIFT)
#define GPIO_AC_SCR_06_0_G2W_RANGE                      10:10
#define GPIO_AC_SCR_06_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_06_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_06_0_G2W_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_06_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G1W_SHIFT)
#define GPIO_AC_SCR_06_0_G1W_RANGE                      9:9
#define GPIO_AC_SCR_06_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_06_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_06_0_G1W_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_06_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G0W_SHIFT)
#define GPIO_AC_SCR_06_0_G0W_RANGE                      8:8
#define GPIO_AC_SCR_06_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_06_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_06_0_G0W_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_06_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G7R_SHIFT)
#define GPIO_AC_SCR_06_0_G7R_RANGE                      7:7
#define GPIO_AC_SCR_06_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_06_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_06_0_G7R_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_06_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G6R_SHIFT)
#define GPIO_AC_SCR_06_0_G6R_RANGE                      6:6
#define GPIO_AC_SCR_06_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_06_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_06_0_G6R_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_06_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G5R_SHIFT)
#define GPIO_AC_SCR_06_0_G5R_RANGE                      5:5
#define GPIO_AC_SCR_06_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_06_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_06_0_G5R_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_06_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G4R_SHIFT)
#define GPIO_AC_SCR_06_0_G4R_RANGE                      4:4
#define GPIO_AC_SCR_06_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_06_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_06_0_G4R_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_06_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G3R_SHIFT)
#define GPIO_AC_SCR_06_0_G3R_RANGE                      3:3
#define GPIO_AC_SCR_06_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_06_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_06_0_G3R_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_06_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G2R_SHIFT)
#define GPIO_AC_SCR_06_0_G2R_RANGE                      2:2
#define GPIO_AC_SCR_06_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_06_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_06_0_G2R_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_06_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G1R_SHIFT)
#define GPIO_AC_SCR_06_0_G1R_RANGE                      1:1
#define GPIO_AC_SCR_06_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_06_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_06_0_G1R_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_06_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_06_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G0R_SHIFT)
#define GPIO_AC_SCR_06_0_G0R_RANGE                      0:0
#define GPIO_AC_SCR_06_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_06_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_06_0_G0R_WOFFSET                    0x0
#define GPIO_AC_SCR_06_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_06_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_06_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AC_VM_07_0
#define GPIO_AC_VM_07_0                 MK_ADDR_CONST(0x78)
#define GPIO_AC_VM_07_0_SECURE                  0x0
#define GPIO_AC_VM_07_0_DUAL                    0x0
#define GPIO_AC_VM_07_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_07_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AC_VM_07_0_WORD_COUNT                      0x1
#define GPIO_AC_VM_07_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_07_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_07_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AC_VM_07_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_VM_07_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM1_SHIFT)
#define GPIO_AC_VM_07_0_VM1_RANGE                       1:0
#define GPIO_AC_VM_07_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AC_VM_07_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_VM_07_0_VM1_WOFFSET                     0x0
#define GPIO_AC_VM_07_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_07_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AC_VM_07_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM2_SHIFT)
#define GPIO_AC_VM_07_0_VM2_RANGE                       3:2
#define GPIO_AC_VM_07_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AC_VM_07_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AC_VM_07_0_VM2_WOFFSET                     0x0
#define GPIO_AC_VM_07_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_07_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AC_VM_07_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM3_SHIFT)
#define GPIO_AC_VM_07_0_VM3_RANGE                       5:4
#define GPIO_AC_VM_07_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AC_VM_07_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AC_VM_07_0_VM3_WOFFSET                     0x0
#define GPIO_AC_VM_07_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_07_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AC_VM_07_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM4_SHIFT)
#define GPIO_AC_VM_07_0_VM4_RANGE                       7:6
#define GPIO_AC_VM_07_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_VM_07_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AC_VM_07_0_VM4_WOFFSET                     0x0
#define GPIO_AC_VM_07_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_07_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AC_VM_07_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM5_SHIFT)
#define GPIO_AC_VM_07_0_VM5_RANGE                       9:8
#define GPIO_AC_VM_07_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AC_VM_07_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AC_VM_07_0_VM5_WOFFSET                     0x0
#define GPIO_AC_VM_07_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_07_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AC_VM_07_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM6_SHIFT)
#define GPIO_AC_VM_07_0_VM6_RANGE                       11:10
#define GPIO_AC_VM_07_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AC_VM_07_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AC_VM_07_0_VM6_WOFFSET                     0x0
#define GPIO_AC_VM_07_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_07_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AC_VM_07_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM7_SHIFT)
#define GPIO_AC_VM_07_0_VM7_RANGE                       13:12
#define GPIO_AC_VM_07_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AC_VM_07_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AC_VM_07_0_VM7_WOFFSET                     0x0
#define GPIO_AC_VM_07_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AC_VM_07_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AC_VM_07_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM8_SHIFT)
#define GPIO_AC_VM_07_0_VM8_RANGE                       15:14
#define GPIO_AC_VM_07_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AC_VM_07_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AC_VM_07_0_VM8_WOFFSET                     0x0
#define GPIO_AC_VM_07_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AC_VM_07_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_VM_07_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_SCR_07_0
#define GPIO_AC_SCR_07_0                        MK_ADDR_CONST(0x7c)
#define GPIO_AC_SCR_07_0_SECURE                         0x0
#define GPIO_AC_SCR_07_0_DUAL                   0x0
#define GPIO_AC_SCR_07_0_SCR                    0
#define GPIO_AC_SCR_07_0_SCRREG                         0
#define GPIO_AC_SCR_07_0_WORD_COUNT                     0x1
#define GPIO_AC_SCR_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_07_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AC_SCR_07_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_07_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_AC_SCR_07_0_SEC_LCK_RANGE                  29:29
#define GPIO_AC_SCR_07_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_07_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AC_SCR_07_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AC_SCR_07_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_07_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_AC_SCR_07_0_SEC_WEN_RANGE                  28:28
#define GPIO_AC_SCR_07_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_07_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AC_SCR_07_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AC_SCR_07_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_07_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_AC_SCR_07_0_SEC_REN_RANGE                  27:27
#define GPIO_AC_SCR_07_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_07_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AC_SCR_07_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AC_SCR_07_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_07_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_AC_SCR_07_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AC_SCR_07_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AC_SCR_07_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AC_SCR_07_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AC_SCR_07_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AC_SCR_07_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_07_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR7_SHIFT)
#define GPIO_AC_SCR_07_0_PR7_RANGE                      23:23
#define GPIO_AC_SCR_07_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_07_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AC_SCR_07_0_PR7_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_07_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR6_SHIFT)
#define GPIO_AC_SCR_07_0_PR6_RANGE                      22:22
#define GPIO_AC_SCR_07_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_07_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AC_SCR_07_0_PR6_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_07_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR5_SHIFT)
#define GPIO_AC_SCR_07_0_PR5_RANGE                      21:21
#define GPIO_AC_SCR_07_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_07_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AC_SCR_07_0_PR5_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_07_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR4_SHIFT)
#define GPIO_AC_SCR_07_0_PR4_RANGE                      20:20
#define GPIO_AC_SCR_07_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_07_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AC_SCR_07_0_PR4_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_07_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR3_SHIFT)
#define GPIO_AC_SCR_07_0_PR3_RANGE                      19:19
#define GPIO_AC_SCR_07_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_07_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AC_SCR_07_0_PR3_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_07_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR2_SHIFT)
#define GPIO_AC_SCR_07_0_PR2_RANGE                      18:18
#define GPIO_AC_SCR_07_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_07_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AC_SCR_07_0_PR2_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_07_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR1_SHIFT)
#define GPIO_AC_SCR_07_0_PR1_RANGE                      17:17
#define GPIO_AC_SCR_07_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_07_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AC_SCR_07_0_PR1_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_07_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR0_SHIFT)
#define GPIO_AC_SCR_07_0_PR0_RANGE                      16:16
#define GPIO_AC_SCR_07_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_07_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AC_SCR_07_0_PR0_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_07_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G7W_SHIFT)
#define GPIO_AC_SCR_07_0_G7W_RANGE                      15:15
#define GPIO_AC_SCR_07_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_07_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AC_SCR_07_0_G7W_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_07_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G6W_SHIFT)
#define GPIO_AC_SCR_07_0_G6W_RANGE                      14:14
#define GPIO_AC_SCR_07_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_07_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AC_SCR_07_0_G6W_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_07_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G5W_SHIFT)
#define GPIO_AC_SCR_07_0_G5W_RANGE                      13:13
#define GPIO_AC_SCR_07_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_07_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AC_SCR_07_0_G5W_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_07_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G4W_SHIFT)
#define GPIO_AC_SCR_07_0_G4W_RANGE                      12:12
#define GPIO_AC_SCR_07_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_07_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AC_SCR_07_0_G4W_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_07_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G3W_SHIFT)
#define GPIO_AC_SCR_07_0_G3W_RANGE                      11:11
#define GPIO_AC_SCR_07_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_07_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AC_SCR_07_0_G3W_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_07_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G2W_SHIFT)
#define GPIO_AC_SCR_07_0_G2W_RANGE                      10:10
#define GPIO_AC_SCR_07_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_07_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AC_SCR_07_0_G2W_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_07_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G1W_SHIFT)
#define GPIO_AC_SCR_07_0_G1W_RANGE                      9:9
#define GPIO_AC_SCR_07_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_07_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AC_SCR_07_0_G1W_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_07_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G0W_SHIFT)
#define GPIO_AC_SCR_07_0_G0W_RANGE                      8:8
#define GPIO_AC_SCR_07_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_07_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AC_SCR_07_0_G0W_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_07_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G7R_SHIFT)
#define GPIO_AC_SCR_07_0_G7R_RANGE                      7:7
#define GPIO_AC_SCR_07_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_07_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AC_SCR_07_0_G7R_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_07_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G6R_SHIFT)
#define GPIO_AC_SCR_07_0_G6R_RANGE                      6:6
#define GPIO_AC_SCR_07_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_07_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AC_SCR_07_0_G6R_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_07_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G5R_SHIFT)
#define GPIO_AC_SCR_07_0_G5R_RANGE                      5:5
#define GPIO_AC_SCR_07_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_07_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_SCR_07_0_G5R_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_07_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G4R_SHIFT)
#define GPIO_AC_SCR_07_0_G4R_RANGE                      4:4
#define GPIO_AC_SCR_07_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_07_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AC_SCR_07_0_G4R_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_07_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G3R_SHIFT)
#define GPIO_AC_SCR_07_0_G3R_RANGE                      3:3
#define GPIO_AC_SCR_07_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_07_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AC_SCR_07_0_G3R_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_07_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G2R_SHIFT)
#define GPIO_AC_SCR_07_0_G2R_RANGE                      2:2
#define GPIO_AC_SCR_07_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_07_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AC_SCR_07_0_G2R_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_07_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G1R_SHIFT)
#define GPIO_AC_SCR_07_0_G1R_RANGE                      1:1
#define GPIO_AC_SCR_07_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_07_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AC_SCR_07_0_G1R_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AC_SCR_07_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_07_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G0R_SHIFT)
#define GPIO_AC_SCR_07_0_G0R_RANGE                      0:0
#define GPIO_AC_SCR_07_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_07_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_SCR_07_0_G0R_WOFFSET                    0x0
#define GPIO_AC_SCR_07_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_SCR_07_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AC_SCR_07_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AD_VM_00_0
#define GPIO_AD_VM_00_0                 MK_ADDR_CONST(0x80)
#define GPIO_AD_VM_00_0_SECURE                  0x0
#define GPIO_AD_VM_00_0_DUAL                    0x0
#define GPIO_AD_VM_00_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AD_VM_00_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AD_VM_00_0_WORD_COUNT                      0x1
#define GPIO_AD_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM1_SHIFT)
#define GPIO_AD_VM_00_0_VM1_RANGE                       1:0
#define GPIO_AD_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AD_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_AD_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AD_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM2_SHIFT)
#define GPIO_AD_VM_00_0_VM2_RANGE                       3:2
#define GPIO_AD_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AD_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_AD_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AD_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM3_SHIFT)
#define GPIO_AD_VM_00_0_VM3_RANGE                       5:4
#define GPIO_AD_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AD_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AD_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_AD_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AD_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM4_SHIFT)
#define GPIO_AD_VM_00_0_VM4_RANGE                       7:6
#define GPIO_AD_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AD_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AD_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_AD_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AD_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM5_SHIFT)
#define GPIO_AD_VM_00_0_VM5_RANGE                       9:8
#define GPIO_AD_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AD_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AD_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_AD_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AD_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM6_SHIFT)
#define GPIO_AD_VM_00_0_VM6_RANGE                       11:10
#define GPIO_AD_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AD_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AD_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_AD_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AD_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM7_SHIFT)
#define GPIO_AD_VM_00_0_VM7_RANGE                       13:12
#define GPIO_AD_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AD_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AD_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_AD_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AD_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM8_SHIFT)
#define GPIO_AD_VM_00_0_VM8_RANGE                       15:14
#define GPIO_AD_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AD_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AD_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_AD_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_SCR_00_0
#define GPIO_AD_SCR_00_0                        MK_ADDR_CONST(0x84)
#define GPIO_AD_SCR_00_0_SECURE                         0x0
#define GPIO_AD_SCR_00_0_DUAL                   0x0
#define GPIO_AD_SCR_00_0_SCR                    0
#define GPIO_AD_SCR_00_0_SCRREG                         0
#define GPIO_AD_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_AD_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_AD_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_AD_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AD_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_AD_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_AD_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AD_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_AD_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_AD_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AD_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AD_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AD_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_AD_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AD_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AD_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AD_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AD_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AD_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR7_SHIFT)
#define GPIO_AD_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_AD_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR6_SHIFT)
#define GPIO_AD_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_AD_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR5_SHIFT)
#define GPIO_AD_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_AD_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR4_SHIFT)
#define GPIO_AD_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_AD_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR3_SHIFT)
#define GPIO_AD_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_AD_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR2_SHIFT)
#define GPIO_AD_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_AD_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR1_SHIFT)
#define GPIO_AD_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_AD_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR0_SHIFT)
#define GPIO_AD_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_AD_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G7W_SHIFT)
#define GPIO_AD_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_AD_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G6W_SHIFT)
#define GPIO_AD_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_AD_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G5W_SHIFT)
#define GPIO_AD_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_AD_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G4W_SHIFT)
#define GPIO_AD_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_AD_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G3W_SHIFT)
#define GPIO_AD_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_AD_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G2W_SHIFT)
#define GPIO_AD_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_AD_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G1W_SHIFT)
#define GPIO_AD_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_AD_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G0W_SHIFT)
#define GPIO_AD_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_AD_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G7R_SHIFT)
#define GPIO_AD_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_AD_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G6R_SHIFT)
#define GPIO_AD_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_AD_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G5R_SHIFT)
#define GPIO_AD_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_AD_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G4R_SHIFT)
#define GPIO_AD_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_AD_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G3R_SHIFT)
#define GPIO_AD_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_AD_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G2R_SHIFT)
#define GPIO_AD_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_AD_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G1R_SHIFT)
#define GPIO_AD_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_AD_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G0R_SHIFT)
#define GPIO_AD_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_AD_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_AD_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AD_VM_01_0
#define GPIO_AD_VM_01_0                 MK_ADDR_CONST(0x88)
#define GPIO_AD_VM_01_0_SECURE                  0x0
#define GPIO_AD_VM_01_0_DUAL                    0x0
#define GPIO_AD_VM_01_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AD_VM_01_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AD_VM_01_0_WORD_COUNT                      0x1
#define GPIO_AD_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM1_SHIFT)
#define GPIO_AD_VM_01_0_VM1_RANGE                       1:0
#define GPIO_AD_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AD_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_AD_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AD_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM2_SHIFT)
#define GPIO_AD_VM_01_0_VM2_RANGE                       3:2
#define GPIO_AD_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AD_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_AD_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AD_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM3_SHIFT)
#define GPIO_AD_VM_01_0_VM3_RANGE                       5:4
#define GPIO_AD_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AD_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AD_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_AD_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AD_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM4_SHIFT)
#define GPIO_AD_VM_01_0_VM4_RANGE                       7:6
#define GPIO_AD_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AD_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AD_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_AD_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AD_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM5_SHIFT)
#define GPIO_AD_VM_01_0_VM5_RANGE                       9:8
#define GPIO_AD_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AD_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AD_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_AD_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AD_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM6_SHIFT)
#define GPIO_AD_VM_01_0_VM6_RANGE                       11:10
#define GPIO_AD_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AD_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AD_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_AD_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AD_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM7_SHIFT)
#define GPIO_AD_VM_01_0_VM7_RANGE                       13:12
#define GPIO_AD_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AD_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AD_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_AD_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AD_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM8_SHIFT)
#define GPIO_AD_VM_01_0_VM8_RANGE                       15:14
#define GPIO_AD_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AD_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AD_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_AD_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_SCR_01_0
#define GPIO_AD_SCR_01_0                        MK_ADDR_CONST(0x8c)
#define GPIO_AD_SCR_01_0_SECURE                         0x0
#define GPIO_AD_SCR_01_0_DUAL                   0x0
#define GPIO_AD_SCR_01_0_SCR                    0
#define GPIO_AD_SCR_01_0_SCRREG                         0
#define GPIO_AD_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_AD_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_AD_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_AD_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AD_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_AD_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_AD_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AD_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_AD_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_AD_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AD_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AD_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AD_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_AD_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AD_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AD_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AD_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AD_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AD_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR7_SHIFT)
#define GPIO_AD_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_AD_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR6_SHIFT)
#define GPIO_AD_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_AD_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR5_SHIFT)
#define GPIO_AD_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_AD_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR4_SHIFT)
#define GPIO_AD_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_AD_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR3_SHIFT)
#define GPIO_AD_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_AD_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR2_SHIFT)
#define GPIO_AD_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_AD_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR1_SHIFT)
#define GPIO_AD_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_AD_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR0_SHIFT)
#define GPIO_AD_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_AD_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G7W_SHIFT)
#define GPIO_AD_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_AD_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G6W_SHIFT)
#define GPIO_AD_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_AD_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G5W_SHIFT)
#define GPIO_AD_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_AD_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G4W_SHIFT)
#define GPIO_AD_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_AD_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G3W_SHIFT)
#define GPIO_AD_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_AD_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G2W_SHIFT)
#define GPIO_AD_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_AD_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G1W_SHIFT)
#define GPIO_AD_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_AD_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G0W_SHIFT)
#define GPIO_AD_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_AD_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G7R_SHIFT)
#define GPIO_AD_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_AD_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G6R_SHIFT)
#define GPIO_AD_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_AD_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G5R_SHIFT)
#define GPIO_AD_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_AD_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G4R_SHIFT)
#define GPIO_AD_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_AD_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G3R_SHIFT)
#define GPIO_AD_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_AD_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G2R_SHIFT)
#define GPIO_AD_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_AD_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G1R_SHIFT)
#define GPIO_AD_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_AD_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G0R_SHIFT)
#define GPIO_AD_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_AD_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_AD_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AD_VM_02_0
#define GPIO_AD_VM_02_0                 MK_ADDR_CONST(0x90)
#define GPIO_AD_VM_02_0_SECURE                  0x0
#define GPIO_AD_VM_02_0_DUAL                    0x0
#define GPIO_AD_VM_02_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AD_VM_02_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AD_VM_02_0_WORD_COUNT                      0x1
#define GPIO_AD_VM_02_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_02_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_02_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_02_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_VM_02_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM1_SHIFT)
#define GPIO_AD_VM_02_0_VM1_RANGE                       1:0
#define GPIO_AD_VM_02_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AD_VM_02_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_VM_02_0_VM1_WOFFSET                     0x0
#define GPIO_AD_VM_02_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_02_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AD_VM_02_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM2_SHIFT)
#define GPIO_AD_VM_02_0_VM2_RANGE                       3:2
#define GPIO_AD_VM_02_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_VM_02_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AD_VM_02_0_VM2_WOFFSET                     0x0
#define GPIO_AD_VM_02_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_02_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AD_VM_02_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM3_SHIFT)
#define GPIO_AD_VM_02_0_VM3_RANGE                       5:4
#define GPIO_AD_VM_02_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AD_VM_02_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AD_VM_02_0_VM3_WOFFSET                     0x0
#define GPIO_AD_VM_02_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_02_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AD_VM_02_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM4_SHIFT)
#define GPIO_AD_VM_02_0_VM4_RANGE                       7:6
#define GPIO_AD_VM_02_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AD_VM_02_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AD_VM_02_0_VM4_WOFFSET                     0x0
#define GPIO_AD_VM_02_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_02_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AD_VM_02_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM5_SHIFT)
#define GPIO_AD_VM_02_0_VM5_RANGE                       9:8
#define GPIO_AD_VM_02_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AD_VM_02_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AD_VM_02_0_VM5_WOFFSET                     0x0
#define GPIO_AD_VM_02_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_02_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AD_VM_02_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM6_SHIFT)
#define GPIO_AD_VM_02_0_VM6_RANGE                       11:10
#define GPIO_AD_VM_02_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AD_VM_02_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AD_VM_02_0_VM6_WOFFSET                     0x0
#define GPIO_AD_VM_02_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_02_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AD_VM_02_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM7_SHIFT)
#define GPIO_AD_VM_02_0_VM7_RANGE                       13:12
#define GPIO_AD_VM_02_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AD_VM_02_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AD_VM_02_0_VM7_WOFFSET                     0x0
#define GPIO_AD_VM_02_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_02_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AD_VM_02_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM8_SHIFT)
#define GPIO_AD_VM_02_0_VM8_RANGE                       15:14
#define GPIO_AD_VM_02_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AD_VM_02_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AD_VM_02_0_VM8_WOFFSET                     0x0
#define GPIO_AD_VM_02_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_02_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_02_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_SCR_02_0
#define GPIO_AD_SCR_02_0                        MK_ADDR_CONST(0x94)
#define GPIO_AD_SCR_02_0_SECURE                         0x0
#define GPIO_AD_SCR_02_0_DUAL                   0x0
#define GPIO_AD_SCR_02_0_SCR                    0
#define GPIO_AD_SCR_02_0_SCRREG                         0
#define GPIO_AD_SCR_02_0_WORD_COUNT                     0x1
#define GPIO_AD_SCR_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_02_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_02_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_02_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_AD_SCR_02_0_SEC_LCK_RANGE                  29:29
#define GPIO_AD_SCR_02_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_02_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_02_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AD_SCR_02_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_02_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_AD_SCR_02_0_SEC_WEN_RANGE                  28:28
#define GPIO_AD_SCR_02_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_02_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_02_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AD_SCR_02_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_02_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_AD_SCR_02_0_SEC_REN_RANGE                  27:27
#define GPIO_AD_SCR_02_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_02_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_02_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AD_SCR_02_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AD_SCR_02_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AD_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_AD_SCR_02_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AD_SCR_02_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AD_SCR_02_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AD_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AD_SCR_02_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AD_SCR_02_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_02_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR7_SHIFT)
#define GPIO_AD_SCR_02_0_PR7_RANGE                      23:23
#define GPIO_AD_SCR_02_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_02_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_02_0_PR7_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_02_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR6_SHIFT)
#define GPIO_AD_SCR_02_0_PR6_RANGE                      22:22
#define GPIO_AD_SCR_02_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_02_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_02_0_PR6_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_02_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR5_SHIFT)
#define GPIO_AD_SCR_02_0_PR5_RANGE                      21:21
#define GPIO_AD_SCR_02_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_02_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_02_0_PR5_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_02_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR4_SHIFT)
#define GPIO_AD_SCR_02_0_PR4_RANGE                      20:20
#define GPIO_AD_SCR_02_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_02_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_02_0_PR4_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_02_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR3_SHIFT)
#define GPIO_AD_SCR_02_0_PR3_RANGE                      19:19
#define GPIO_AD_SCR_02_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_02_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_02_0_PR3_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_02_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR2_SHIFT)
#define GPIO_AD_SCR_02_0_PR2_RANGE                      18:18
#define GPIO_AD_SCR_02_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_02_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_02_0_PR2_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_02_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR1_SHIFT)
#define GPIO_AD_SCR_02_0_PR1_RANGE                      17:17
#define GPIO_AD_SCR_02_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_02_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_02_0_PR1_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_02_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR0_SHIFT)
#define GPIO_AD_SCR_02_0_PR0_RANGE                      16:16
#define GPIO_AD_SCR_02_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_02_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_02_0_PR0_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_02_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G7W_SHIFT)
#define GPIO_AD_SCR_02_0_G7W_RANGE                      15:15
#define GPIO_AD_SCR_02_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_02_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_02_0_G7W_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_02_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G6W_SHIFT)
#define GPIO_AD_SCR_02_0_G6W_RANGE                      14:14
#define GPIO_AD_SCR_02_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_02_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_02_0_G6W_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_02_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G5W_SHIFT)
#define GPIO_AD_SCR_02_0_G5W_RANGE                      13:13
#define GPIO_AD_SCR_02_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_02_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_02_0_G5W_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_02_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G4W_SHIFT)
#define GPIO_AD_SCR_02_0_G4W_RANGE                      12:12
#define GPIO_AD_SCR_02_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_02_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_02_0_G4W_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_02_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G3W_SHIFT)
#define GPIO_AD_SCR_02_0_G3W_RANGE                      11:11
#define GPIO_AD_SCR_02_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_02_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_02_0_G3W_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_02_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G2W_SHIFT)
#define GPIO_AD_SCR_02_0_G2W_RANGE                      10:10
#define GPIO_AD_SCR_02_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_02_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_02_0_G2W_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_02_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G1W_SHIFT)
#define GPIO_AD_SCR_02_0_G1W_RANGE                      9:9
#define GPIO_AD_SCR_02_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_02_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_02_0_G1W_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_02_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G0W_SHIFT)
#define GPIO_AD_SCR_02_0_G0W_RANGE                      8:8
#define GPIO_AD_SCR_02_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_02_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_02_0_G0W_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_02_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G7R_SHIFT)
#define GPIO_AD_SCR_02_0_G7R_RANGE                      7:7
#define GPIO_AD_SCR_02_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_02_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_02_0_G7R_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_02_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G6R_SHIFT)
#define GPIO_AD_SCR_02_0_G6R_RANGE                      6:6
#define GPIO_AD_SCR_02_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_02_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_02_0_G6R_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_02_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G5R_SHIFT)
#define GPIO_AD_SCR_02_0_G5R_RANGE                      5:5
#define GPIO_AD_SCR_02_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_02_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_02_0_G5R_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_02_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G4R_SHIFT)
#define GPIO_AD_SCR_02_0_G4R_RANGE                      4:4
#define GPIO_AD_SCR_02_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_02_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_02_0_G4R_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_02_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G3R_SHIFT)
#define GPIO_AD_SCR_02_0_G3R_RANGE                      3:3
#define GPIO_AD_SCR_02_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_02_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_02_0_G3R_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_02_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G2R_SHIFT)
#define GPIO_AD_SCR_02_0_G2R_RANGE                      2:2
#define GPIO_AD_SCR_02_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_02_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_02_0_G2R_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_02_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G1R_SHIFT)
#define GPIO_AD_SCR_02_0_G1R_RANGE                      1:1
#define GPIO_AD_SCR_02_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_02_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_02_0_G1R_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_02_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_02_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G0R_SHIFT)
#define GPIO_AD_SCR_02_0_G0R_RANGE                      0:0
#define GPIO_AD_SCR_02_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_02_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_02_0_G0R_WOFFSET                    0x0
#define GPIO_AD_SCR_02_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_02_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_02_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AD_VM_03_0
#define GPIO_AD_VM_03_0                 MK_ADDR_CONST(0x98)
#define GPIO_AD_VM_03_0_SECURE                  0x0
#define GPIO_AD_VM_03_0_DUAL                    0x0
#define GPIO_AD_VM_03_0_SCR                     GPIO_CTL0_VM_SCR_0
#define GPIO_AD_VM_03_0_SCRREG                  GPIO_CTL0_VM_SCR_0
#define GPIO_AD_VM_03_0_WORD_COUNT                      0x1
#define GPIO_AD_VM_03_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_03_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_03_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AD_VM_03_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_VM_03_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM1_SHIFT)
#define GPIO_AD_VM_03_0_VM1_RANGE                       1:0
#define GPIO_AD_VM_03_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AD_VM_03_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_VM_03_0_VM1_WOFFSET                     0x0
#define GPIO_AD_VM_03_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_03_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AD_VM_03_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM2_SHIFT)
#define GPIO_AD_VM_03_0_VM2_RANGE                       3:2
#define GPIO_AD_VM_03_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_VM_03_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AD_VM_03_0_VM2_WOFFSET                     0x0
#define GPIO_AD_VM_03_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_03_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AD_VM_03_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM3_SHIFT)
#define GPIO_AD_VM_03_0_VM3_RANGE                       5:4
#define GPIO_AD_VM_03_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AD_VM_03_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AD_VM_03_0_VM3_WOFFSET                     0x0
#define GPIO_AD_VM_03_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_03_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AD_VM_03_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM4_SHIFT)
#define GPIO_AD_VM_03_0_VM4_RANGE                       7:6
#define GPIO_AD_VM_03_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AD_VM_03_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AD_VM_03_0_VM4_WOFFSET                     0x0
#define GPIO_AD_VM_03_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_03_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AD_VM_03_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM5_SHIFT)
#define GPIO_AD_VM_03_0_VM5_RANGE                       9:8
#define GPIO_AD_VM_03_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AD_VM_03_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AD_VM_03_0_VM5_WOFFSET                     0x0
#define GPIO_AD_VM_03_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_03_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AD_VM_03_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM6_SHIFT)
#define GPIO_AD_VM_03_0_VM6_RANGE                       11:10
#define GPIO_AD_VM_03_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AD_VM_03_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AD_VM_03_0_VM6_WOFFSET                     0x0
#define GPIO_AD_VM_03_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_03_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AD_VM_03_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM7_SHIFT)
#define GPIO_AD_VM_03_0_VM7_RANGE                       13:12
#define GPIO_AD_VM_03_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AD_VM_03_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AD_VM_03_0_VM7_WOFFSET                     0x0
#define GPIO_AD_VM_03_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AD_VM_03_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AD_VM_03_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM8_SHIFT)
#define GPIO_AD_VM_03_0_VM8_RANGE                       15:14
#define GPIO_AD_VM_03_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AD_VM_03_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AD_VM_03_0_VM8_WOFFSET                     0x0
#define GPIO_AD_VM_03_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AD_VM_03_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_VM_03_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_SCR_03_0
#define GPIO_AD_SCR_03_0                        MK_ADDR_CONST(0x9c)
#define GPIO_AD_SCR_03_0_SECURE                         0x0
#define GPIO_AD_SCR_03_0_DUAL                   0x0
#define GPIO_AD_SCR_03_0_SCR                    0
#define GPIO_AD_SCR_03_0_SCRREG                         0
#define GPIO_AD_SCR_03_0_WORD_COUNT                     0x1
#define GPIO_AD_SCR_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_03_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AD_SCR_03_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_03_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_AD_SCR_03_0_SEC_LCK_RANGE                  29:29
#define GPIO_AD_SCR_03_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_03_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AD_SCR_03_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AD_SCR_03_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_03_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_AD_SCR_03_0_SEC_WEN_RANGE                  28:28
#define GPIO_AD_SCR_03_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_03_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AD_SCR_03_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AD_SCR_03_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_03_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_AD_SCR_03_0_SEC_REN_RANGE                  27:27
#define GPIO_AD_SCR_03_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_03_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AD_SCR_03_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AD_SCR_03_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AD_SCR_03_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AD_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_AD_SCR_03_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AD_SCR_03_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AD_SCR_03_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AD_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AD_SCR_03_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AD_SCR_03_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_03_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR7_SHIFT)
#define GPIO_AD_SCR_03_0_PR7_RANGE                      23:23
#define GPIO_AD_SCR_03_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_03_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AD_SCR_03_0_PR7_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_03_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR6_SHIFT)
#define GPIO_AD_SCR_03_0_PR6_RANGE                      22:22
#define GPIO_AD_SCR_03_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_03_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AD_SCR_03_0_PR6_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_03_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR5_SHIFT)
#define GPIO_AD_SCR_03_0_PR5_RANGE                      21:21
#define GPIO_AD_SCR_03_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_03_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AD_SCR_03_0_PR5_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_03_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR4_SHIFT)
#define GPIO_AD_SCR_03_0_PR4_RANGE                      20:20
#define GPIO_AD_SCR_03_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_03_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AD_SCR_03_0_PR4_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_03_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR3_SHIFT)
#define GPIO_AD_SCR_03_0_PR3_RANGE                      19:19
#define GPIO_AD_SCR_03_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_03_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AD_SCR_03_0_PR3_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_03_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR2_SHIFT)
#define GPIO_AD_SCR_03_0_PR2_RANGE                      18:18
#define GPIO_AD_SCR_03_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_03_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AD_SCR_03_0_PR2_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_03_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR1_SHIFT)
#define GPIO_AD_SCR_03_0_PR1_RANGE                      17:17
#define GPIO_AD_SCR_03_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_03_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AD_SCR_03_0_PR1_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_03_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR0_SHIFT)
#define GPIO_AD_SCR_03_0_PR0_RANGE                      16:16
#define GPIO_AD_SCR_03_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_03_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AD_SCR_03_0_PR0_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_03_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G7W_SHIFT)
#define GPIO_AD_SCR_03_0_G7W_RANGE                      15:15
#define GPIO_AD_SCR_03_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_03_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AD_SCR_03_0_G7W_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_03_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G6W_SHIFT)
#define GPIO_AD_SCR_03_0_G6W_RANGE                      14:14
#define GPIO_AD_SCR_03_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_03_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AD_SCR_03_0_G6W_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_03_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G5W_SHIFT)
#define GPIO_AD_SCR_03_0_G5W_RANGE                      13:13
#define GPIO_AD_SCR_03_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_03_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AD_SCR_03_0_G5W_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_03_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G4W_SHIFT)
#define GPIO_AD_SCR_03_0_G4W_RANGE                      12:12
#define GPIO_AD_SCR_03_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_03_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AD_SCR_03_0_G4W_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_03_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G3W_SHIFT)
#define GPIO_AD_SCR_03_0_G3W_RANGE                      11:11
#define GPIO_AD_SCR_03_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_03_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AD_SCR_03_0_G3W_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_03_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G2W_SHIFT)
#define GPIO_AD_SCR_03_0_G2W_RANGE                      10:10
#define GPIO_AD_SCR_03_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_03_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AD_SCR_03_0_G2W_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_03_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G1W_SHIFT)
#define GPIO_AD_SCR_03_0_G1W_RANGE                      9:9
#define GPIO_AD_SCR_03_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_03_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AD_SCR_03_0_G1W_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_03_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G0W_SHIFT)
#define GPIO_AD_SCR_03_0_G0W_RANGE                      8:8
#define GPIO_AD_SCR_03_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_03_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AD_SCR_03_0_G0W_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_03_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G7R_SHIFT)
#define GPIO_AD_SCR_03_0_G7R_RANGE                      7:7
#define GPIO_AD_SCR_03_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_03_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AD_SCR_03_0_G7R_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_03_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G6R_SHIFT)
#define GPIO_AD_SCR_03_0_G6R_RANGE                      6:6
#define GPIO_AD_SCR_03_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_03_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AD_SCR_03_0_G6R_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_03_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G5R_SHIFT)
#define GPIO_AD_SCR_03_0_G5R_RANGE                      5:5
#define GPIO_AD_SCR_03_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_03_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_SCR_03_0_G5R_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_03_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G4R_SHIFT)
#define GPIO_AD_SCR_03_0_G4R_RANGE                      4:4
#define GPIO_AD_SCR_03_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_03_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AD_SCR_03_0_G4R_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_03_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G3R_SHIFT)
#define GPIO_AD_SCR_03_0_G3R_RANGE                      3:3
#define GPIO_AD_SCR_03_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_03_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AD_SCR_03_0_G3R_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_03_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G2R_SHIFT)
#define GPIO_AD_SCR_03_0_G2R_RANGE                      2:2
#define GPIO_AD_SCR_03_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_03_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AD_SCR_03_0_G2R_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_03_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G1R_SHIFT)
#define GPIO_AD_SCR_03_0_G1R_RANGE                      1:1
#define GPIO_AD_SCR_03_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_03_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AD_SCR_03_0_G1R_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AD_SCR_03_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_03_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G0R_SHIFT)
#define GPIO_AD_SCR_03_0_G0R_RANGE                      0:0
#define GPIO_AD_SCR_03_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_03_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_SCR_03_0_G0R_WOFFSET                    0x0
#define GPIO_AD_SCR_03_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_SCR_03_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AD_SCR_03_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0xa0

// Reserved address 0xa4

// Reserved address 0xa8

// Reserved address 0xac

// Reserved address 0xb0

// Reserved address 0xb4

// Reserved address 0xb8

// Reserved address 0xbc

// Register GPIO_B_VM_00_0
#define GPIO_B_VM_00_0                  MK_ADDR_CONST(0xc0)
#define GPIO_B_VM_00_0_SECURE                   0x0
#define GPIO_B_VM_00_0_DUAL                     0x0
#define GPIO_B_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
#define GPIO_B_VM_00_0_SCRREG                   GPIO_CTL0_VM_SCR_0
#define GPIO_B_VM_00_0_WORD_COUNT                       0x1
#define GPIO_B_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_B_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM1_SHIFT)
#define GPIO_B_VM_00_0_VM1_RANGE                        1:0
#define GPIO_B_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_B_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_B_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM2_SHIFT)
#define GPIO_B_VM_00_0_VM2_RANGE                        3:2
#define GPIO_B_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_B_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_B_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_B_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM3_SHIFT)
#define GPIO_B_VM_00_0_VM3_RANGE                        5:4
#define GPIO_B_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_B_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_B_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_B_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM4_SHIFT)
#define GPIO_B_VM_00_0_VM4_RANGE                        7:6
#define GPIO_B_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_B_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_B_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_B_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM5_SHIFT)
#define GPIO_B_VM_00_0_VM5_RANGE                        9:8
#define GPIO_B_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_B_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_B_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_B_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM6_SHIFT)
#define GPIO_B_VM_00_0_VM6_RANGE                        11:10
#define GPIO_B_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_B_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_B_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_B_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM7_SHIFT)
#define GPIO_B_VM_00_0_VM7_RANGE                        13:12
#define GPIO_B_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_B_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_B_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_B_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_B_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM8_SHIFT)
#define GPIO_B_VM_00_0_VM8_RANGE                        15:14
#define GPIO_B_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_B_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_B_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_B_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_B_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_B_SCR_00_0
#define GPIO_B_SCR_00_0                 MK_ADDR_CONST(0xc4)
#define GPIO_B_SCR_00_0_SECURE                  0x0
#define GPIO_B_SCR_00_0_DUAL                    0x0
#define GPIO_B_SCR_00_0_SCR                     0
#define GPIO_B_SCR_00_0_SCRREG                  0
#define GPIO_B_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_B_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_B_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_B_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_B_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_B_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_B_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_B_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_B_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_B_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_B_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_B_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_B_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_B_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_B_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_B_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_B_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_B_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_B_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_B_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_B_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_B_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_B_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_B_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_B_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_B_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_B_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_B_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR7_SHIFT)
#define GPIO_B_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_B_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_B_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_B_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_B_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR6_SHIFT)
#define GPIO_B_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_B_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_B_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_B_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_B_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR5_SHIFT)
#define GPIO_B_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_B_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_B_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_B_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_B_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR4_SHIFT)
#define GPIO_B_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_B_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_B_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_B_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_B_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR3_SHIFT)
#define GPIO_B_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_B_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_B_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_B_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_B_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR2_SHIFT)
#define GPIO_B_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_B_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_B_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_B_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_B_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR1_SHIFT)
#define GPIO_B_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_B_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_B_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_B_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_B_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR0_SHIFT)
#define GPIO_B_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_B_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_B_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_B_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_B_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G7W_SHIFT)
#define GPIO_B_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_B_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_B_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_B_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_B_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G6W_SHIFT)
#define GPIO_B_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_B_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_B_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_B_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_B_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G5W_SHIFT)
#define GPIO_B_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_B_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_B_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_B_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_B_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G4W_SHIFT)
#define GPIO_B_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_B_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_B_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_B_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_B_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G3W_SHIFT)
#define GPIO_B_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_B_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_B_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_B_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_B_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G2W_SHIFT)
#define GPIO_B_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_B_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_B_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_B_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_B_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G1W_SHIFT)
#define GPIO_B_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_B_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_B_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_B_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_B_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G0W_SHIFT)
#define GPIO_B_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_B_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_B_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_B_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_B_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G7R_SHIFT)
#define GPIO_B_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_B_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_B_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_B_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_B_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G6R_SHIFT)
#define GPIO_B_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_B_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_B_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_B_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_B_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G5R_SHIFT)
#define GPIO_B_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_B_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_B_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_B_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_B_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G4R_SHIFT)
#define GPIO_B_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_B_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_B_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_B_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_B_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G3R_SHIFT)
#define GPIO_B_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_B_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_B_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_B_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_B_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G2R_SHIFT)
#define GPIO_B_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_B_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_B_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_B_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_B_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G1R_SHIFT)
#define GPIO_B_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_B_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_B_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_B_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_B_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_B_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G0R_SHIFT)
#define GPIO_B_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_B_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_B_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_B_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_B_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_B_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0xc8

// Reserved address 0xcc

// Reserved address 0xd0

// Reserved address 0xd4

// Reserved address 0xd8

// Reserved address 0xdc

// Reserved address 0xe0

// Reserved address 0xe4

// Reserved address 0xe8

// Reserved address 0xec

// Reserved address 0xf0

// Reserved address 0xf4

// Reserved address 0xf8

// Reserved address 0xfc

// Register GPIO_CTL0_VM_SCR_0
#define GPIO_CTL0_VM_SCR_0                      MK_ADDR_CONST(0x800)
#define GPIO_CTL0_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL0_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL0_VM_SCR_0_SCR                  0
#define GPIO_CTL0_VM_SCR_0_SCRREG                       0
#define GPIO_CTL0_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL0_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL0_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL0_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL0_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define GPIO_CTL0_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL0_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL0_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL0_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define GPIO_CTL0_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL0_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL0_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL0_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define GPIO_CTL0_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL0_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL0_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL0_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define GPIO_CTL0_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL0_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL0_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL0_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define GPIO_CTL0_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL0_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL0_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL0_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define GPIO_CTL0_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL0_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL0_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL0_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define GPIO_CTL0_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL0_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL0_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL0_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define GPIO_CTL0_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL0_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL0_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL0_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define GPIO_CTL0_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL0_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL0_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL0_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define GPIO_CTL0_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL0_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL0_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL0_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define GPIO_CTL0_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL0_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL0_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL0_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define GPIO_CTL0_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL0_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL0_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL0_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define GPIO_CTL0_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL0_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL0_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL0_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define GPIO_CTL0_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL0_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL0_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL0_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define GPIO_CTL0_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL0_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL0_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL0_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define GPIO_CTL0_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL0_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL0_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL0_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define GPIO_CTL0_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL0_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL0_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL0_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define GPIO_CTL0_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL0_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL0_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL0_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define GPIO_CTL0_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL0_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL0_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL0_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define GPIO_CTL0_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL0_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL0_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL0_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define GPIO_CTL0_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL0_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL0_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL0_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_CTL0_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL0_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL0_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL0_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define GPIO_CTL0_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL0_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL0_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL0_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL0_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CTL0_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL0_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL0_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL0_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL0_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL0_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x804)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL0_INTERRUPT_STATUS_VM_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x808)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_CTL0_SCR_0
#define GPIO_CTL0_SCR_0                 MK_ADDR_CONST(0x80c)
#define GPIO_CTL0_SCR_0_SECURE                  0x0
#define GPIO_CTL0_SCR_0_DUAL                    0x0
#define GPIO_CTL0_SCR_0_SCR                     0
#define GPIO_CTL0_SCR_0_SCRREG                  0
#define GPIO_CTL0_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL0_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL0_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_CTL0_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL0_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL0_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL0_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_CTL0_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL0_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL0_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL0_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_CTL0_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL0_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL0_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL0_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL0_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_CTL0_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL0_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL0_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL0_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_CTL0_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_CTL0_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL0_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_CTL0_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_CTL0_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR7_SHIFT)
#define GPIO_CTL0_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL0_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL0_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL0_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_CTL0_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR6_SHIFT)
#define GPIO_CTL0_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL0_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL0_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL0_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_CTL0_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR5_SHIFT)
#define GPIO_CTL0_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL0_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL0_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL0_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_CTL0_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR4_SHIFT)
#define GPIO_CTL0_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL0_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL0_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL0_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_CTL0_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR3_SHIFT)
#define GPIO_CTL0_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL0_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL0_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL0_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_CTL0_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR2_SHIFT)
#define GPIO_CTL0_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL0_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL0_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL0_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_CTL0_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR1_SHIFT)
#define GPIO_CTL0_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL0_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL0_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL0_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_CTL0_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR0_SHIFT)
#define GPIO_CTL0_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL0_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL0_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL0_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_CTL0_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G7W_SHIFT)
#define GPIO_CTL0_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL0_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL0_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL0_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_CTL0_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G6W_SHIFT)
#define GPIO_CTL0_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL0_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL0_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL0_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_CTL0_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G5W_SHIFT)
#define GPIO_CTL0_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL0_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL0_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL0_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_CTL0_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G4W_SHIFT)
#define GPIO_CTL0_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL0_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL0_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL0_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_CTL0_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G3W_SHIFT)
#define GPIO_CTL0_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL0_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL0_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL0_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_CTL0_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G2W_SHIFT)
#define GPIO_CTL0_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL0_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL0_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL0_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_CTL0_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G1W_SHIFT)
#define GPIO_CTL0_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL0_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL0_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL0_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_CTL0_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G0W_SHIFT)
#define GPIO_CTL0_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL0_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL0_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL0_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_CTL0_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G7R_SHIFT)
#define GPIO_CTL0_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL0_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL0_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL0_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_CTL0_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G6R_SHIFT)
#define GPIO_CTL0_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL0_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL0_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL0_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_CTL0_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G5R_SHIFT)
#define GPIO_CTL0_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL0_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL0_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL0_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_CTL0_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G4R_SHIFT)
#define GPIO_CTL0_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL0_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL0_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL0_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_CTL0_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G3R_SHIFT)
#define GPIO_CTL0_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL0_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL0_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL0_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_CTL0_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G2R_SHIFT)
#define GPIO_CTL0_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL0_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL0_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL0_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_CTL0_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G1R_SHIFT)
#define GPIO_CTL0_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL0_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL0_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL0_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL0_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CTL0_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G0R_SHIFT)
#define GPIO_CTL0_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL0_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL0_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL0_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL0_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL0_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CTL0_ICG_EN_OVERRIDE_0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x810)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_A_INT0_ROUTE_MAPPING_0
#define GPIO_A_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x814)
#define GPIO_A_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_A_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_A_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_A_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_A_INT1_ROUTE_MAPPING_0
#define GPIO_A_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x818)
#define GPIO_A_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_A_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_A_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_A_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_A_INT2_ROUTE_MAPPING_0
#define GPIO_A_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x81c)
#define GPIO_A_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_A_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_A_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_A_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_A_INT3_ROUTE_MAPPING_0
#define GPIO_A_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x820)
#define GPIO_A_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_A_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_A_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_A_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_A_INT4_ROUTE_MAPPING_0
#define GPIO_A_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x824)
#define GPIO_A_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_A_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_A_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_A_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_A_INT5_ROUTE_MAPPING_0
#define GPIO_A_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x828)
#define GPIO_A_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_A_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_A_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_A_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_A_INT6_ROUTE_MAPPING_0
#define GPIO_A_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x82c)
#define GPIO_A_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_A_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_A_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_A_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_A_INT7_ROUTE_MAPPING_0
#define GPIO_A_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x830)
#define GPIO_A_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_A_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_A_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_A_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_A_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_A_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_A_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_AC_INT0_ROUTE_MAPPING_0
#define GPIO_AC_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x834)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AC_INT0_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AC_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AC_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AC_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AC_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AC_INT1_ROUTE_MAPPING_0
#define GPIO_AC_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x838)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AC_INT1_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AC_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AC_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AC_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AC_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AC_INT2_ROUTE_MAPPING_0
#define GPIO_AC_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x83c)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AC_INT2_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AC_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AC_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AC_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AC_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AC_INT3_ROUTE_MAPPING_0
#define GPIO_AC_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x840)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AC_INT3_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AC_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AC_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AC_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AC_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AC_INT4_ROUTE_MAPPING_0
#define GPIO_AC_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x844)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AC_INT4_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AC_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AC_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AC_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AC_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AC_INT5_ROUTE_MAPPING_0
#define GPIO_AC_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x848)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AC_INT5_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AC_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AC_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AC_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AC_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AC_INT6_ROUTE_MAPPING_0
#define GPIO_AC_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x84c)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AC_INT6_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AC_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AC_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AC_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AC_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AC_INT7_ROUTE_MAPPING_0
#define GPIO_AC_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x850)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AC_INT7_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AC_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AC_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AC_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AC_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AD_INT0_ROUTE_MAPPING_0
#define GPIO_AD_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x854)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AD_INT0_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AD_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AD_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AD_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AD_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AD_INT1_ROUTE_MAPPING_0
#define GPIO_AD_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x858)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AD_INT1_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AD_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AD_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AD_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AD_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AD_INT2_ROUTE_MAPPING_0
#define GPIO_AD_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x85c)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AD_INT2_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AD_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AD_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AD_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AD_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AD_INT3_ROUTE_MAPPING_0
#define GPIO_AD_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x860)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AD_INT3_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AD_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AD_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AD_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AD_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AD_INT4_ROUTE_MAPPING_0
#define GPIO_AD_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x864)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AD_INT4_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AD_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AD_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AD_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AD_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AD_INT5_ROUTE_MAPPING_0
#define GPIO_AD_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x868)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AD_INT5_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AD_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AD_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AD_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AD_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AD_INT6_ROUTE_MAPPING_0
#define GPIO_AD_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x86c)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AD_INT6_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AD_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AD_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AD_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AD_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AD_INT7_ROUTE_MAPPING_0
#define GPIO_AD_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x870)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AD_INT7_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AD_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
#define GPIO_AD_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
#define GPIO_AD_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AD_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_B_INT0_ROUTE_MAPPING_0
#define GPIO_B_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x874)
#define GPIO_B_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_B_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_B_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_B_INT1_ROUTE_MAPPING_0
#define GPIO_B_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x878)
#define GPIO_B_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_B_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_B_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_B_INT2_ROUTE_MAPPING_0
#define GPIO_B_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x87c)
#define GPIO_B_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_B_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_B_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_B_INT3_ROUTE_MAPPING_0
#define GPIO_B_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x880)
#define GPIO_B_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_B_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_B_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_B_INT4_ROUTE_MAPPING_0
#define GPIO_B_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x884)
#define GPIO_B_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_B_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_B_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_B_INT5_ROUTE_MAPPING_0
#define GPIO_B_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x888)
#define GPIO_B_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_B_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_B_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_B_INT6_ROUTE_MAPPING_0
#define GPIO_B_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x88c)
#define GPIO_B_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_B_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_B_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_B_INT7_ROUTE_MAPPING_0
#define GPIO_B_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x890)
#define GPIO_B_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_B_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_B_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
#define GPIO_B_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
#define GPIO_B_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_B_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_RANGE                   0:0
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL0_SPARE_0
#define GPIO_CTL0_SPARE_0                       MK_ADDR_CONST(0x894)
#define GPIO_CTL0_SPARE_0_SECURE                        0x0
#define GPIO_CTL0_SPARE_0_DUAL                  0x0
#define GPIO_CTL0_SPARE_0_SCR                   0
#define GPIO_CTL0_SPARE_0_SCRREG                        0
#define GPIO_CTL0_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL0_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL0_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL0_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL0_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL0_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL0_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL0_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL0_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL0_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL0_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_X_VM_00_0
#define GPIO_X_VM_00_0                  MK_ADDR_CONST(0x1000)
#define GPIO_X_VM_00_0_SECURE                   0x0
#define GPIO_X_VM_00_0_DUAL                     0x0
#define GPIO_X_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_00_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_00_0_WORD_COUNT                       0x1
#define GPIO_X_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM1_SHIFT)
#define GPIO_X_VM_00_0_VM1_RANGE                        1:0
#define GPIO_X_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_X_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_X_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM2_SHIFT)
#define GPIO_X_VM_00_0_VM2_RANGE                        3:2
#define GPIO_X_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_X_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_X_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_X_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM3_SHIFT)
#define GPIO_X_VM_00_0_VM3_RANGE                        5:4
#define GPIO_X_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_X_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_X_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_X_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM4_SHIFT)
#define GPIO_X_VM_00_0_VM4_RANGE                        7:6
#define GPIO_X_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_X_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_X_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM5_SHIFT)
#define GPIO_X_VM_00_0_VM5_RANGE                        9:8
#define GPIO_X_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_X_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_X_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_X_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM6_SHIFT)
#define GPIO_X_VM_00_0_VM6_RANGE                        11:10
#define GPIO_X_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_X_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_X_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_X_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM7_SHIFT)
#define GPIO_X_VM_00_0_VM7_RANGE                        13:12
#define GPIO_X_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_X_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_X_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_X_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM8_SHIFT)
#define GPIO_X_VM_00_0_VM8_RANGE                        15:14
#define GPIO_X_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_X_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_X_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_00_0
#define GPIO_X_SCR_00_0                 MK_ADDR_CONST(0x1004)
#define GPIO_X_SCR_00_0_SECURE                  0x0
#define GPIO_X_SCR_00_0_DUAL                    0x0
#define GPIO_X_SCR_00_0_SCR                     0
#define GPIO_X_SCR_00_0_SCRREG                  0
#define GPIO_X_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_X_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_X_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_X_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_X_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_X_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_X_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_X_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_X_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR7_SHIFT)
#define GPIO_X_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_X_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR6_SHIFT)
#define GPIO_X_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_X_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR5_SHIFT)
#define GPIO_X_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_X_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR4_SHIFT)
#define GPIO_X_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_X_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR3_SHIFT)
#define GPIO_X_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_X_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR2_SHIFT)
#define GPIO_X_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_X_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR1_SHIFT)
#define GPIO_X_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_X_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR0_SHIFT)
#define GPIO_X_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_X_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G7W_SHIFT)
#define GPIO_X_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_X_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G6W_SHIFT)
#define GPIO_X_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_X_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G5W_SHIFT)
#define GPIO_X_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_X_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G4W_SHIFT)
#define GPIO_X_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_X_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G3W_SHIFT)
#define GPIO_X_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_X_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G2W_SHIFT)
#define GPIO_X_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_X_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G1W_SHIFT)
#define GPIO_X_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_X_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G0W_SHIFT)
#define GPIO_X_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_X_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G7R_SHIFT)
#define GPIO_X_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_X_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G6R_SHIFT)
#define GPIO_X_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G5R_SHIFT)
#define GPIO_X_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_X_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G4R_SHIFT)
#define GPIO_X_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_X_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G3R_SHIFT)
#define GPIO_X_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_X_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G2R_SHIFT)
#define GPIO_X_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_X_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G1R_SHIFT)
#define GPIO_X_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G0R_SHIFT)
#define GPIO_X_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_X_VM_01_0
#define GPIO_X_VM_01_0                  MK_ADDR_CONST(0x1008)
#define GPIO_X_VM_01_0_SECURE                   0x0
#define GPIO_X_VM_01_0_DUAL                     0x0
#define GPIO_X_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_01_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_01_0_WORD_COUNT                       0x1
#define GPIO_X_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM1_SHIFT)
#define GPIO_X_VM_01_0_VM1_RANGE                        1:0
#define GPIO_X_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_X_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_X_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM2_SHIFT)
#define GPIO_X_VM_01_0_VM2_RANGE                        3:2
#define GPIO_X_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_X_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_X_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_X_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM3_SHIFT)
#define GPIO_X_VM_01_0_VM3_RANGE                        5:4
#define GPIO_X_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_X_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_X_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_X_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM4_SHIFT)
#define GPIO_X_VM_01_0_VM4_RANGE                        7:6
#define GPIO_X_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_X_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_X_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM5_SHIFT)
#define GPIO_X_VM_01_0_VM5_RANGE                        9:8
#define GPIO_X_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_X_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_X_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_X_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM6_SHIFT)
#define GPIO_X_VM_01_0_VM6_RANGE                        11:10
#define GPIO_X_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_X_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_X_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_X_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM7_SHIFT)
#define GPIO_X_VM_01_0_VM7_RANGE                        13:12
#define GPIO_X_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_X_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_X_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_X_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM8_SHIFT)
#define GPIO_X_VM_01_0_VM8_RANGE                        15:14
#define GPIO_X_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_X_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_X_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_01_0
#define GPIO_X_SCR_01_0                 MK_ADDR_CONST(0x100c)
#define GPIO_X_SCR_01_0_SECURE                  0x0
#define GPIO_X_SCR_01_0_DUAL                    0x0
#define GPIO_X_SCR_01_0_SCR                     0
#define GPIO_X_SCR_01_0_SCRREG                  0
#define GPIO_X_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_X_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_X_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_X_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_X_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_X_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_X_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_X_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_X_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR7_SHIFT)
#define GPIO_X_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_X_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR6_SHIFT)
#define GPIO_X_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_X_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR5_SHIFT)
#define GPIO_X_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_X_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR4_SHIFT)
#define GPIO_X_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_X_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR3_SHIFT)
#define GPIO_X_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_X_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR2_SHIFT)
#define GPIO_X_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_X_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR1_SHIFT)
#define GPIO_X_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_X_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR0_SHIFT)
#define GPIO_X_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_X_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G7W_SHIFT)
#define GPIO_X_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_X_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G6W_SHIFT)
#define GPIO_X_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_X_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G5W_SHIFT)
#define GPIO_X_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_X_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G4W_SHIFT)
#define GPIO_X_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_X_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G3W_SHIFT)
#define GPIO_X_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_X_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G2W_SHIFT)
#define GPIO_X_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_X_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G1W_SHIFT)
#define GPIO_X_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_X_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G0W_SHIFT)
#define GPIO_X_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_X_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G7R_SHIFT)
#define GPIO_X_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_X_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G6R_SHIFT)
#define GPIO_X_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G5R_SHIFT)
#define GPIO_X_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_X_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G4R_SHIFT)
#define GPIO_X_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_X_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G3R_SHIFT)
#define GPIO_X_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_X_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G2R_SHIFT)
#define GPIO_X_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_X_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G1R_SHIFT)
#define GPIO_X_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G0R_SHIFT)
#define GPIO_X_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_X_VM_02_0
#define GPIO_X_VM_02_0                  MK_ADDR_CONST(0x1010)
#define GPIO_X_VM_02_0_SECURE                   0x0
#define GPIO_X_VM_02_0_DUAL                     0x0
#define GPIO_X_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_02_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_02_0_WORD_COUNT                       0x1
#define GPIO_X_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM1_SHIFT)
#define GPIO_X_VM_02_0_VM1_RANGE                        1:0
#define GPIO_X_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_X_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_X_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM2_SHIFT)
#define GPIO_X_VM_02_0_VM2_RANGE                        3:2
#define GPIO_X_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_X_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_X_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_X_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM3_SHIFT)
#define GPIO_X_VM_02_0_VM3_RANGE                        5:4
#define GPIO_X_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_X_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_X_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_X_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM4_SHIFT)
#define GPIO_X_VM_02_0_VM4_RANGE                        7:6
#define GPIO_X_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_X_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_X_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM5_SHIFT)
#define GPIO_X_VM_02_0_VM5_RANGE                        9:8
#define GPIO_X_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_X_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_X_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_X_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM6_SHIFT)
#define GPIO_X_VM_02_0_VM6_RANGE                        11:10
#define GPIO_X_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_X_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_X_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_X_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM7_SHIFT)
#define GPIO_X_VM_02_0_VM7_RANGE                        13:12
#define GPIO_X_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_X_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_X_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_X_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM8_SHIFT)
#define GPIO_X_VM_02_0_VM8_RANGE                        15:14
#define GPIO_X_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_X_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_X_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_02_0
#define GPIO_X_SCR_02_0                 MK_ADDR_CONST(0x1014)
#define GPIO_X_SCR_02_0_SECURE                  0x0
#define GPIO_X_SCR_02_0_DUAL                    0x0
#define GPIO_X_SCR_02_0_SCR                     0
#define GPIO_X_SCR_02_0_SCRREG                  0
#define GPIO_X_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_X_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_X_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_X_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_X_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_X_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_X_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_X_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_X_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR7_SHIFT)
#define GPIO_X_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_X_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR6_SHIFT)
#define GPIO_X_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_X_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR5_SHIFT)
#define GPIO_X_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_X_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR4_SHIFT)
#define GPIO_X_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_X_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR3_SHIFT)
#define GPIO_X_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_X_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR2_SHIFT)
#define GPIO_X_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_X_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR1_SHIFT)
#define GPIO_X_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_X_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR0_SHIFT)
#define GPIO_X_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_X_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G7W_SHIFT)
#define GPIO_X_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_X_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G6W_SHIFT)
#define GPIO_X_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_X_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G5W_SHIFT)
#define GPIO_X_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_X_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G4W_SHIFT)
#define GPIO_X_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_X_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G3W_SHIFT)
#define GPIO_X_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_X_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G2W_SHIFT)
#define GPIO_X_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_X_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G1W_SHIFT)
#define GPIO_X_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_X_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G0W_SHIFT)
#define GPIO_X_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_X_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G7R_SHIFT)
#define GPIO_X_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_X_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G6R_SHIFT)
#define GPIO_X_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G5R_SHIFT)
#define GPIO_X_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_X_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G4R_SHIFT)
#define GPIO_X_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_X_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G3R_SHIFT)
#define GPIO_X_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_X_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G2R_SHIFT)
#define GPIO_X_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_X_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G1R_SHIFT)
#define GPIO_X_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G0R_SHIFT)
#define GPIO_X_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_X_VM_03_0
#define GPIO_X_VM_03_0                  MK_ADDR_CONST(0x1018)
#define GPIO_X_VM_03_0_SECURE                   0x0
#define GPIO_X_VM_03_0_DUAL                     0x0
#define GPIO_X_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_03_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_03_0_WORD_COUNT                       0x1
#define GPIO_X_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM1_SHIFT)
#define GPIO_X_VM_03_0_VM1_RANGE                        1:0
#define GPIO_X_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_X_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_X_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM2_SHIFT)
#define GPIO_X_VM_03_0_VM2_RANGE                        3:2
#define GPIO_X_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_X_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_X_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_X_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM3_SHIFT)
#define GPIO_X_VM_03_0_VM3_RANGE                        5:4
#define GPIO_X_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_X_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_X_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_X_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM4_SHIFT)
#define GPIO_X_VM_03_0_VM4_RANGE                        7:6
#define GPIO_X_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_X_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_X_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM5_SHIFT)
#define GPIO_X_VM_03_0_VM5_RANGE                        9:8
#define GPIO_X_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_X_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_X_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_X_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM6_SHIFT)
#define GPIO_X_VM_03_0_VM6_RANGE                        11:10
#define GPIO_X_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_X_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_X_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_X_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM7_SHIFT)
#define GPIO_X_VM_03_0_VM7_RANGE                        13:12
#define GPIO_X_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_X_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_X_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_X_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM8_SHIFT)
#define GPIO_X_VM_03_0_VM8_RANGE                        15:14
#define GPIO_X_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_X_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_X_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_03_0
#define GPIO_X_SCR_03_0                 MK_ADDR_CONST(0x101c)
#define GPIO_X_SCR_03_0_SECURE                  0x0
#define GPIO_X_SCR_03_0_DUAL                    0x0
#define GPIO_X_SCR_03_0_SCR                     0
#define GPIO_X_SCR_03_0_SCRREG                  0
#define GPIO_X_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_X_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_X_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_X_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_X_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_X_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_X_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_X_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_X_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR7_SHIFT)
#define GPIO_X_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_X_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR6_SHIFT)
#define GPIO_X_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_X_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR5_SHIFT)
#define GPIO_X_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_X_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR4_SHIFT)
#define GPIO_X_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_X_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR3_SHIFT)
#define GPIO_X_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_X_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR2_SHIFT)
#define GPIO_X_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_X_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR1_SHIFT)
#define GPIO_X_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_X_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR0_SHIFT)
#define GPIO_X_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_X_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G7W_SHIFT)
#define GPIO_X_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_X_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G6W_SHIFT)
#define GPIO_X_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_X_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G5W_SHIFT)
#define GPIO_X_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_X_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G4W_SHIFT)
#define GPIO_X_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_X_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G3W_SHIFT)
#define GPIO_X_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_X_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G2W_SHIFT)
#define GPIO_X_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_X_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G1W_SHIFT)
#define GPIO_X_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_X_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G0W_SHIFT)
#define GPIO_X_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_X_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G7R_SHIFT)
#define GPIO_X_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_X_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G6R_SHIFT)
#define GPIO_X_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G5R_SHIFT)
#define GPIO_X_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_X_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G4R_SHIFT)
#define GPIO_X_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_X_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G3R_SHIFT)
#define GPIO_X_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_X_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G2R_SHIFT)
#define GPIO_X_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_X_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G1R_SHIFT)
#define GPIO_X_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G0R_SHIFT)
#define GPIO_X_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_X_VM_04_0
#define GPIO_X_VM_04_0                  MK_ADDR_CONST(0x1020)
#define GPIO_X_VM_04_0_SECURE                   0x0
#define GPIO_X_VM_04_0_DUAL                     0x0
#define GPIO_X_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_04_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_04_0_WORD_COUNT                       0x1
#define GPIO_X_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM1_SHIFT)
#define GPIO_X_VM_04_0_VM1_RANGE                        1:0
#define GPIO_X_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_X_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_X_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM2_SHIFT)
#define GPIO_X_VM_04_0_VM2_RANGE                        3:2
#define GPIO_X_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_X_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_X_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_X_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM3_SHIFT)
#define GPIO_X_VM_04_0_VM3_RANGE                        5:4
#define GPIO_X_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_X_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_X_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_X_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM4_SHIFT)
#define GPIO_X_VM_04_0_VM4_RANGE                        7:6
#define GPIO_X_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_X_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_X_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM5_SHIFT)
#define GPIO_X_VM_04_0_VM5_RANGE                        9:8
#define GPIO_X_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_X_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_X_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_X_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM6_SHIFT)
#define GPIO_X_VM_04_0_VM6_RANGE                        11:10
#define GPIO_X_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_X_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_X_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_X_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM7_SHIFT)
#define GPIO_X_VM_04_0_VM7_RANGE                        13:12
#define GPIO_X_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_X_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_X_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_X_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM8_SHIFT)
#define GPIO_X_VM_04_0_VM8_RANGE                        15:14
#define GPIO_X_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_X_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_X_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_04_0
#define GPIO_X_SCR_04_0                 MK_ADDR_CONST(0x1024)
#define GPIO_X_SCR_04_0_SECURE                  0x0
#define GPIO_X_SCR_04_0_DUAL                    0x0
#define GPIO_X_SCR_04_0_SCR                     0
#define GPIO_X_SCR_04_0_SCRREG                  0
#define GPIO_X_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_X_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_X_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_X_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_X_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_X_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_X_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_X_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_X_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR7_SHIFT)
#define GPIO_X_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_X_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR6_SHIFT)
#define GPIO_X_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_X_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR5_SHIFT)
#define GPIO_X_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_X_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR4_SHIFT)
#define GPIO_X_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_X_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR3_SHIFT)
#define GPIO_X_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_X_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR2_SHIFT)
#define GPIO_X_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_X_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR1_SHIFT)
#define GPIO_X_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_X_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR0_SHIFT)
#define GPIO_X_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_X_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G7W_SHIFT)
#define GPIO_X_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_X_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G6W_SHIFT)
#define GPIO_X_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_X_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G5W_SHIFT)
#define GPIO_X_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_X_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G4W_SHIFT)
#define GPIO_X_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_X_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G3W_SHIFT)
#define GPIO_X_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_X_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G2W_SHIFT)
#define GPIO_X_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_X_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G1W_SHIFT)
#define GPIO_X_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_X_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G0W_SHIFT)
#define GPIO_X_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_X_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G7R_SHIFT)
#define GPIO_X_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_X_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G6R_SHIFT)
#define GPIO_X_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G5R_SHIFT)
#define GPIO_X_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_X_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G4R_SHIFT)
#define GPIO_X_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_X_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G3R_SHIFT)
#define GPIO_X_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_X_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G2R_SHIFT)
#define GPIO_X_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_X_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G1R_SHIFT)
#define GPIO_X_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G0R_SHIFT)
#define GPIO_X_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_X_VM_05_0
#define GPIO_X_VM_05_0                  MK_ADDR_CONST(0x1028)
#define GPIO_X_VM_05_0_SECURE                   0x0
#define GPIO_X_VM_05_0_DUAL                     0x0
#define GPIO_X_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_05_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_05_0_WORD_COUNT                       0x1
#define GPIO_X_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM1_SHIFT)
#define GPIO_X_VM_05_0_VM1_RANGE                        1:0
#define GPIO_X_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_X_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_X_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM2_SHIFT)
#define GPIO_X_VM_05_0_VM2_RANGE                        3:2
#define GPIO_X_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_X_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_X_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_X_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM3_SHIFT)
#define GPIO_X_VM_05_0_VM3_RANGE                        5:4
#define GPIO_X_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_X_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_X_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_X_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM4_SHIFT)
#define GPIO_X_VM_05_0_VM4_RANGE                        7:6
#define GPIO_X_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_X_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_X_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM5_SHIFT)
#define GPIO_X_VM_05_0_VM5_RANGE                        9:8
#define GPIO_X_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_X_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_X_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_X_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM6_SHIFT)
#define GPIO_X_VM_05_0_VM6_RANGE                        11:10
#define GPIO_X_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_X_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_X_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_X_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM7_SHIFT)
#define GPIO_X_VM_05_0_VM7_RANGE                        13:12
#define GPIO_X_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_X_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_X_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_X_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM8_SHIFT)
#define GPIO_X_VM_05_0_VM8_RANGE                        15:14
#define GPIO_X_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_X_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_X_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_05_0
#define GPIO_X_SCR_05_0                 MK_ADDR_CONST(0x102c)
#define GPIO_X_SCR_05_0_SECURE                  0x0
#define GPIO_X_SCR_05_0_DUAL                    0x0
#define GPIO_X_SCR_05_0_SCR                     0
#define GPIO_X_SCR_05_0_SCRREG                  0
#define GPIO_X_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_X_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_X_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_X_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_X_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_X_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_X_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_X_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_X_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR7_SHIFT)
#define GPIO_X_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_X_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR6_SHIFT)
#define GPIO_X_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_X_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR5_SHIFT)
#define GPIO_X_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_X_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR4_SHIFT)
#define GPIO_X_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_X_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR3_SHIFT)
#define GPIO_X_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_X_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR2_SHIFT)
#define GPIO_X_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_X_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR1_SHIFT)
#define GPIO_X_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_X_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR0_SHIFT)
#define GPIO_X_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_X_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G7W_SHIFT)
#define GPIO_X_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_X_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G6W_SHIFT)
#define GPIO_X_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_X_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G5W_SHIFT)
#define GPIO_X_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_X_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G4W_SHIFT)
#define GPIO_X_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_X_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G3W_SHIFT)
#define GPIO_X_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_X_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G2W_SHIFT)
#define GPIO_X_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_X_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G1W_SHIFT)
#define GPIO_X_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_X_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G0W_SHIFT)
#define GPIO_X_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_X_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G7R_SHIFT)
#define GPIO_X_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_X_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G6R_SHIFT)
#define GPIO_X_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G5R_SHIFT)
#define GPIO_X_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_X_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G4R_SHIFT)
#define GPIO_X_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_X_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G3R_SHIFT)
#define GPIO_X_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_X_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G2R_SHIFT)
#define GPIO_X_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_X_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G1R_SHIFT)
#define GPIO_X_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G0R_SHIFT)
#define GPIO_X_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_X_VM_06_0
#define GPIO_X_VM_06_0                  MK_ADDR_CONST(0x1030)
#define GPIO_X_VM_06_0_SECURE                   0x0
#define GPIO_X_VM_06_0_DUAL                     0x0
#define GPIO_X_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_06_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_06_0_WORD_COUNT                       0x1
#define GPIO_X_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM1_SHIFT)
#define GPIO_X_VM_06_0_VM1_RANGE                        1:0
#define GPIO_X_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_X_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_X_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM2_SHIFT)
#define GPIO_X_VM_06_0_VM2_RANGE                        3:2
#define GPIO_X_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_X_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_X_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_X_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM3_SHIFT)
#define GPIO_X_VM_06_0_VM3_RANGE                        5:4
#define GPIO_X_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_X_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_X_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_X_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM4_SHIFT)
#define GPIO_X_VM_06_0_VM4_RANGE                        7:6
#define GPIO_X_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_X_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_X_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM5_SHIFT)
#define GPIO_X_VM_06_0_VM5_RANGE                        9:8
#define GPIO_X_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_X_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_X_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_X_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM6_SHIFT)
#define GPIO_X_VM_06_0_VM6_RANGE                        11:10
#define GPIO_X_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_X_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_X_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_X_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM7_SHIFT)
#define GPIO_X_VM_06_0_VM7_RANGE                        13:12
#define GPIO_X_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_X_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_X_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_X_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM8_SHIFT)
#define GPIO_X_VM_06_0_VM8_RANGE                        15:14
#define GPIO_X_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_X_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_X_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_06_0
#define GPIO_X_SCR_06_0                 MK_ADDR_CONST(0x1034)
#define GPIO_X_SCR_06_0_SECURE                  0x0
#define GPIO_X_SCR_06_0_DUAL                    0x0
#define GPIO_X_SCR_06_0_SCR                     0
#define GPIO_X_SCR_06_0_SCRREG                  0
#define GPIO_X_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_X_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_X_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_X_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_X_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_X_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_X_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_X_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_X_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR7_SHIFT)
#define GPIO_X_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_X_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR6_SHIFT)
#define GPIO_X_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_X_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR5_SHIFT)
#define GPIO_X_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_X_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR4_SHIFT)
#define GPIO_X_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_X_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR3_SHIFT)
#define GPIO_X_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_X_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR2_SHIFT)
#define GPIO_X_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_X_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR1_SHIFT)
#define GPIO_X_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_X_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR0_SHIFT)
#define GPIO_X_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_X_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G7W_SHIFT)
#define GPIO_X_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_X_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G6W_SHIFT)
#define GPIO_X_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_X_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G5W_SHIFT)
#define GPIO_X_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_X_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G4W_SHIFT)
#define GPIO_X_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_X_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G3W_SHIFT)
#define GPIO_X_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_X_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G2W_SHIFT)
#define GPIO_X_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_X_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G1W_SHIFT)
#define GPIO_X_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_X_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G0W_SHIFT)
#define GPIO_X_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_X_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G7R_SHIFT)
#define GPIO_X_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_X_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G6R_SHIFT)
#define GPIO_X_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G5R_SHIFT)
#define GPIO_X_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_X_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G4R_SHIFT)
#define GPIO_X_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_X_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G3R_SHIFT)
#define GPIO_X_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_X_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G2R_SHIFT)
#define GPIO_X_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_X_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G1R_SHIFT)
#define GPIO_X_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G0R_SHIFT)
#define GPIO_X_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_X_VM_07_0
#define GPIO_X_VM_07_0                  MK_ADDR_CONST(0x1038)
#define GPIO_X_VM_07_0_SECURE                   0x0
#define GPIO_X_VM_07_0_DUAL                     0x0
#define GPIO_X_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_07_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_X_VM_07_0_WORD_COUNT                       0x1
#define GPIO_X_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_X_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM1_SHIFT)
#define GPIO_X_VM_07_0_VM1_RANGE                        1:0
#define GPIO_X_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_X_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_X_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM2_SHIFT)
#define GPIO_X_VM_07_0_VM2_RANGE                        3:2
#define GPIO_X_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_X_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_X_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_X_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM3_SHIFT)
#define GPIO_X_VM_07_0_VM3_RANGE                        5:4
#define GPIO_X_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_X_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_X_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_X_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM4_SHIFT)
#define GPIO_X_VM_07_0_VM4_RANGE                        7:6
#define GPIO_X_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_X_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_X_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM5_SHIFT)
#define GPIO_X_VM_07_0_VM5_RANGE                        9:8
#define GPIO_X_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_X_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_X_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_X_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM6_SHIFT)
#define GPIO_X_VM_07_0_VM6_RANGE                        11:10
#define GPIO_X_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_X_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_X_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_X_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM7_SHIFT)
#define GPIO_X_VM_07_0_VM7_RANGE                        13:12
#define GPIO_X_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_X_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_X_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_X_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_X_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM8_SHIFT)
#define GPIO_X_VM_07_0_VM8_RANGE                        15:14
#define GPIO_X_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_X_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_X_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_X_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_X_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_SCR_07_0
#define GPIO_X_SCR_07_0                 MK_ADDR_CONST(0x103c)
#define GPIO_X_SCR_07_0_SECURE                  0x0
#define GPIO_X_SCR_07_0_DUAL                    0x0
#define GPIO_X_SCR_07_0_SCR                     0
#define GPIO_X_SCR_07_0_SCRREG                  0
#define GPIO_X_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_X_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_X_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_X_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_X_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_X_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_X_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_X_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_X_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_X_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_X_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_X_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_X_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_X_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_X_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_X_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_X_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_X_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_X_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_X_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_X_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_X_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_X_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_X_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR7_SHIFT)
#define GPIO_X_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_X_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_X_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_X_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR6_SHIFT)
#define GPIO_X_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_X_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_X_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_X_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR5_SHIFT)
#define GPIO_X_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_X_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_X_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_X_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR4_SHIFT)
#define GPIO_X_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_X_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_X_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_X_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR3_SHIFT)
#define GPIO_X_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_X_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_X_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_X_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR2_SHIFT)
#define GPIO_X_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_X_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_X_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_X_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR1_SHIFT)
#define GPIO_X_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_X_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_X_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_X_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR0_SHIFT)
#define GPIO_X_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_X_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_X_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_X_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G7W_SHIFT)
#define GPIO_X_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_X_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_X_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_X_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G6W_SHIFT)
#define GPIO_X_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_X_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_X_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_X_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G5W_SHIFT)
#define GPIO_X_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_X_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_X_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_X_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G4W_SHIFT)
#define GPIO_X_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_X_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_X_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_X_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G3W_SHIFT)
#define GPIO_X_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_X_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_X_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_X_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G2W_SHIFT)
#define GPIO_X_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_X_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_X_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_X_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G1W_SHIFT)
#define GPIO_X_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_X_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_X_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_X_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G0W_SHIFT)
#define GPIO_X_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_X_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_X_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_X_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G7R_SHIFT)
#define GPIO_X_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_X_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_X_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_X_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G6R_SHIFT)
#define GPIO_X_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_X_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_X_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G5R_SHIFT)
#define GPIO_X_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_X_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_X_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G4R_SHIFT)
#define GPIO_X_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_X_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_X_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_X_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G3R_SHIFT)
#define GPIO_X_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_X_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_X_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_X_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G2R_SHIFT)
#define GPIO_X_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_X_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_X_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_X_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G1R_SHIFT)
#define GPIO_X_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_X_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_X_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_X_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G0R_SHIFT)
#define GPIO_X_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_X_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_X_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_X_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_00_0
#define GPIO_Y_VM_00_0                  MK_ADDR_CONST(0x1040)
#define GPIO_Y_VM_00_0_SECURE                   0x0
#define GPIO_Y_VM_00_0_DUAL                     0x0
#define GPIO_Y_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_00_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_00_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM1_SHIFT)
#define GPIO_Y_VM_00_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Y_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Y_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM2_SHIFT)
#define GPIO_Y_VM_00_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Y_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Y_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Y_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM3_SHIFT)
#define GPIO_Y_VM_00_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Y_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Y_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Y_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM4_SHIFT)
#define GPIO_Y_VM_00_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Y_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Y_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM5_SHIFT)
#define GPIO_Y_VM_00_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Y_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Y_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Y_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM6_SHIFT)
#define GPIO_Y_VM_00_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Y_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Y_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Y_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM7_SHIFT)
#define GPIO_Y_VM_00_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Y_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Y_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Y_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM8_SHIFT)
#define GPIO_Y_VM_00_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Y_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Y_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_00_0
#define GPIO_Y_SCR_00_0                 MK_ADDR_CONST(0x1044)
#define GPIO_Y_SCR_00_0_SECURE                  0x0
#define GPIO_Y_SCR_00_0_DUAL                    0x0
#define GPIO_Y_SCR_00_0_SCR                     0
#define GPIO_Y_SCR_00_0_SCRREG                  0
#define GPIO_Y_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Y_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR7_SHIFT)
#define GPIO_Y_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR6_SHIFT)
#define GPIO_Y_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR5_SHIFT)
#define GPIO_Y_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR4_SHIFT)
#define GPIO_Y_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR3_SHIFT)
#define GPIO_Y_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR2_SHIFT)
#define GPIO_Y_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR1_SHIFT)
#define GPIO_Y_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR0_SHIFT)
#define GPIO_Y_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G7W_SHIFT)
#define GPIO_Y_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G6W_SHIFT)
#define GPIO_Y_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G5W_SHIFT)
#define GPIO_Y_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G4W_SHIFT)
#define GPIO_Y_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G3W_SHIFT)
#define GPIO_Y_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G2W_SHIFT)
#define GPIO_Y_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G1W_SHIFT)
#define GPIO_Y_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G0W_SHIFT)
#define GPIO_Y_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G7R_SHIFT)
#define GPIO_Y_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G6R_SHIFT)
#define GPIO_Y_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G5R_SHIFT)
#define GPIO_Y_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G4R_SHIFT)
#define GPIO_Y_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G3R_SHIFT)
#define GPIO_Y_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G2R_SHIFT)
#define GPIO_Y_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G1R_SHIFT)
#define GPIO_Y_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G0R_SHIFT)
#define GPIO_Y_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_01_0
#define GPIO_Y_VM_01_0                  MK_ADDR_CONST(0x1048)
#define GPIO_Y_VM_01_0_SECURE                   0x0
#define GPIO_Y_VM_01_0_DUAL                     0x0
#define GPIO_Y_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_01_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_01_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM1_SHIFT)
#define GPIO_Y_VM_01_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Y_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Y_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM2_SHIFT)
#define GPIO_Y_VM_01_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Y_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Y_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Y_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM3_SHIFT)
#define GPIO_Y_VM_01_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Y_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Y_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Y_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM4_SHIFT)
#define GPIO_Y_VM_01_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Y_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Y_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM5_SHIFT)
#define GPIO_Y_VM_01_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Y_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Y_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Y_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM6_SHIFT)
#define GPIO_Y_VM_01_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Y_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Y_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Y_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM7_SHIFT)
#define GPIO_Y_VM_01_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Y_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Y_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Y_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM8_SHIFT)
#define GPIO_Y_VM_01_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Y_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Y_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_01_0
#define GPIO_Y_SCR_01_0                 MK_ADDR_CONST(0x104c)
#define GPIO_Y_SCR_01_0_SECURE                  0x0
#define GPIO_Y_SCR_01_0_DUAL                    0x0
#define GPIO_Y_SCR_01_0_SCR                     0
#define GPIO_Y_SCR_01_0_SCRREG                  0
#define GPIO_Y_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Y_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR7_SHIFT)
#define GPIO_Y_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR6_SHIFT)
#define GPIO_Y_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR5_SHIFT)
#define GPIO_Y_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR4_SHIFT)
#define GPIO_Y_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR3_SHIFT)
#define GPIO_Y_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR2_SHIFT)
#define GPIO_Y_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR1_SHIFT)
#define GPIO_Y_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR0_SHIFT)
#define GPIO_Y_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G7W_SHIFT)
#define GPIO_Y_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G6W_SHIFT)
#define GPIO_Y_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G5W_SHIFT)
#define GPIO_Y_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G4W_SHIFT)
#define GPIO_Y_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G3W_SHIFT)
#define GPIO_Y_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G2W_SHIFT)
#define GPIO_Y_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G1W_SHIFT)
#define GPIO_Y_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G0W_SHIFT)
#define GPIO_Y_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G7R_SHIFT)
#define GPIO_Y_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G6R_SHIFT)
#define GPIO_Y_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G5R_SHIFT)
#define GPIO_Y_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G4R_SHIFT)
#define GPIO_Y_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G3R_SHIFT)
#define GPIO_Y_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G2R_SHIFT)
#define GPIO_Y_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G1R_SHIFT)
#define GPIO_Y_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G0R_SHIFT)
#define GPIO_Y_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_02_0
#define GPIO_Y_VM_02_0                  MK_ADDR_CONST(0x1050)
#define GPIO_Y_VM_02_0_SECURE                   0x0
#define GPIO_Y_VM_02_0_DUAL                     0x0
#define GPIO_Y_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_02_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_02_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM1_SHIFT)
#define GPIO_Y_VM_02_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Y_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Y_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM2_SHIFT)
#define GPIO_Y_VM_02_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Y_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Y_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Y_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM3_SHIFT)
#define GPIO_Y_VM_02_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Y_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Y_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Y_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM4_SHIFT)
#define GPIO_Y_VM_02_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Y_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Y_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM5_SHIFT)
#define GPIO_Y_VM_02_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Y_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Y_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Y_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM6_SHIFT)
#define GPIO_Y_VM_02_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Y_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Y_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Y_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM7_SHIFT)
#define GPIO_Y_VM_02_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Y_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Y_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Y_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM8_SHIFT)
#define GPIO_Y_VM_02_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Y_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Y_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_02_0
#define GPIO_Y_SCR_02_0                 MK_ADDR_CONST(0x1054)
#define GPIO_Y_SCR_02_0_SECURE                  0x0
#define GPIO_Y_SCR_02_0_DUAL                    0x0
#define GPIO_Y_SCR_02_0_SCR                     0
#define GPIO_Y_SCR_02_0_SCRREG                  0
#define GPIO_Y_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Y_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR7_SHIFT)
#define GPIO_Y_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR6_SHIFT)
#define GPIO_Y_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR5_SHIFT)
#define GPIO_Y_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR4_SHIFT)
#define GPIO_Y_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR3_SHIFT)
#define GPIO_Y_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR2_SHIFT)
#define GPIO_Y_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR1_SHIFT)
#define GPIO_Y_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR0_SHIFT)
#define GPIO_Y_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G7W_SHIFT)
#define GPIO_Y_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G6W_SHIFT)
#define GPIO_Y_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G5W_SHIFT)
#define GPIO_Y_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G4W_SHIFT)
#define GPIO_Y_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G3W_SHIFT)
#define GPIO_Y_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G2W_SHIFT)
#define GPIO_Y_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G1W_SHIFT)
#define GPIO_Y_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G0W_SHIFT)
#define GPIO_Y_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G7R_SHIFT)
#define GPIO_Y_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G6R_SHIFT)
#define GPIO_Y_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G5R_SHIFT)
#define GPIO_Y_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G4R_SHIFT)
#define GPIO_Y_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G3R_SHIFT)
#define GPIO_Y_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G2R_SHIFT)
#define GPIO_Y_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G1R_SHIFT)
#define GPIO_Y_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G0R_SHIFT)
#define GPIO_Y_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_03_0
#define GPIO_Y_VM_03_0                  MK_ADDR_CONST(0x1058)
#define GPIO_Y_VM_03_0_SECURE                   0x0
#define GPIO_Y_VM_03_0_DUAL                     0x0
#define GPIO_Y_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_03_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_03_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM1_SHIFT)
#define GPIO_Y_VM_03_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Y_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Y_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM2_SHIFT)
#define GPIO_Y_VM_03_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Y_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Y_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Y_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM3_SHIFT)
#define GPIO_Y_VM_03_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Y_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Y_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Y_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM4_SHIFT)
#define GPIO_Y_VM_03_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Y_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Y_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM5_SHIFT)
#define GPIO_Y_VM_03_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Y_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Y_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Y_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM6_SHIFT)
#define GPIO_Y_VM_03_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Y_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Y_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Y_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM7_SHIFT)
#define GPIO_Y_VM_03_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Y_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Y_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Y_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM8_SHIFT)
#define GPIO_Y_VM_03_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Y_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Y_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_03_0
#define GPIO_Y_SCR_03_0                 MK_ADDR_CONST(0x105c)
#define GPIO_Y_SCR_03_0_SECURE                  0x0
#define GPIO_Y_SCR_03_0_DUAL                    0x0
#define GPIO_Y_SCR_03_0_SCR                     0
#define GPIO_Y_SCR_03_0_SCRREG                  0
#define GPIO_Y_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Y_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR7_SHIFT)
#define GPIO_Y_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR6_SHIFT)
#define GPIO_Y_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR5_SHIFT)
#define GPIO_Y_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR4_SHIFT)
#define GPIO_Y_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR3_SHIFT)
#define GPIO_Y_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR2_SHIFT)
#define GPIO_Y_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR1_SHIFT)
#define GPIO_Y_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR0_SHIFT)
#define GPIO_Y_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G7W_SHIFT)
#define GPIO_Y_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G6W_SHIFT)
#define GPIO_Y_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G5W_SHIFT)
#define GPIO_Y_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G4W_SHIFT)
#define GPIO_Y_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G3W_SHIFT)
#define GPIO_Y_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G2W_SHIFT)
#define GPIO_Y_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G1W_SHIFT)
#define GPIO_Y_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G0W_SHIFT)
#define GPIO_Y_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G7R_SHIFT)
#define GPIO_Y_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G6R_SHIFT)
#define GPIO_Y_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G5R_SHIFT)
#define GPIO_Y_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G4R_SHIFT)
#define GPIO_Y_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G3R_SHIFT)
#define GPIO_Y_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G2R_SHIFT)
#define GPIO_Y_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G1R_SHIFT)
#define GPIO_Y_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G0R_SHIFT)
#define GPIO_Y_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_04_0
#define GPIO_Y_VM_04_0                  MK_ADDR_CONST(0x1060)
#define GPIO_Y_VM_04_0_SECURE                   0x0
#define GPIO_Y_VM_04_0_DUAL                     0x0
#define GPIO_Y_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_04_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_04_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM1_SHIFT)
#define GPIO_Y_VM_04_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Y_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Y_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM2_SHIFT)
#define GPIO_Y_VM_04_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Y_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Y_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Y_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM3_SHIFT)
#define GPIO_Y_VM_04_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Y_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Y_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Y_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM4_SHIFT)
#define GPIO_Y_VM_04_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Y_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Y_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM5_SHIFT)
#define GPIO_Y_VM_04_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Y_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Y_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Y_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM6_SHIFT)
#define GPIO_Y_VM_04_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Y_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Y_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Y_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM7_SHIFT)
#define GPIO_Y_VM_04_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Y_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Y_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Y_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM8_SHIFT)
#define GPIO_Y_VM_04_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Y_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Y_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_04_0
#define GPIO_Y_SCR_04_0                 MK_ADDR_CONST(0x1064)
#define GPIO_Y_SCR_04_0_SECURE                  0x0
#define GPIO_Y_SCR_04_0_DUAL                    0x0
#define GPIO_Y_SCR_04_0_SCR                     0
#define GPIO_Y_SCR_04_0_SCRREG                  0
#define GPIO_Y_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Y_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR7_SHIFT)
#define GPIO_Y_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR6_SHIFT)
#define GPIO_Y_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR5_SHIFT)
#define GPIO_Y_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR4_SHIFT)
#define GPIO_Y_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR3_SHIFT)
#define GPIO_Y_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR2_SHIFT)
#define GPIO_Y_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR1_SHIFT)
#define GPIO_Y_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR0_SHIFT)
#define GPIO_Y_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G7W_SHIFT)
#define GPIO_Y_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G6W_SHIFT)
#define GPIO_Y_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G5W_SHIFT)
#define GPIO_Y_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G4W_SHIFT)
#define GPIO_Y_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G3W_SHIFT)
#define GPIO_Y_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G2W_SHIFT)
#define GPIO_Y_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G1W_SHIFT)
#define GPIO_Y_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G0W_SHIFT)
#define GPIO_Y_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G7R_SHIFT)
#define GPIO_Y_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G6R_SHIFT)
#define GPIO_Y_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G5R_SHIFT)
#define GPIO_Y_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G4R_SHIFT)
#define GPIO_Y_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G3R_SHIFT)
#define GPIO_Y_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G2R_SHIFT)
#define GPIO_Y_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G1R_SHIFT)
#define GPIO_Y_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G0R_SHIFT)
#define GPIO_Y_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_05_0
#define GPIO_Y_VM_05_0                  MK_ADDR_CONST(0x1068)
#define GPIO_Y_VM_05_0_SECURE                   0x0
#define GPIO_Y_VM_05_0_DUAL                     0x0
#define GPIO_Y_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_05_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_05_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM1_SHIFT)
#define GPIO_Y_VM_05_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Y_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Y_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM2_SHIFT)
#define GPIO_Y_VM_05_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Y_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Y_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Y_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM3_SHIFT)
#define GPIO_Y_VM_05_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Y_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Y_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Y_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM4_SHIFT)
#define GPIO_Y_VM_05_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Y_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Y_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM5_SHIFT)
#define GPIO_Y_VM_05_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Y_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Y_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Y_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM6_SHIFT)
#define GPIO_Y_VM_05_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Y_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Y_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Y_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM7_SHIFT)
#define GPIO_Y_VM_05_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Y_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Y_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Y_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM8_SHIFT)
#define GPIO_Y_VM_05_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Y_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Y_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_05_0
#define GPIO_Y_SCR_05_0                 MK_ADDR_CONST(0x106c)
#define GPIO_Y_SCR_05_0_SECURE                  0x0
#define GPIO_Y_SCR_05_0_DUAL                    0x0
#define GPIO_Y_SCR_05_0_SCR                     0
#define GPIO_Y_SCR_05_0_SCRREG                  0
#define GPIO_Y_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Y_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR7_SHIFT)
#define GPIO_Y_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR6_SHIFT)
#define GPIO_Y_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR5_SHIFT)
#define GPIO_Y_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR4_SHIFT)
#define GPIO_Y_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR3_SHIFT)
#define GPIO_Y_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR2_SHIFT)
#define GPIO_Y_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR1_SHIFT)
#define GPIO_Y_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR0_SHIFT)
#define GPIO_Y_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G7W_SHIFT)
#define GPIO_Y_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G6W_SHIFT)
#define GPIO_Y_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G5W_SHIFT)
#define GPIO_Y_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G4W_SHIFT)
#define GPIO_Y_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G3W_SHIFT)
#define GPIO_Y_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G2W_SHIFT)
#define GPIO_Y_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G1W_SHIFT)
#define GPIO_Y_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G0W_SHIFT)
#define GPIO_Y_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G7R_SHIFT)
#define GPIO_Y_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G6R_SHIFT)
#define GPIO_Y_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G5R_SHIFT)
#define GPIO_Y_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G4R_SHIFT)
#define GPIO_Y_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G3R_SHIFT)
#define GPIO_Y_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G2R_SHIFT)
#define GPIO_Y_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G1R_SHIFT)
#define GPIO_Y_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G0R_SHIFT)
#define GPIO_Y_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_06_0
#define GPIO_Y_VM_06_0                  MK_ADDR_CONST(0x1070)
#define GPIO_Y_VM_06_0_SECURE                   0x0
#define GPIO_Y_VM_06_0_DUAL                     0x0
#define GPIO_Y_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_06_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_06_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM1_SHIFT)
#define GPIO_Y_VM_06_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Y_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Y_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM2_SHIFT)
#define GPIO_Y_VM_06_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Y_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Y_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Y_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM3_SHIFT)
#define GPIO_Y_VM_06_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Y_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Y_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Y_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM4_SHIFT)
#define GPIO_Y_VM_06_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Y_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Y_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM5_SHIFT)
#define GPIO_Y_VM_06_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Y_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Y_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Y_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM6_SHIFT)
#define GPIO_Y_VM_06_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Y_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Y_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Y_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM7_SHIFT)
#define GPIO_Y_VM_06_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Y_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Y_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Y_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM8_SHIFT)
#define GPIO_Y_VM_06_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Y_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Y_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_06_0
#define GPIO_Y_SCR_06_0                 MK_ADDR_CONST(0x1074)
#define GPIO_Y_SCR_06_0_SECURE                  0x0
#define GPIO_Y_SCR_06_0_DUAL                    0x0
#define GPIO_Y_SCR_06_0_SCR                     0
#define GPIO_Y_SCR_06_0_SCRREG                  0
#define GPIO_Y_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Y_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR7_SHIFT)
#define GPIO_Y_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR6_SHIFT)
#define GPIO_Y_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR5_SHIFT)
#define GPIO_Y_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR4_SHIFT)
#define GPIO_Y_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR3_SHIFT)
#define GPIO_Y_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR2_SHIFT)
#define GPIO_Y_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR1_SHIFT)
#define GPIO_Y_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR0_SHIFT)
#define GPIO_Y_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G7W_SHIFT)
#define GPIO_Y_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G6W_SHIFT)
#define GPIO_Y_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G5W_SHIFT)
#define GPIO_Y_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G4W_SHIFT)
#define GPIO_Y_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G3W_SHIFT)
#define GPIO_Y_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G2W_SHIFT)
#define GPIO_Y_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G1W_SHIFT)
#define GPIO_Y_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G0W_SHIFT)
#define GPIO_Y_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G7R_SHIFT)
#define GPIO_Y_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G6R_SHIFT)
#define GPIO_Y_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G5R_SHIFT)
#define GPIO_Y_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G4R_SHIFT)
#define GPIO_Y_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G3R_SHIFT)
#define GPIO_Y_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G2R_SHIFT)
#define GPIO_Y_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G1R_SHIFT)
#define GPIO_Y_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G0R_SHIFT)
#define GPIO_Y_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Y_VM_07_0
#define GPIO_Y_VM_07_0                  MK_ADDR_CONST(0x1078)
#define GPIO_Y_VM_07_0_SECURE                   0x0
#define GPIO_Y_VM_07_0_DUAL                     0x0
#define GPIO_Y_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_07_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Y_VM_07_0_WORD_COUNT                       0x1
#define GPIO_Y_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Y_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM1_SHIFT)
#define GPIO_Y_VM_07_0_VM1_RANGE                        1:0
#define GPIO_Y_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Y_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Y_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM2_SHIFT)
#define GPIO_Y_VM_07_0_VM2_RANGE                        3:2
#define GPIO_Y_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Y_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Y_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Y_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM3_SHIFT)
#define GPIO_Y_VM_07_0_VM3_RANGE                        5:4
#define GPIO_Y_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Y_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Y_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Y_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM4_SHIFT)
#define GPIO_Y_VM_07_0_VM4_RANGE                        7:6
#define GPIO_Y_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Y_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Y_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM5_SHIFT)
#define GPIO_Y_VM_07_0_VM5_RANGE                        9:8
#define GPIO_Y_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Y_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Y_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Y_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM6_SHIFT)
#define GPIO_Y_VM_07_0_VM6_RANGE                        11:10
#define GPIO_Y_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Y_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Y_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Y_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM7_SHIFT)
#define GPIO_Y_VM_07_0_VM7_RANGE                        13:12
#define GPIO_Y_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Y_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Y_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Y_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Y_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM8_SHIFT)
#define GPIO_Y_VM_07_0_VM8_RANGE                        15:14
#define GPIO_Y_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Y_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Y_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_Y_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Y_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_SCR_07_0
#define GPIO_Y_SCR_07_0                 MK_ADDR_CONST(0x107c)
#define GPIO_Y_SCR_07_0_SECURE                  0x0
#define GPIO_Y_SCR_07_0_DUAL                    0x0
#define GPIO_Y_SCR_07_0_SCR                     0
#define GPIO_Y_SCR_07_0_SCRREG                  0
#define GPIO_Y_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_Y_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Y_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_Y_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_Y_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Y_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Y_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_Y_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_Y_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Y_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Y_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_Y_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_Y_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Y_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Y_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_Y_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Y_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Y_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Y_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Y_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Y_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR7_SHIFT)
#define GPIO_Y_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_Y_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Y_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR6_SHIFT)
#define GPIO_Y_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_Y_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Y_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR5_SHIFT)
#define GPIO_Y_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_Y_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Y_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR4_SHIFT)
#define GPIO_Y_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_Y_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Y_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR3_SHIFT)
#define GPIO_Y_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_Y_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Y_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR2_SHIFT)
#define GPIO_Y_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_Y_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Y_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR1_SHIFT)
#define GPIO_Y_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_Y_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Y_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR0_SHIFT)
#define GPIO_Y_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_Y_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Y_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G7W_SHIFT)
#define GPIO_Y_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_Y_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Y_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G6W_SHIFT)
#define GPIO_Y_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_Y_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Y_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G5W_SHIFT)
#define GPIO_Y_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_Y_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Y_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G4W_SHIFT)
#define GPIO_Y_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_Y_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Y_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G3W_SHIFT)
#define GPIO_Y_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_Y_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Y_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G2W_SHIFT)
#define GPIO_Y_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_Y_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Y_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G1W_SHIFT)
#define GPIO_Y_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_Y_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Y_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G0W_SHIFT)
#define GPIO_Y_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_Y_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Y_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G7R_SHIFT)
#define GPIO_Y_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_Y_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Y_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G6R_SHIFT)
#define GPIO_Y_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_Y_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Y_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G5R_SHIFT)
#define GPIO_Y_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_Y_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G4R_SHIFT)
#define GPIO_Y_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_Y_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Y_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G3R_SHIFT)
#define GPIO_Y_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_Y_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Y_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G2R_SHIFT)
#define GPIO_Y_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_Y_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Y_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G1R_SHIFT)
#define GPIO_Y_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_Y_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Y_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Y_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G0R_SHIFT)
#define GPIO_Y_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_Y_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_Y_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Y_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_00_0
#define GPIO_Z_VM_00_0                  MK_ADDR_CONST(0x1080)
#define GPIO_Z_VM_00_0_SECURE                   0x0
#define GPIO_Z_VM_00_0_DUAL                     0x0
#define GPIO_Z_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_00_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_00_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM1_SHIFT)
#define GPIO_Z_VM_00_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Z_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Z_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM2_SHIFT)
#define GPIO_Z_VM_00_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Z_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Z_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Z_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM3_SHIFT)
#define GPIO_Z_VM_00_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Z_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Z_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Z_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM4_SHIFT)
#define GPIO_Z_VM_00_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Z_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Z_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM5_SHIFT)
#define GPIO_Z_VM_00_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Z_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Z_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Z_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM6_SHIFT)
#define GPIO_Z_VM_00_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Z_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Z_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Z_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM7_SHIFT)
#define GPIO_Z_VM_00_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Z_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Z_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Z_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM8_SHIFT)
#define GPIO_Z_VM_00_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Z_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Z_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_00_0
#define GPIO_Z_SCR_00_0                 MK_ADDR_CONST(0x1084)
#define GPIO_Z_SCR_00_0_SECURE                  0x0
#define GPIO_Z_SCR_00_0_DUAL                    0x0
#define GPIO_Z_SCR_00_0_SCR                     0
#define GPIO_Z_SCR_00_0_SCRREG                  0
#define GPIO_Z_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Z_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR7_SHIFT)
#define GPIO_Z_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR6_SHIFT)
#define GPIO_Z_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR5_SHIFT)
#define GPIO_Z_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR4_SHIFT)
#define GPIO_Z_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR3_SHIFT)
#define GPIO_Z_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR2_SHIFT)
#define GPIO_Z_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR1_SHIFT)
#define GPIO_Z_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR0_SHIFT)
#define GPIO_Z_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G7W_SHIFT)
#define GPIO_Z_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G6W_SHIFT)
#define GPIO_Z_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G5W_SHIFT)
#define GPIO_Z_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G4W_SHIFT)
#define GPIO_Z_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G3W_SHIFT)
#define GPIO_Z_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G2W_SHIFT)
#define GPIO_Z_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G1W_SHIFT)
#define GPIO_Z_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G0W_SHIFT)
#define GPIO_Z_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G7R_SHIFT)
#define GPIO_Z_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G6R_SHIFT)
#define GPIO_Z_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G5R_SHIFT)
#define GPIO_Z_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G4R_SHIFT)
#define GPIO_Z_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G3R_SHIFT)
#define GPIO_Z_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G2R_SHIFT)
#define GPIO_Z_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G1R_SHIFT)
#define GPIO_Z_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G0R_SHIFT)
#define GPIO_Z_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_01_0
#define GPIO_Z_VM_01_0                  MK_ADDR_CONST(0x1088)
#define GPIO_Z_VM_01_0_SECURE                   0x0
#define GPIO_Z_VM_01_0_DUAL                     0x0
#define GPIO_Z_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_01_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_01_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM1_SHIFT)
#define GPIO_Z_VM_01_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Z_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Z_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM2_SHIFT)
#define GPIO_Z_VM_01_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Z_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Z_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Z_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM3_SHIFT)
#define GPIO_Z_VM_01_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Z_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Z_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Z_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM4_SHIFT)
#define GPIO_Z_VM_01_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Z_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Z_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM5_SHIFT)
#define GPIO_Z_VM_01_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Z_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Z_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Z_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM6_SHIFT)
#define GPIO_Z_VM_01_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Z_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Z_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Z_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM7_SHIFT)
#define GPIO_Z_VM_01_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Z_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Z_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Z_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM8_SHIFT)
#define GPIO_Z_VM_01_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Z_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Z_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_01_0
#define GPIO_Z_SCR_01_0                 MK_ADDR_CONST(0x108c)
#define GPIO_Z_SCR_01_0_SECURE                  0x0
#define GPIO_Z_SCR_01_0_DUAL                    0x0
#define GPIO_Z_SCR_01_0_SCR                     0
#define GPIO_Z_SCR_01_0_SCRREG                  0
#define GPIO_Z_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Z_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR7_SHIFT)
#define GPIO_Z_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR6_SHIFT)
#define GPIO_Z_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR5_SHIFT)
#define GPIO_Z_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR4_SHIFT)
#define GPIO_Z_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR3_SHIFT)
#define GPIO_Z_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR2_SHIFT)
#define GPIO_Z_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR1_SHIFT)
#define GPIO_Z_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR0_SHIFT)
#define GPIO_Z_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G7W_SHIFT)
#define GPIO_Z_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G6W_SHIFT)
#define GPIO_Z_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G5W_SHIFT)
#define GPIO_Z_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G4W_SHIFT)
#define GPIO_Z_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G3W_SHIFT)
#define GPIO_Z_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G2W_SHIFT)
#define GPIO_Z_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G1W_SHIFT)
#define GPIO_Z_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G0W_SHIFT)
#define GPIO_Z_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G7R_SHIFT)
#define GPIO_Z_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G6R_SHIFT)
#define GPIO_Z_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G5R_SHIFT)
#define GPIO_Z_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G4R_SHIFT)
#define GPIO_Z_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G3R_SHIFT)
#define GPIO_Z_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G2R_SHIFT)
#define GPIO_Z_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G1R_SHIFT)
#define GPIO_Z_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G0R_SHIFT)
#define GPIO_Z_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_02_0
#define GPIO_Z_VM_02_0                  MK_ADDR_CONST(0x1090)
#define GPIO_Z_VM_02_0_SECURE                   0x0
#define GPIO_Z_VM_02_0_DUAL                     0x0
#define GPIO_Z_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_02_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_02_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM1_SHIFT)
#define GPIO_Z_VM_02_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Z_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Z_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM2_SHIFT)
#define GPIO_Z_VM_02_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Z_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Z_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Z_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM3_SHIFT)
#define GPIO_Z_VM_02_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Z_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Z_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Z_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM4_SHIFT)
#define GPIO_Z_VM_02_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Z_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Z_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM5_SHIFT)
#define GPIO_Z_VM_02_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Z_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Z_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Z_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM6_SHIFT)
#define GPIO_Z_VM_02_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Z_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Z_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Z_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM7_SHIFT)
#define GPIO_Z_VM_02_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Z_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Z_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Z_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM8_SHIFT)
#define GPIO_Z_VM_02_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Z_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Z_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_02_0
#define GPIO_Z_SCR_02_0                 MK_ADDR_CONST(0x1094)
#define GPIO_Z_SCR_02_0_SECURE                  0x0
#define GPIO_Z_SCR_02_0_DUAL                    0x0
#define GPIO_Z_SCR_02_0_SCR                     0
#define GPIO_Z_SCR_02_0_SCRREG                  0
#define GPIO_Z_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Z_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR7_SHIFT)
#define GPIO_Z_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR6_SHIFT)
#define GPIO_Z_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR5_SHIFT)
#define GPIO_Z_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR4_SHIFT)
#define GPIO_Z_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR3_SHIFT)
#define GPIO_Z_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR2_SHIFT)
#define GPIO_Z_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR1_SHIFT)
#define GPIO_Z_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR0_SHIFT)
#define GPIO_Z_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G7W_SHIFT)
#define GPIO_Z_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G6W_SHIFT)
#define GPIO_Z_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G5W_SHIFT)
#define GPIO_Z_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G4W_SHIFT)
#define GPIO_Z_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G3W_SHIFT)
#define GPIO_Z_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G2W_SHIFT)
#define GPIO_Z_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G1W_SHIFT)
#define GPIO_Z_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G0W_SHIFT)
#define GPIO_Z_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G7R_SHIFT)
#define GPIO_Z_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G6R_SHIFT)
#define GPIO_Z_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G5R_SHIFT)
#define GPIO_Z_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G4R_SHIFT)
#define GPIO_Z_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G3R_SHIFT)
#define GPIO_Z_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G2R_SHIFT)
#define GPIO_Z_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G1R_SHIFT)
#define GPIO_Z_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G0R_SHIFT)
#define GPIO_Z_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_03_0
#define GPIO_Z_VM_03_0                  MK_ADDR_CONST(0x1098)
#define GPIO_Z_VM_03_0_SECURE                   0x0
#define GPIO_Z_VM_03_0_DUAL                     0x0
#define GPIO_Z_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_03_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_03_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM1_SHIFT)
#define GPIO_Z_VM_03_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Z_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Z_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM2_SHIFT)
#define GPIO_Z_VM_03_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Z_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Z_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Z_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM3_SHIFT)
#define GPIO_Z_VM_03_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Z_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Z_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Z_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM4_SHIFT)
#define GPIO_Z_VM_03_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Z_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Z_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM5_SHIFT)
#define GPIO_Z_VM_03_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Z_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Z_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Z_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM6_SHIFT)
#define GPIO_Z_VM_03_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Z_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Z_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Z_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM7_SHIFT)
#define GPIO_Z_VM_03_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Z_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Z_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Z_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM8_SHIFT)
#define GPIO_Z_VM_03_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Z_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Z_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_03_0
#define GPIO_Z_SCR_03_0                 MK_ADDR_CONST(0x109c)
#define GPIO_Z_SCR_03_0_SECURE                  0x0
#define GPIO_Z_SCR_03_0_DUAL                    0x0
#define GPIO_Z_SCR_03_0_SCR                     0
#define GPIO_Z_SCR_03_0_SCRREG                  0
#define GPIO_Z_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Z_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR7_SHIFT)
#define GPIO_Z_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR6_SHIFT)
#define GPIO_Z_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR5_SHIFT)
#define GPIO_Z_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR4_SHIFT)
#define GPIO_Z_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR3_SHIFT)
#define GPIO_Z_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR2_SHIFT)
#define GPIO_Z_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR1_SHIFT)
#define GPIO_Z_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR0_SHIFT)
#define GPIO_Z_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G7W_SHIFT)
#define GPIO_Z_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G6W_SHIFT)
#define GPIO_Z_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G5W_SHIFT)
#define GPIO_Z_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G4W_SHIFT)
#define GPIO_Z_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G3W_SHIFT)
#define GPIO_Z_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G2W_SHIFT)
#define GPIO_Z_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G1W_SHIFT)
#define GPIO_Z_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G0W_SHIFT)
#define GPIO_Z_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G7R_SHIFT)
#define GPIO_Z_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G6R_SHIFT)
#define GPIO_Z_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G5R_SHIFT)
#define GPIO_Z_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G4R_SHIFT)
#define GPIO_Z_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G3R_SHIFT)
#define GPIO_Z_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G2R_SHIFT)
#define GPIO_Z_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G1R_SHIFT)
#define GPIO_Z_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G0R_SHIFT)
#define GPIO_Z_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_04_0
#define GPIO_Z_VM_04_0                  MK_ADDR_CONST(0x10a0)
#define GPIO_Z_VM_04_0_SECURE                   0x0
#define GPIO_Z_VM_04_0_DUAL                     0x0
#define GPIO_Z_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_04_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_04_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM1_SHIFT)
#define GPIO_Z_VM_04_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Z_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Z_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM2_SHIFT)
#define GPIO_Z_VM_04_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Z_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Z_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Z_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM3_SHIFT)
#define GPIO_Z_VM_04_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Z_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Z_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Z_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM4_SHIFT)
#define GPIO_Z_VM_04_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Z_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Z_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM5_SHIFT)
#define GPIO_Z_VM_04_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Z_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Z_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Z_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM6_SHIFT)
#define GPIO_Z_VM_04_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Z_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Z_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Z_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM7_SHIFT)
#define GPIO_Z_VM_04_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Z_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Z_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Z_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM8_SHIFT)
#define GPIO_Z_VM_04_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Z_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Z_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_04_0
#define GPIO_Z_SCR_04_0                 MK_ADDR_CONST(0x10a4)
#define GPIO_Z_SCR_04_0_SECURE                  0x0
#define GPIO_Z_SCR_04_0_DUAL                    0x0
#define GPIO_Z_SCR_04_0_SCR                     0
#define GPIO_Z_SCR_04_0_SCRREG                  0
#define GPIO_Z_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Z_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR7_SHIFT)
#define GPIO_Z_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR6_SHIFT)
#define GPIO_Z_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR5_SHIFT)
#define GPIO_Z_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR4_SHIFT)
#define GPIO_Z_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR3_SHIFT)
#define GPIO_Z_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR2_SHIFT)
#define GPIO_Z_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR1_SHIFT)
#define GPIO_Z_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR0_SHIFT)
#define GPIO_Z_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G7W_SHIFT)
#define GPIO_Z_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G6W_SHIFT)
#define GPIO_Z_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G5W_SHIFT)
#define GPIO_Z_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G4W_SHIFT)
#define GPIO_Z_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G3W_SHIFT)
#define GPIO_Z_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G2W_SHIFT)
#define GPIO_Z_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G1W_SHIFT)
#define GPIO_Z_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G0W_SHIFT)
#define GPIO_Z_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G7R_SHIFT)
#define GPIO_Z_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G6R_SHIFT)
#define GPIO_Z_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G5R_SHIFT)
#define GPIO_Z_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G4R_SHIFT)
#define GPIO_Z_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G3R_SHIFT)
#define GPIO_Z_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G2R_SHIFT)
#define GPIO_Z_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G1R_SHIFT)
#define GPIO_Z_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G0R_SHIFT)
#define GPIO_Z_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_05_0
#define GPIO_Z_VM_05_0                  MK_ADDR_CONST(0x10a8)
#define GPIO_Z_VM_05_0_SECURE                   0x0
#define GPIO_Z_VM_05_0_DUAL                     0x0
#define GPIO_Z_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_05_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_05_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM1_SHIFT)
#define GPIO_Z_VM_05_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Z_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Z_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM2_SHIFT)
#define GPIO_Z_VM_05_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Z_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Z_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Z_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM3_SHIFT)
#define GPIO_Z_VM_05_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Z_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Z_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Z_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM4_SHIFT)
#define GPIO_Z_VM_05_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Z_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Z_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM5_SHIFT)
#define GPIO_Z_VM_05_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Z_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Z_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Z_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM6_SHIFT)
#define GPIO_Z_VM_05_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Z_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Z_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Z_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM7_SHIFT)
#define GPIO_Z_VM_05_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Z_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Z_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Z_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM8_SHIFT)
#define GPIO_Z_VM_05_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Z_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Z_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_05_0
#define GPIO_Z_SCR_05_0                 MK_ADDR_CONST(0x10ac)
#define GPIO_Z_SCR_05_0_SECURE                  0x0
#define GPIO_Z_SCR_05_0_DUAL                    0x0
#define GPIO_Z_SCR_05_0_SCR                     0
#define GPIO_Z_SCR_05_0_SCRREG                  0
#define GPIO_Z_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Z_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR7_SHIFT)
#define GPIO_Z_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR6_SHIFT)
#define GPIO_Z_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR5_SHIFT)
#define GPIO_Z_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR4_SHIFT)
#define GPIO_Z_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR3_SHIFT)
#define GPIO_Z_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR2_SHIFT)
#define GPIO_Z_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR1_SHIFT)
#define GPIO_Z_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR0_SHIFT)
#define GPIO_Z_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G7W_SHIFT)
#define GPIO_Z_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G6W_SHIFT)
#define GPIO_Z_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G5W_SHIFT)
#define GPIO_Z_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G4W_SHIFT)
#define GPIO_Z_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G3W_SHIFT)
#define GPIO_Z_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G2W_SHIFT)
#define GPIO_Z_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G1W_SHIFT)
#define GPIO_Z_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G0W_SHIFT)
#define GPIO_Z_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G7R_SHIFT)
#define GPIO_Z_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G6R_SHIFT)
#define GPIO_Z_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G5R_SHIFT)
#define GPIO_Z_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G4R_SHIFT)
#define GPIO_Z_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G3R_SHIFT)
#define GPIO_Z_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G2R_SHIFT)
#define GPIO_Z_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G1R_SHIFT)
#define GPIO_Z_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G0R_SHIFT)
#define GPIO_Z_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_06_0
#define GPIO_Z_VM_06_0                  MK_ADDR_CONST(0x10b0)
#define GPIO_Z_VM_06_0_SECURE                   0x0
#define GPIO_Z_VM_06_0_DUAL                     0x0
#define GPIO_Z_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_06_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_06_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM1_SHIFT)
#define GPIO_Z_VM_06_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Z_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Z_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM2_SHIFT)
#define GPIO_Z_VM_06_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Z_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Z_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Z_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM3_SHIFT)
#define GPIO_Z_VM_06_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Z_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Z_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Z_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM4_SHIFT)
#define GPIO_Z_VM_06_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Z_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Z_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM5_SHIFT)
#define GPIO_Z_VM_06_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Z_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Z_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Z_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM6_SHIFT)
#define GPIO_Z_VM_06_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Z_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Z_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Z_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM7_SHIFT)
#define GPIO_Z_VM_06_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Z_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Z_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Z_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM8_SHIFT)
#define GPIO_Z_VM_06_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Z_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Z_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_06_0
#define GPIO_Z_SCR_06_0                 MK_ADDR_CONST(0x10b4)
#define GPIO_Z_SCR_06_0_SECURE                  0x0
#define GPIO_Z_SCR_06_0_DUAL                    0x0
#define GPIO_Z_SCR_06_0_SCR                     0
#define GPIO_Z_SCR_06_0_SCRREG                  0
#define GPIO_Z_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Z_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR7_SHIFT)
#define GPIO_Z_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR6_SHIFT)
#define GPIO_Z_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR5_SHIFT)
#define GPIO_Z_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR4_SHIFT)
#define GPIO_Z_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR3_SHIFT)
#define GPIO_Z_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR2_SHIFT)
#define GPIO_Z_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR1_SHIFT)
#define GPIO_Z_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR0_SHIFT)
#define GPIO_Z_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G7W_SHIFT)
#define GPIO_Z_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G6W_SHIFT)
#define GPIO_Z_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G5W_SHIFT)
#define GPIO_Z_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G4W_SHIFT)
#define GPIO_Z_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G3W_SHIFT)
#define GPIO_Z_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G2W_SHIFT)
#define GPIO_Z_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G1W_SHIFT)
#define GPIO_Z_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G0W_SHIFT)
#define GPIO_Z_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G7R_SHIFT)
#define GPIO_Z_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G6R_SHIFT)
#define GPIO_Z_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G5R_SHIFT)
#define GPIO_Z_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G4R_SHIFT)
#define GPIO_Z_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G3R_SHIFT)
#define GPIO_Z_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G2R_SHIFT)
#define GPIO_Z_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G1R_SHIFT)
#define GPIO_Z_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G0R_SHIFT)
#define GPIO_Z_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Z_VM_07_0
#define GPIO_Z_VM_07_0                  MK_ADDR_CONST(0x10b8)
#define GPIO_Z_VM_07_0_SECURE                   0x0
#define GPIO_Z_VM_07_0_DUAL                     0x0
#define GPIO_Z_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_07_0_SCRREG                   GPIO_CTL1_VM_SCR_0
#define GPIO_Z_VM_07_0_WORD_COUNT                       0x1
#define GPIO_Z_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Z_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM1_SHIFT)
#define GPIO_Z_VM_07_0_VM1_RANGE                        1:0
#define GPIO_Z_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Z_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Z_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM2_SHIFT)
#define GPIO_Z_VM_07_0_VM2_RANGE                        3:2
#define GPIO_Z_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Z_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Z_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Z_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM3_SHIFT)
#define GPIO_Z_VM_07_0_VM3_RANGE                        5:4
#define GPIO_Z_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Z_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Z_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Z_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM4_SHIFT)
#define GPIO_Z_VM_07_0_VM4_RANGE                        7:6
#define GPIO_Z_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Z_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Z_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM5_SHIFT)
#define GPIO_Z_VM_07_0_VM5_RANGE                        9:8
#define GPIO_Z_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Z_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Z_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Z_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM6_SHIFT)
#define GPIO_Z_VM_07_0_VM6_RANGE                        11:10
#define GPIO_Z_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Z_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Z_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Z_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM7_SHIFT)
#define GPIO_Z_VM_07_0_VM7_RANGE                        13:12
#define GPIO_Z_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Z_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Z_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Z_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Z_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM8_SHIFT)
#define GPIO_Z_VM_07_0_VM8_RANGE                        15:14
#define GPIO_Z_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Z_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Z_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_Z_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Z_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_SCR_07_0
#define GPIO_Z_SCR_07_0                 MK_ADDR_CONST(0x10bc)
#define GPIO_Z_SCR_07_0_SECURE                  0x0
#define GPIO_Z_SCR_07_0_DUAL                    0x0
#define GPIO_Z_SCR_07_0_SCR                     0
#define GPIO_Z_SCR_07_0_SCRREG                  0
#define GPIO_Z_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_Z_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Z_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_Z_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_Z_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Z_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Z_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_Z_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_Z_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Z_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Z_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_Z_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_Z_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Z_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Z_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_Z_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Z_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Z_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Z_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Z_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Z_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR7_SHIFT)
#define GPIO_Z_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_Z_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Z_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR6_SHIFT)
#define GPIO_Z_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_Z_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Z_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR5_SHIFT)
#define GPIO_Z_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_Z_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Z_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR4_SHIFT)
#define GPIO_Z_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_Z_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Z_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR3_SHIFT)
#define GPIO_Z_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_Z_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Z_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR2_SHIFT)
#define GPIO_Z_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_Z_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Z_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR1_SHIFT)
#define GPIO_Z_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_Z_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Z_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR0_SHIFT)
#define GPIO_Z_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_Z_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Z_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G7W_SHIFT)
#define GPIO_Z_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_Z_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Z_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G6W_SHIFT)
#define GPIO_Z_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_Z_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Z_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G5W_SHIFT)
#define GPIO_Z_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_Z_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Z_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G4W_SHIFT)
#define GPIO_Z_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_Z_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Z_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G3W_SHIFT)
#define GPIO_Z_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_Z_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Z_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G2W_SHIFT)
#define GPIO_Z_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_Z_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Z_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G1W_SHIFT)
#define GPIO_Z_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_Z_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Z_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G0W_SHIFT)
#define GPIO_Z_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_Z_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Z_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G7R_SHIFT)
#define GPIO_Z_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_Z_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Z_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G6R_SHIFT)
#define GPIO_Z_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_Z_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Z_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G5R_SHIFT)
#define GPIO_Z_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_Z_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G4R_SHIFT)
#define GPIO_Z_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_Z_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Z_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G3R_SHIFT)
#define GPIO_Z_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_Z_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Z_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G2R_SHIFT)
#define GPIO_Z_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_Z_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Z_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G1R_SHIFT)
#define GPIO_Z_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_Z_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Z_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Z_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G0R_SHIFT)
#define GPIO_Z_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_Z_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_Z_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Z_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CTL1_VM_SCR_0
#define GPIO_CTL1_VM_SCR_0                      MK_ADDR_CONST(0x1800)
#define GPIO_CTL1_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL1_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL1_VM_SCR_0_SCR                  0
#define GPIO_CTL1_VM_SCR_0_SCRREG                       0
#define GPIO_CTL1_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL1_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL1_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL1_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL1_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define GPIO_CTL1_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL1_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL1_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL1_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define GPIO_CTL1_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL1_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL1_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL1_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define GPIO_CTL1_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL1_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL1_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL1_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define GPIO_CTL1_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL1_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL1_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL1_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define GPIO_CTL1_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL1_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL1_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL1_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define GPIO_CTL1_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL1_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL1_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL1_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define GPIO_CTL1_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL1_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL1_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL1_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define GPIO_CTL1_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL1_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL1_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL1_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define GPIO_CTL1_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL1_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL1_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL1_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define GPIO_CTL1_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL1_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL1_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL1_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define GPIO_CTL1_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL1_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL1_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL1_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define GPIO_CTL1_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL1_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL1_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL1_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define GPIO_CTL1_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL1_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL1_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL1_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define GPIO_CTL1_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL1_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL1_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL1_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define GPIO_CTL1_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL1_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL1_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL1_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define GPIO_CTL1_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL1_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL1_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL1_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define GPIO_CTL1_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL1_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL1_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL1_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define GPIO_CTL1_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL1_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL1_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL1_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define GPIO_CTL1_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL1_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL1_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL1_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define GPIO_CTL1_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL1_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL1_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL1_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define GPIO_CTL1_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL1_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL1_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL1_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_CTL1_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL1_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL1_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL1_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define GPIO_CTL1_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL1_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL1_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL1_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL1_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CTL1_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL1_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL1_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL1_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL1_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL1_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x1804)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL1_INTERRUPT_STATUS_VM_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x1808)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_CTL1_SCR_0
#define GPIO_CTL1_SCR_0                 MK_ADDR_CONST(0x180c)
#define GPIO_CTL1_SCR_0_SECURE                  0x0
#define GPIO_CTL1_SCR_0_DUAL                    0x0
#define GPIO_CTL1_SCR_0_SCR                     0
#define GPIO_CTL1_SCR_0_SCRREG                  0
#define GPIO_CTL1_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL1_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL1_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_CTL1_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL1_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL1_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL1_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_CTL1_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL1_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL1_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL1_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_CTL1_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL1_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL1_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL1_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL1_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_CTL1_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL1_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL1_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL1_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_CTL1_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_CTL1_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL1_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_CTL1_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_CTL1_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR7_SHIFT)
#define GPIO_CTL1_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL1_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL1_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL1_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_CTL1_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR6_SHIFT)
#define GPIO_CTL1_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL1_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL1_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL1_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_CTL1_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR5_SHIFT)
#define GPIO_CTL1_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL1_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL1_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL1_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_CTL1_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR4_SHIFT)
#define GPIO_CTL1_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL1_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL1_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL1_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_CTL1_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR3_SHIFT)
#define GPIO_CTL1_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL1_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL1_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL1_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_CTL1_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR2_SHIFT)
#define GPIO_CTL1_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL1_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL1_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL1_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_CTL1_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR1_SHIFT)
#define GPIO_CTL1_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL1_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL1_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL1_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_CTL1_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR0_SHIFT)
#define GPIO_CTL1_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL1_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL1_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL1_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_CTL1_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G7W_SHIFT)
#define GPIO_CTL1_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL1_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL1_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL1_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_CTL1_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G6W_SHIFT)
#define GPIO_CTL1_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL1_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL1_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL1_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_CTL1_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G5W_SHIFT)
#define GPIO_CTL1_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL1_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL1_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL1_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_CTL1_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G4W_SHIFT)
#define GPIO_CTL1_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL1_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL1_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL1_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_CTL1_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G3W_SHIFT)
#define GPIO_CTL1_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL1_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL1_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL1_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_CTL1_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G2W_SHIFT)
#define GPIO_CTL1_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL1_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL1_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL1_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_CTL1_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G1W_SHIFT)
#define GPIO_CTL1_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL1_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL1_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL1_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_CTL1_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G0W_SHIFT)
#define GPIO_CTL1_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL1_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL1_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL1_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_CTL1_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G7R_SHIFT)
#define GPIO_CTL1_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL1_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL1_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL1_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_CTL1_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G6R_SHIFT)
#define GPIO_CTL1_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL1_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL1_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL1_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_CTL1_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G5R_SHIFT)
#define GPIO_CTL1_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL1_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL1_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL1_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_CTL1_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G4R_SHIFT)
#define GPIO_CTL1_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL1_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL1_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL1_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_CTL1_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G3R_SHIFT)
#define GPIO_CTL1_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL1_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL1_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL1_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_CTL1_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G2R_SHIFT)
#define GPIO_CTL1_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL1_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL1_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL1_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_CTL1_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G1R_SHIFT)
#define GPIO_CTL1_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL1_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL1_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL1_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL1_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CTL1_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G0R_SHIFT)
#define GPIO_CTL1_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL1_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL1_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL1_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL1_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL1_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CTL1_ICG_EN_OVERRIDE_0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x1810)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_X_INT0_ROUTE_MAPPING_0
#define GPIO_X_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1814)
#define GPIO_X_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_X_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_X_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_X_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_X_INT1_ROUTE_MAPPING_0
#define GPIO_X_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1818)
#define GPIO_X_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_X_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_X_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_X_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_X_INT2_ROUTE_MAPPING_0
#define GPIO_X_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x181c)
#define GPIO_X_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_X_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_X_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_X_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_X_INT3_ROUTE_MAPPING_0
#define GPIO_X_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1820)
#define GPIO_X_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_X_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_X_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_X_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_X_INT4_ROUTE_MAPPING_0
#define GPIO_X_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1824)
#define GPIO_X_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_X_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_X_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_X_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_X_INT5_ROUTE_MAPPING_0
#define GPIO_X_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1828)
#define GPIO_X_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_X_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_X_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_X_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_X_INT6_ROUTE_MAPPING_0
#define GPIO_X_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x182c)
#define GPIO_X_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_X_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_X_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_X_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_X_INT7_ROUTE_MAPPING_0
#define GPIO_X_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1830)
#define GPIO_X_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_X_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_X_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_X_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_X_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_X_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_X_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Y_INT0_ROUTE_MAPPING_0
#define GPIO_Y_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1834)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Y_INT1_ROUTE_MAPPING_0
#define GPIO_Y_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1838)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Y_INT2_ROUTE_MAPPING_0
#define GPIO_Y_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x183c)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Y_INT3_ROUTE_MAPPING_0
#define GPIO_Y_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1840)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Y_INT4_ROUTE_MAPPING_0
#define GPIO_Y_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1844)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Y_INT5_ROUTE_MAPPING_0
#define GPIO_Y_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1848)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Y_INT6_ROUTE_MAPPING_0
#define GPIO_Y_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x184c)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Y_INT7_ROUTE_MAPPING_0
#define GPIO_Y_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1850)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Y_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Z_INT0_ROUTE_MAPPING_0
#define GPIO_Z_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1854)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Z_INT1_ROUTE_MAPPING_0
#define GPIO_Z_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1858)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Z_INT2_ROUTE_MAPPING_0
#define GPIO_Z_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x185c)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Z_INT3_ROUTE_MAPPING_0
#define GPIO_Z_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1860)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Z_INT4_ROUTE_MAPPING_0
#define GPIO_Z_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1864)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Z_INT5_ROUTE_MAPPING_0
#define GPIO_Z_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1868)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Z_INT6_ROUTE_MAPPING_0
#define GPIO_Z_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x186c)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Z_INT7_ROUTE_MAPPING_0
#define GPIO_Z_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1870)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Z_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL1_SPARE_0
#define GPIO_CTL1_SPARE_0                       MK_ADDR_CONST(0x1874)
#define GPIO_CTL1_SPARE_0_SECURE                        0x0
#define GPIO_CTL1_SPARE_0_DUAL                  0x0
#define GPIO_CTL1_SPARE_0_SCR                   0
#define GPIO_CTL1_SPARE_0_SCRREG                        0
#define GPIO_CTL1_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL1_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL1_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL1_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL1_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL1_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL1_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL1_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL1_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL1_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL1_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_M_VM_00_0
#define GPIO_M_VM_00_0                  MK_ADDR_CONST(0x2000)
#define GPIO_M_VM_00_0_SECURE                   0x0
#define GPIO_M_VM_00_0_DUAL                     0x0
#define GPIO_M_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_00_0_WORD_COUNT                       0x1
#define GPIO_M_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM1_SHIFT)
#define GPIO_M_VM_00_0_VM1_RANGE                        1:0
#define GPIO_M_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_M_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_M_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM2_SHIFT)
#define GPIO_M_VM_00_0_VM2_RANGE                        3:2
#define GPIO_M_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_M_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_M_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_M_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM3_SHIFT)
#define GPIO_M_VM_00_0_VM3_RANGE                        5:4
#define GPIO_M_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_M_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_M_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_M_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM4_SHIFT)
#define GPIO_M_VM_00_0_VM4_RANGE                        7:6
#define GPIO_M_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_M_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_M_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM5_SHIFT)
#define GPIO_M_VM_00_0_VM5_RANGE                        9:8
#define GPIO_M_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_M_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_M_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_M_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM6_SHIFT)
#define GPIO_M_VM_00_0_VM6_RANGE                        11:10
#define GPIO_M_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_M_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_M_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_M_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM7_SHIFT)
#define GPIO_M_VM_00_0_VM7_RANGE                        13:12
#define GPIO_M_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_M_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_M_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_M_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM8_SHIFT)
#define GPIO_M_VM_00_0_VM8_RANGE                        15:14
#define GPIO_M_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_M_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_M_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_00_0
#define GPIO_M_SCR_00_0                 MK_ADDR_CONST(0x2004)
#define GPIO_M_SCR_00_0_SECURE                  0x0
#define GPIO_M_SCR_00_0_DUAL                    0x0
#define GPIO_M_SCR_00_0_SCR                     0
#define GPIO_M_SCR_00_0_SCRREG                  0
#define GPIO_M_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_M_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_M_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_M_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_M_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_M_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_M_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_M_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_M_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR7_SHIFT)
#define GPIO_M_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_M_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR6_SHIFT)
#define GPIO_M_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_M_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR5_SHIFT)
#define GPIO_M_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_M_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR4_SHIFT)
#define GPIO_M_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_M_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR3_SHIFT)
#define GPIO_M_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_M_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR2_SHIFT)
#define GPIO_M_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_M_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR1_SHIFT)
#define GPIO_M_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_M_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR0_SHIFT)
#define GPIO_M_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_M_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G7W_SHIFT)
#define GPIO_M_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_M_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G6W_SHIFT)
#define GPIO_M_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_M_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G5W_SHIFT)
#define GPIO_M_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_M_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G4W_SHIFT)
#define GPIO_M_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_M_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G3W_SHIFT)
#define GPIO_M_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_M_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G2W_SHIFT)
#define GPIO_M_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_M_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G1W_SHIFT)
#define GPIO_M_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_M_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G0W_SHIFT)
#define GPIO_M_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_M_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G7R_SHIFT)
#define GPIO_M_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_M_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G6R_SHIFT)
#define GPIO_M_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G5R_SHIFT)
#define GPIO_M_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_M_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G4R_SHIFT)
#define GPIO_M_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_M_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G3R_SHIFT)
#define GPIO_M_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_M_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G2R_SHIFT)
#define GPIO_M_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_M_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G1R_SHIFT)
#define GPIO_M_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G0R_SHIFT)
#define GPIO_M_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_M_VM_01_0
#define GPIO_M_VM_01_0                  MK_ADDR_CONST(0x2008)
#define GPIO_M_VM_01_0_SECURE                   0x0
#define GPIO_M_VM_01_0_DUAL                     0x0
#define GPIO_M_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_01_0_WORD_COUNT                       0x1
#define GPIO_M_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM1_SHIFT)
#define GPIO_M_VM_01_0_VM1_RANGE                        1:0
#define GPIO_M_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_M_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_M_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM2_SHIFT)
#define GPIO_M_VM_01_0_VM2_RANGE                        3:2
#define GPIO_M_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_M_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_M_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_M_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM3_SHIFT)
#define GPIO_M_VM_01_0_VM3_RANGE                        5:4
#define GPIO_M_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_M_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_M_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_M_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM4_SHIFT)
#define GPIO_M_VM_01_0_VM4_RANGE                        7:6
#define GPIO_M_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_M_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_M_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM5_SHIFT)
#define GPIO_M_VM_01_0_VM5_RANGE                        9:8
#define GPIO_M_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_M_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_M_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_M_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM6_SHIFT)
#define GPIO_M_VM_01_0_VM6_RANGE                        11:10
#define GPIO_M_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_M_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_M_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_M_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM7_SHIFT)
#define GPIO_M_VM_01_0_VM7_RANGE                        13:12
#define GPIO_M_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_M_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_M_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_M_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM8_SHIFT)
#define GPIO_M_VM_01_0_VM8_RANGE                        15:14
#define GPIO_M_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_M_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_M_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_01_0
#define GPIO_M_SCR_01_0                 MK_ADDR_CONST(0x200c)
#define GPIO_M_SCR_01_0_SECURE                  0x0
#define GPIO_M_SCR_01_0_DUAL                    0x0
#define GPIO_M_SCR_01_0_SCR                     0
#define GPIO_M_SCR_01_0_SCRREG                  0
#define GPIO_M_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_M_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_M_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_M_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_M_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_M_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_M_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_M_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_M_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR7_SHIFT)
#define GPIO_M_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_M_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR6_SHIFT)
#define GPIO_M_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_M_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR5_SHIFT)
#define GPIO_M_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_M_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR4_SHIFT)
#define GPIO_M_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_M_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR3_SHIFT)
#define GPIO_M_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_M_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR2_SHIFT)
#define GPIO_M_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_M_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR1_SHIFT)
#define GPIO_M_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_M_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR0_SHIFT)
#define GPIO_M_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_M_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G7W_SHIFT)
#define GPIO_M_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_M_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G6W_SHIFT)
#define GPIO_M_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_M_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G5W_SHIFT)
#define GPIO_M_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_M_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G4W_SHIFT)
#define GPIO_M_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_M_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G3W_SHIFT)
#define GPIO_M_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_M_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G2W_SHIFT)
#define GPIO_M_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_M_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G1W_SHIFT)
#define GPIO_M_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_M_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G0W_SHIFT)
#define GPIO_M_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_M_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G7R_SHIFT)
#define GPIO_M_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_M_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G6R_SHIFT)
#define GPIO_M_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G5R_SHIFT)
#define GPIO_M_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_M_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G4R_SHIFT)
#define GPIO_M_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_M_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G3R_SHIFT)
#define GPIO_M_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_M_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G2R_SHIFT)
#define GPIO_M_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_M_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G1R_SHIFT)
#define GPIO_M_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G0R_SHIFT)
#define GPIO_M_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_M_VM_02_0
#define GPIO_M_VM_02_0                  MK_ADDR_CONST(0x2010)
#define GPIO_M_VM_02_0_SECURE                   0x0
#define GPIO_M_VM_02_0_DUAL                     0x0
#define GPIO_M_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_02_0_WORD_COUNT                       0x1
#define GPIO_M_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM1_SHIFT)
#define GPIO_M_VM_02_0_VM1_RANGE                        1:0
#define GPIO_M_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_M_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_M_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM2_SHIFT)
#define GPIO_M_VM_02_0_VM2_RANGE                        3:2
#define GPIO_M_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_M_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_M_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_M_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM3_SHIFT)
#define GPIO_M_VM_02_0_VM3_RANGE                        5:4
#define GPIO_M_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_M_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_M_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_M_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM4_SHIFT)
#define GPIO_M_VM_02_0_VM4_RANGE                        7:6
#define GPIO_M_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_M_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_M_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM5_SHIFT)
#define GPIO_M_VM_02_0_VM5_RANGE                        9:8
#define GPIO_M_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_M_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_M_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_M_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM6_SHIFT)
#define GPIO_M_VM_02_0_VM6_RANGE                        11:10
#define GPIO_M_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_M_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_M_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_M_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM7_SHIFT)
#define GPIO_M_VM_02_0_VM7_RANGE                        13:12
#define GPIO_M_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_M_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_M_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_M_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM8_SHIFT)
#define GPIO_M_VM_02_0_VM8_RANGE                        15:14
#define GPIO_M_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_M_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_M_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_02_0
#define GPIO_M_SCR_02_0                 MK_ADDR_CONST(0x2014)
#define GPIO_M_SCR_02_0_SECURE                  0x0
#define GPIO_M_SCR_02_0_DUAL                    0x0
#define GPIO_M_SCR_02_0_SCR                     0
#define GPIO_M_SCR_02_0_SCRREG                  0
#define GPIO_M_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_M_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_M_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_M_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_M_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_M_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_M_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_M_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_M_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR7_SHIFT)
#define GPIO_M_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_M_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR6_SHIFT)
#define GPIO_M_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_M_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR5_SHIFT)
#define GPIO_M_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_M_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR4_SHIFT)
#define GPIO_M_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_M_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR3_SHIFT)
#define GPIO_M_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_M_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR2_SHIFT)
#define GPIO_M_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_M_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR1_SHIFT)
#define GPIO_M_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_M_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR0_SHIFT)
#define GPIO_M_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_M_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G7W_SHIFT)
#define GPIO_M_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_M_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G6W_SHIFT)
#define GPIO_M_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_M_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G5W_SHIFT)
#define GPIO_M_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_M_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G4W_SHIFT)
#define GPIO_M_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_M_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G3W_SHIFT)
#define GPIO_M_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_M_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G2W_SHIFT)
#define GPIO_M_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_M_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G1W_SHIFT)
#define GPIO_M_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_M_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G0W_SHIFT)
#define GPIO_M_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_M_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G7R_SHIFT)
#define GPIO_M_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_M_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G6R_SHIFT)
#define GPIO_M_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G5R_SHIFT)
#define GPIO_M_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_M_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G4R_SHIFT)
#define GPIO_M_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_M_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G3R_SHIFT)
#define GPIO_M_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_M_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G2R_SHIFT)
#define GPIO_M_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_M_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G1R_SHIFT)
#define GPIO_M_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G0R_SHIFT)
#define GPIO_M_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_M_VM_03_0
#define GPIO_M_VM_03_0                  MK_ADDR_CONST(0x2018)
#define GPIO_M_VM_03_0_SECURE                   0x0
#define GPIO_M_VM_03_0_DUAL                     0x0
#define GPIO_M_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_03_0_WORD_COUNT                       0x1
#define GPIO_M_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM1_SHIFT)
#define GPIO_M_VM_03_0_VM1_RANGE                        1:0
#define GPIO_M_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_M_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_M_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM2_SHIFT)
#define GPIO_M_VM_03_0_VM2_RANGE                        3:2
#define GPIO_M_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_M_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_M_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_M_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM3_SHIFT)
#define GPIO_M_VM_03_0_VM3_RANGE                        5:4
#define GPIO_M_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_M_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_M_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_M_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM4_SHIFT)
#define GPIO_M_VM_03_0_VM4_RANGE                        7:6
#define GPIO_M_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_M_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_M_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM5_SHIFT)
#define GPIO_M_VM_03_0_VM5_RANGE                        9:8
#define GPIO_M_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_M_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_M_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_M_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM6_SHIFT)
#define GPIO_M_VM_03_0_VM6_RANGE                        11:10
#define GPIO_M_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_M_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_M_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_M_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM7_SHIFT)
#define GPIO_M_VM_03_0_VM7_RANGE                        13:12
#define GPIO_M_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_M_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_M_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_M_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM8_SHIFT)
#define GPIO_M_VM_03_0_VM8_RANGE                        15:14
#define GPIO_M_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_M_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_M_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_03_0
#define GPIO_M_SCR_03_0                 MK_ADDR_CONST(0x201c)
#define GPIO_M_SCR_03_0_SECURE                  0x0
#define GPIO_M_SCR_03_0_DUAL                    0x0
#define GPIO_M_SCR_03_0_SCR                     0
#define GPIO_M_SCR_03_0_SCRREG                  0
#define GPIO_M_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_M_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_M_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_M_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_M_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_M_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_M_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_M_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_M_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR7_SHIFT)
#define GPIO_M_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_M_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR6_SHIFT)
#define GPIO_M_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_M_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR5_SHIFT)
#define GPIO_M_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_M_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR4_SHIFT)
#define GPIO_M_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_M_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR3_SHIFT)
#define GPIO_M_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_M_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR2_SHIFT)
#define GPIO_M_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_M_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR1_SHIFT)
#define GPIO_M_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_M_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR0_SHIFT)
#define GPIO_M_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_M_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G7W_SHIFT)
#define GPIO_M_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_M_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G6W_SHIFT)
#define GPIO_M_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_M_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G5W_SHIFT)
#define GPIO_M_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_M_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G4W_SHIFT)
#define GPIO_M_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_M_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G3W_SHIFT)
#define GPIO_M_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_M_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G2W_SHIFT)
#define GPIO_M_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_M_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G1W_SHIFT)
#define GPIO_M_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_M_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G0W_SHIFT)
#define GPIO_M_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_M_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G7R_SHIFT)
#define GPIO_M_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_M_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G6R_SHIFT)
#define GPIO_M_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G5R_SHIFT)
#define GPIO_M_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_M_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G4R_SHIFT)
#define GPIO_M_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_M_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G3R_SHIFT)
#define GPIO_M_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_M_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G2R_SHIFT)
#define GPIO_M_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_M_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G1R_SHIFT)
#define GPIO_M_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G0R_SHIFT)
#define GPIO_M_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_M_VM_04_0
#define GPIO_M_VM_04_0                  MK_ADDR_CONST(0x2020)
#define GPIO_M_VM_04_0_SECURE                   0x0
#define GPIO_M_VM_04_0_DUAL                     0x0
#define GPIO_M_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_04_0_WORD_COUNT                       0x1
#define GPIO_M_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM1_SHIFT)
#define GPIO_M_VM_04_0_VM1_RANGE                        1:0
#define GPIO_M_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_M_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_M_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM2_SHIFT)
#define GPIO_M_VM_04_0_VM2_RANGE                        3:2
#define GPIO_M_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_M_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_M_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_M_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM3_SHIFT)
#define GPIO_M_VM_04_0_VM3_RANGE                        5:4
#define GPIO_M_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_M_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_M_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_M_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM4_SHIFT)
#define GPIO_M_VM_04_0_VM4_RANGE                        7:6
#define GPIO_M_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_M_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_M_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM5_SHIFT)
#define GPIO_M_VM_04_0_VM5_RANGE                        9:8
#define GPIO_M_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_M_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_M_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_M_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM6_SHIFT)
#define GPIO_M_VM_04_0_VM6_RANGE                        11:10
#define GPIO_M_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_M_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_M_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_M_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM7_SHIFT)
#define GPIO_M_VM_04_0_VM7_RANGE                        13:12
#define GPIO_M_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_M_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_M_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_M_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM8_SHIFT)
#define GPIO_M_VM_04_0_VM8_RANGE                        15:14
#define GPIO_M_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_M_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_M_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_04_0
#define GPIO_M_SCR_04_0                 MK_ADDR_CONST(0x2024)
#define GPIO_M_SCR_04_0_SECURE                  0x0
#define GPIO_M_SCR_04_0_DUAL                    0x0
#define GPIO_M_SCR_04_0_SCR                     0
#define GPIO_M_SCR_04_0_SCRREG                  0
#define GPIO_M_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_M_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_M_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_M_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_M_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_M_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_M_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_M_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_M_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR7_SHIFT)
#define GPIO_M_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_M_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR6_SHIFT)
#define GPIO_M_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_M_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR5_SHIFT)
#define GPIO_M_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_M_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR4_SHIFT)
#define GPIO_M_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_M_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR3_SHIFT)
#define GPIO_M_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_M_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR2_SHIFT)
#define GPIO_M_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_M_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR1_SHIFT)
#define GPIO_M_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_M_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR0_SHIFT)
#define GPIO_M_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_M_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G7W_SHIFT)
#define GPIO_M_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_M_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G6W_SHIFT)
#define GPIO_M_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_M_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G5W_SHIFT)
#define GPIO_M_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_M_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G4W_SHIFT)
#define GPIO_M_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_M_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G3W_SHIFT)
#define GPIO_M_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_M_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G2W_SHIFT)
#define GPIO_M_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_M_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G1W_SHIFT)
#define GPIO_M_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_M_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G0W_SHIFT)
#define GPIO_M_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_M_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G7R_SHIFT)
#define GPIO_M_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_M_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G6R_SHIFT)
#define GPIO_M_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G5R_SHIFT)
#define GPIO_M_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_M_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G4R_SHIFT)
#define GPIO_M_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_M_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G3R_SHIFT)
#define GPIO_M_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_M_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G2R_SHIFT)
#define GPIO_M_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_M_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G1R_SHIFT)
#define GPIO_M_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G0R_SHIFT)
#define GPIO_M_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_M_VM_05_0
#define GPIO_M_VM_05_0                  MK_ADDR_CONST(0x2028)
#define GPIO_M_VM_05_0_SECURE                   0x0
#define GPIO_M_VM_05_0_DUAL                     0x0
#define GPIO_M_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_05_0_WORD_COUNT                       0x1
#define GPIO_M_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM1_SHIFT)
#define GPIO_M_VM_05_0_VM1_RANGE                        1:0
#define GPIO_M_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_M_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_M_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM2_SHIFT)
#define GPIO_M_VM_05_0_VM2_RANGE                        3:2
#define GPIO_M_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_M_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_M_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_M_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM3_SHIFT)
#define GPIO_M_VM_05_0_VM3_RANGE                        5:4
#define GPIO_M_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_M_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_M_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_M_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM4_SHIFT)
#define GPIO_M_VM_05_0_VM4_RANGE                        7:6
#define GPIO_M_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_M_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_M_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM5_SHIFT)
#define GPIO_M_VM_05_0_VM5_RANGE                        9:8
#define GPIO_M_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_M_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_M_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_M_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM6_SHIFT)
#define GPIO_M_VM_05_0_VM6_RANGE                        11:10
#define GPIO_M_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_M_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_M_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_M_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM7_SHIFT)
#define GPIO_M_VM_05_0_VM7_RANGE                        13:12
#define GPIO_M_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_M_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_M_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_M_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM8_SHIFT)
#define GPIO_M_VM_05_0_VM8_RANGE                        15:14
#define GPIO_M_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_M_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_M_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_05_0
#define GPIO_M_SCR_05_0                 MK_ADDR_CONST(0x202c)
#define GPIO_M_SCR_05_0_SECURE                  0x0
#define GPIO_M_SCR_05_0_DUAL                    0x0
#define GPIO_M_SCR_05_0_SCR                     0
#define GPIO_M_SCR_05_0_SCRREG                  0
#define GPIO_M_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_M_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_M_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_M_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_M_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_M_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_M_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_M_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_M_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR7_SHIFT)
#define GPIO_M_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_M_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR6_SHIFT)
#define GPIO_M_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_M_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR5_SHIFT)
#define GPIO_M_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_M_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR4_SHIFT)
#define GPIO_M_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_M_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR3_SHIFT)
#define GPIO_M_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_M_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR2_SHIFT)
#define GPIO_M_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_M_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR1_SHIFT)
#define GPIO_M_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_M_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR0_SHIFT)
#define GPIO_M_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_M_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G7W_SHIFT)
#define GPIO_M_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_M_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G6W_SHIFT)
#define GPIO_M_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_M_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G5W_SHIFT)
#define GPIO_M_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_M_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G4W_SHIFT)
#define GPIO_M_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_M_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G3W_SHIFT)
#define GPIO_M_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_M_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G2W_SHIFT)
#define GPIO_M_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_M_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G1W_SHIFT)
#define GPIO_M_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_M_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G0W_SHIFT)
#define GPIO_M_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_M_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G7R_SHIFT)
#define GPIO_M_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_M_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G6R_SHIFT)
#define GPIO_M_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G5R_SHIFT)
#define GPIO_M_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_M_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G4R_SHIFT)
#define GPIO_M_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_M_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G3R_SHIFT)
#define GPIO_M_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_M_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G2R_SHIFT)
#define GPIO_M_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_M_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G1R_SHIFT)
#define GPIO_M_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G0R_SHIFT)
#define GPIO_M_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_M_VM_06_0
#define GPIO_M_VM_06_0                  MK_ADDR_CONST(0x2030)
#define GPIO_M_VM_06_0_SECURE                   0x0
#define GPIO_M_VM_06_0_DUAL                     0x0
#define GPIO_M_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_06_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_06_0_WORD_COUNT                       0x1
#define GPIO_M_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM1_SHIFT)
#define GPIO_M_VM_06_0_VM1_RANGE                        1:0
#define GPIO_M_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_M_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_M_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM2_SHIFT)
#define GPIO_M_VM_06_0_VM2_RANGE                        3:2
#define GPIO_M_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_M_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_M_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_M_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM3_SHIFT)
#define GPIO_M_VM_06_0_VM3_RANGE                        5:4
#define GPIO_M_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_M_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_M_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_M_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM4_SHIFT)
#define GPIO_M_VM_06_0_VM4_RANGE                        7:6
#define GPIO_M_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_M_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_M_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM5_SHIFT)
#define GPIO_M_VM_06_0_VM5_RANGE                        9:8
#define GPIO_M_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_M_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_M_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_M_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM6_SHIFT)
#define GPIO_M_VM_06_0_VM6_RANGE                        11:10
#define GPIO_M_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_M_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_M_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_M_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM7_SHIFT)
#define GPIO_M_VM_06_0_VM7_RANGE                        13:12
#define GPIO_M_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_M_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_M_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_M_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM8_SHIFT)
#define GPIO_M_VM_06_0_VM8_RANGE                        15:14
#define GPIO_M_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_M_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_M_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_06_0
#define GPIO_M_SCR_06_0                 MK_ADDR_CONST(0x2034)
#define GPIO_M_SCR_06_0_SECURE                  0x0
#define GPIO_M_SCR_06_0_DUAL                    0x0
#define GPIO_M_SCR_06_0_SCR                     0
#define GPIO_M_SCR_06_0_SCRREG                  0
#define GPIO_M_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_M_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_M_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_M_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_M_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_M_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_M_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_M_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_M_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR7_SHIFT)
#define GPIO_M_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_M_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR6_SHIFT)
#define GPIO_M_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_M_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR5_SHIFT)
#define GPIO_M_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_M_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR4_SHIFT)
#define GPIO_M_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_M_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR3_SHIFT)
#define GPIO_M_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_M_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR2_SHIFT)
#define GPIO_M_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_M_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR1_SHIFT)
#define GPIO_M_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_M_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR0_SHIFT)
#define GPIO_M_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_M_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G7W_SHIFT)
#define GPIO_M_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_M_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G6W_SHIFT)
#define GPIO_M_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_M_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G5W_SHIFT)
#define GPIO_M_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_M_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G4W_SHIFT)
#define GPIO_M_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_M_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G3W_SHIFT)
#define GPIO_M_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_M_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G2W_SHIFT)
#define GPIO_M_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_M_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G1W_SHIFT)
#define GPIO_M_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_M_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G0W_SHIFT)
#define GPIO_M_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_M_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G7R_SHIFT)
#define GPIO_M_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_M_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G6R_SHIFT)
#define GPIO_M_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G5R_SHIFT)
#define GPIO_M_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_M_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G4R_SHIFT)
#define GPIO_M_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_M_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G3R_SHIFT)
#define GPIO_M_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_M_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G2R_SHIFT)
#define GPIO_M_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_M_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G1R_SHIFT)
#define GPIO_M_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G0R_SHIFT)
#define GPIO_M_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_M_VM_07_0
#define GPIO_M_VM_07_0                  MK_ADDR_CONST(0x2038)
#define GPIO_M_VM_07_0_SECURE                   0x0
#define GPIO_M_VM_07_0_DUAL                     0x0
#define GPIO_M_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_07_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_M_VM_07_0_WORD_COUNT                       0x1
#define GPIO_M_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_M_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_M_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM1_SHIFT)
#define GPIO_M_VM_07_0_VM1_RANGE                        1:0
#define GPIO_M_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_M_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_M_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM2_SHIFT)
#define GPIO_M_VM_07_0_VM2_RANGE                        3:2
#define GPIO_M_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_M_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_M_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_M_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM3_SHIFT)
#define GPIO_M_VM_07_0_VM3_RANGE                        5:4
#define GPIO_M_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_M_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_M_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_M_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM4_SHIFT)
#define GPIO_M_VM_07_0_VM4_RANGE                        7:6
#define GPIO_M_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_M_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_M_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM5_SHIFT)
#define GPIO_M_VM_07_0_VM5_RANGE                        9:8
#define GPIO_M_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_M_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_M_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_M_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM6_SHIFT)
#define GPIO_M_VM_07_0_VM6_RANGE                        11:10
#define GPIO_M_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_M_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_M_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_M_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM7_SHIFT)
#define GPIO_M_VM_07_0_VM7_RANGE                        13:12
#define GPIO_M_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_M_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_M_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_M_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_M_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM8_SHIFT)
#define GPIO_M_VM_07_0_VM8_RANGE                        15:14
#define GPIO_M_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_M_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_M_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_M_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_M_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_SCR_07_0
#define GPIO_M_SCR_07_0                 MK_ADDR_CONST(0x203c)
#define GPIO_M_SCR_07_0_SECURE                  0x0
#define GPIO_M_SCR_07_0_DUAL                    0x0
#define GPIO_M_SCR_07_0_SCR                     0
#define GPIO_M_SCR_07_0_SCRREG                  0
#define GPIO_M_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_M_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_M_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_M_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_M_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_M_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_M_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_M_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_M_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_M_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_M_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_M_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_M_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_M_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_M_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_M_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_M_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_M_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_M_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_M_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_M_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_M_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_M_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_M_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_M_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_M_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR7_SHIFT)
#define GPIO_M_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_M_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_M_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_M_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR6_SHIFT)
#define GPIO_M_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_M_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_M_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_M_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR5_SHIFT)
#define GPIO_M_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_M_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_M_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_M_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR4_SHIFT)
#define GPIO_M_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_M_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_M_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_M_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR3_SHIFT)
#define GPIO_M_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_M_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_M_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_M_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR2_SHIFT)
#define GPIO_M_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_M_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_M_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_M_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR1_SHIFT)
#define GPIO_M_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_M_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_M_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_M_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR0_SHIFT)
#define GPIO_M_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_M_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_M_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_M_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G7W_SHIFT)
#define GPIO_M_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_M_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_M_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_M_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G6W_SHIFT)
#define GPIO_M_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_M_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_M_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_M_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G5W_SHIFT)
#define GPIO_M_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_M_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_M_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_M_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G4W_SHIFT)
#define GPIO_M_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_M_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_M_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_M_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G3W_SHIFT)
#define GPIO_M_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_M_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_M_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_M_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G2W_SHIFT)
#define GPIO_M_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_M_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_M_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_M_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G1W_SHIFT)
#define GPIO_M_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_M_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_M_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_M_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G0W_SHIFT)
#define GPIO_M_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_M_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_M_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_M_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G7R_SHIFT)
#define GPIO_M_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_M_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_M_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_M_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G6R_SHIFT)
#define GPIO_M_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_M_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_M_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G5R_SHIFT)
#define GPIO_M_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_M_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_M_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G4R_SHIFT)
#define GPIO_M_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_M_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_M_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_M_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G3R_SHIFT)
#define GPIO_M_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_M_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_M_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_M_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G2R_SHIFT)
#define GPIO_M_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_M_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_M_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_M_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G1R_SHIFT)
#define GPIO_M_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_M_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_M_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_M_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G0R_SHIFT)
#define GPIO_M_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_M_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_M_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_M_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_N_VM_00_0
#define GPIO_N_VM_00_0                  MK_ADDR_CONST(0x2040)
#define GPIO_N_VM_00_0_SECURE                   0x0
#define GPIO_N_VM_00_0_DUAL                     0x0
#define GPIO_N_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_00_0_WORD_COUNT                       0x1
#define GPIO_N_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM1_SHIFT)
#define GPIO_N_VM_00_0_VM1_RANGE                        1:0
#define GPIO_N_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_N_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_N_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM2_SHIFT)
#define GPIO_N_VM_00_0_VM2_RANGE                        3:2
#define GPIO_N_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_N_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_N_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_N_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM3_SHIFT)
#define GPIO_N_VM_00_0_VM3_RANGE                        5:4
#define GPIO_N_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_N_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_N_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_N_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM4_SHIFT)
#define GPIO_N_VM_00_0_VM4_RANGE                        7:6
#define GPIO_N_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_N_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_N_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM5_SHIFT)
#define GPIO_N_VM_00_0_VM5_RANGE                        9:8
#define GPIO_N_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_N_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_N_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_N_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM6_SHIFT)
#define GPIO_N_VM_00_0_VM6_RANGE                        11:10
#define GPIO_N_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_N_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_N_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_N_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM7_SHIFT)
#define GPIO_N_VM_00_0_VM7_RANGE                        13:12
#define GPIO_N_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_N_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_N_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_N_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM8_SHIFT)
#define GPIO_N_VM_00_0_VM8_RANGE                        15:14
#define GPIO_N_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_N_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_N_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_00_0
#define GPIO_N_SCR_00_0                 MK_ADDR_CONST(0x2044)
#define GPIO_N_SCR_00_0_SECURE                  0x0
#define GPIO_N_SCR_00_0_DUAL                    0x0
#define GPIO_N_SCR_00_0_SCR                     0
#define GPIO_N_SCR_00_0_SCRREG                  0
#define GPIO_N_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_N_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_N_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_N_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_N_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_N_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_N_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_N_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_N_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR7_SHIFT)
#define GPIO_N_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_N_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR6_SHIFT)
#define GPIO_N_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_N_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR5_SHIFT)
#define GPIO_N_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_N_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR4_SHIFT)
#define GPIO_N_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_N_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR3_SHIFT)
#define GPIO_N_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_N_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR2_SHIFT)
#define GPIO_N_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_N_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR1_SHIFT)
#define GPIO_N_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_N_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR0_SHIFT)
#define GPIO_N_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_N_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G7W_SHIFT)
#define GPIO_N_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_N_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G6W_SHIFT)
#define GPIO_N_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_N_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G5W_SHIFT)
#define GPIO_N_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_N_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G4W_SHIFT)
#define GPIO_N_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_N_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G3W_SHIFT)
#define GPIO_N_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_N_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G2W_SHIFT)
#define GPIO_N_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_N_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G1W_SHIFT)
#define GPIO_N_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_N_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G0W_SHIFT)
#define GPIO_N_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_N_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G7R_SHIFT)
#define GPIO_N_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_N_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G6R_SHIFT)
#define GPIO_N_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G5R_SHIFT)
#define GPIO_N_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_N_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G4R_SHIFT)
#define GPIO_N_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_N_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G3R_SHIFT)
#define GPIO_N_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_N_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G2R_SHIFT)
#define GPIO_N_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_N_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G1R_SHIFT)
#define GPIO_N_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G0R_SHIFT)
#define GPIO_N_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_N_VM_01_0
#define GPIO_N_VM_01_0                  MK_ADDR_CONST(0x2048)
#define GPIO_N_VM_01_0_SECURE                   0x0
#define GPIO_N_VM_01_0_DUAL                     0x0
#define GPIO_N_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_01_0_WORD_COUNT                       0x1
#define GPIO_N_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM1_SHIFT)
#define GPIO_N_VM_01_0_VM1_RANGE                        1:0
#define GPIO_N_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_N_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_N_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM2_SHIFT)
#define GPIO_N_VM_01_0_VM2_RANGE                        3:2
#define GPIO_N_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_N_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_N_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_N_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM3_SHIFT)
#define GPIO_N_VM_01_0_VM3_RANGE                        5:4
#define GPIO_N_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_N_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_N_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_N_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM4_SHIFT)
#define GPIO_N_VM_01_0_VM4_RANGE                        7:6
#define GPIO_N_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_N_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_N_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM5_SHIFT)
#define GPIO_N_VM_01_0_VM5_RANGE                        9:8
#define GPIO_N_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_N_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_N_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_N_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM6_SHIFT)
#define GPIO_N_VM_01_0_VM6_RANGE                        11:10
#define GPIO_N_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_N_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_N_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_N_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM7_SHIFT)
#define GPIO_N_VM_01_0_VM7_RANGE                        13:12
#define GPIO_N_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_N_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_N_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_N_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM8_SHIFT)
#define GPIO_N_VM_01_0_VM8_RANGE                        15:14
#define GPIO_N_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_N_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_N_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_01_0
#define GPIO_N_SCR_01_0                 MK_ADDR_CONST(0x204c)
#define GPIO_N_SCR_01_0_SECURE                  0x0
#define GPIO_N_SCR_01_0_DUAL                    0x0
#define GPIO_N_SCR_01_0_SCR                     0
#define GPIO_N_SCR_01_0_SCRREG                  0
#define GPIO_N_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_N_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_N_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_N_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_N_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_N_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_N_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_N_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_N_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR7_SHIFT)
#define GPIO_N_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_N_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR6_SHIFT)
#define GPIO_N_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_N_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR5_SHIFT)
#define GPIO_N_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_N_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR4_SHIFT)
#define GPIO_N_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_N_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR3_SHIFT)
#define GPIO_N_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_N_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR2_SHIFT)
#define GPIO_N_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_N_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR1_SHIFT)
#define GPIO_N_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_N_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR0_SHIFT)
#define GPIO_N_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_N_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G7W_SHIFT)
#define GPIO_N_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_N_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G6W_SHIFT)
#define GPIO_N_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_N_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G5W_SHIFT)
#define GPIO_N_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_N_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G4W_SHIFT)
#define GPIO_N_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_N_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G3W_SHIFT)
#define GPIO_N_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_N_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G2W_SHIFT)
#define GPIO_N_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_N_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G1W_SHIFT)
#define GPIO_N_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_N_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G0W_SHIFT)
#define GPIO_N_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_N_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G7R_SHIFT)
#define GPIO_N_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_N_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G6R_SHIFT)
#define GPIO_N_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G5R_SHIFT)
#define GPIO_N_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_N_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G4R_SHIFT)
#define GPIO_N_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_N_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G3R_SHIFT)
#define GPIO_N_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_N_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G2R_SHIFT)
#define GPIO_N_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_N_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G1R_SHIFT)
#define GPIO_N_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G0R_SHIFT)
#define GPIO_N_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_N_VM_02_0
#define GPIO_N_VM_02_0                  MK_ADDR_CONST(0x2050)
#define GPIO_N_VM_02_0_SECURE                   0x0
#define GPIO_N_VM_02_0_DUAL                     0x0
#define GPIO_N_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_02_0_WORD_COUNT                       0x1
#define GPIO_N_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM1_SHIFT)
#define GPIO_N_VM_02_0_VM1_RANGE                        1:0
#define GPIO_N_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_N_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_N_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM2_SHIFT)
#define GPIO_N_VM_02_0_VM2_RANGE                        3:2
#define GPIO_N_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_N_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_N_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_N_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM3_SHIFT)
#define GPIO_N_VM_02_0_VM3_RANGE                        5:4
#define GPIO_N_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_N_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_N_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_N_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM4_SHIFT)
#define GPIO_N_VM_02_0_VM4_RANGE                        7:6
#define GPIO_N_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_N_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_N_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM5_SHIFT)
#define GPIO_N_VM_02_0_VM5_RANGE                        9:8
#define GPIO_N_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_N_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_N_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_N_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM6_SHIFT)
#define GPIO_N_VM_02_0_VM6_RANGE                        11:10
#define GPIO_N_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_N_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_N_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_N_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM7_SHIFT)
#define GPIO_N_VM_02_0_VM7_RANGE                        13:12
#define GPIO_N_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_N_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_N_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_N_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM8_SHIFT)
#define GPIO_N_VM_02_0_VM8_RANGE                        15:14
#define GPIO_N_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_N_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_N_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_02_0
#define GPIO_N_SCR_02_0                 MK_ADDR_CONST(0x2054)
#define GPIO_N_SCR_02_0_SECURE                  0x0
#define GPIO_N_SCR_02_0_DUAL                    0x0
#define GPIO_N_SCR_02_0_SCR                     0
#define GPIO_N_SCR_02_0_SCRREG                  0
#define GPIO_N_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_N_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_N_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_N_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_N_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_N_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_N_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_N_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_N_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR7_SHIFT)
#define GPIO_N_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_N_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR6_SHIFT)
#define GPIO_N_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_N_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR5_SHIFT)
#define GPIO_N_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_N_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR4_SHIFT)
#define GPIO_N_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_N_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR3_SHIFT)
#define GPIO_N_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_N_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR2_SHIFT)
#define GPIO_N_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_N_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR1_SHIFT)
#define GPIO_N_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_N_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR0_SHIFT)
#define GPIO_N_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_N_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G7W_SHIFT)
#define GPIO_N_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_N_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G6W_SHIFT)
#define GPIO_N_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_N_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G5W_SHIFT)
#define GPIO_N_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_N_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G4W_SHIFT)
#define GPIO_N_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_N_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G3W_SHIFT)
#define GPIO_N_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_N_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G2W_SHIFT)
#define GPIO_N_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_N_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G1W_SHIFT)
#define GPIO_N_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_N_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G0W_SHIFT)
#define GPIO_N_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_N_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G7R_SHIFT)
#define GPIO_N_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_N_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G6R_SHIFT)
#define GPIO_N_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G5R_SHIFT)
#define GPIO_N_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_N_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G4R_SHIFT)
#define GPIO_N_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_N_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G3R_SHIFT)
#define GPIO_N_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_N_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G2R_SHIFT)
#define GPIO_N_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_N_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G1R_SHIFT)
#define GPIO_N_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G0R_SHIFT)
#define GPIO_N_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_N_VM_03_0
#define GPIO_N_VM_03_0                  MK_ADDR_CONST(0x2058)
#define GPIO_N_VM_03_0_SECURE                   0x0
#define GPIO_N_VM_03_0_DUAL                     0x0
#define GPIO_N_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_03_0_WORD_COUNT                       0x1
#define GPIO_N_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM1_SHIFT)
#define GPIO_N_VM_03_0_VM1_RANGE                        1:0
#define GPIO_N_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_N_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_N_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM2_SHIFT)
#define GPIO_N_VM_03_0_VM2_RANGE                        3:2
#define GPIO_N_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_N_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_N_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_N_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM3_SHIFT)
#define GPIO_N_VM_03_0_VM3_RANGE                        5:4
#define GPIO_N_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_N_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_N_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_N_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM4_SHIFT)
#define GPIO_N_VM_03_0_VM4_RANGE                        7:6
#define GPIO_N_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_N_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_N_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM5_SHIFT)
#define GPIO_N_VM_03_0_VM5_RANGE                        9:8
#define GPIO_N_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_N_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_N_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_N_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM6_SHIFT)
#define GPIO_N_VM_03_0_VM6_RANGE                        11:10
#define GPIO_N_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_N_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_N_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_N_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM7_SHIFT)
#define GPIO_N_VM_03_0_VM7_RANGE                        13:12
#define GPIO_N_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_N_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_N_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_N_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM8_SHIFT)
#define GPIO_N_VM_03_0_VM8_RANGE                        15:14
#define GPIO_N_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_N_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_N_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_03_0
#define GPIO_N_SCR_03_0                 MK_ADDR_CONST(0x205c)
#define GPIO_N_SCR_03_0_SECURE                  0x0
#define GPIO_N_SCR_03_0_DUAL                    0x0
#define GPIO_N_SCR_03_0_SCR                     0
#define GPIO_N_SCR_03_0_SCRREG                  0
#define GPIO_N_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_N_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_N_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_N_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_N_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_N_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_N_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_N_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_N_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR7_SHIFT)
#define GPIO_N_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_N_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR6_SHIFT)
#define GPIO_N_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_N_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR5_SHIFT)
#define GPIO_N_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_N_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR4_SHIFT)
#define GPIO_N_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_N_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR3_SHIFT)
#define GPIO_N_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_N_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR2_SHIFT)
#define GPIO_N_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_N_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR1_SHIFT)
#define GPIO_N_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_N_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR0_SHIFT)
#define GPIO_N_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_N_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G7W_SHIFT)
#define GPIO_N_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_N_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G6W_SHIFT)
#define GPIO_N_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_N_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G5W_SHIFT)
#define GPIO_N_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_N_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G4W_SHIFT)
#define GPIO_N_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_N_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G3W_SHIFT)
#define GPIO_N_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_N_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G2W_SHIFT)
#define GPIO_N_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_N_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G1W_SHIFT)
#define GPIO_N_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_N_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G0W_SHIFT)
#define GPIO_N_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_N_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G7R_SHIFT)
#define GPIO_N_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_N_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G6R_SHIFT)
#define GPIO_N_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G5R_SHIFT)
#define GPIO_N_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_N_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G4R_SHIFT)
#define GPIO_N_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_N_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G3R_SHIFT)
#define GPIO_N_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_N_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G2R_SHIFT)
#define GPIO_N_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_N_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G1R_SHIFT)
#define GPIO_N_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G0R_SHIFT)
#define GPIO_N_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_N_VM_04_0
#define GPIO_N_VM_04_0                  MK_ADDR_CONST(0x2060)
#define GPIO_N_VM_04_0_SECURE                   0x0
#define GPIO_N_VM_04_0_DUAL                     0x0
#define GPIO_N_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_04_0_WORD_COUNT                       0x1
#define GPIO_N_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM1_SHIFT)
#define GPIO_N_VM_04_0_VM1_RANGE                        1:0
#define GPIO_N_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_N_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_N_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM2_SHIFT)
#define GPIO_N_VM_04_0_VM2_RANGE                        3:2
#define GPIO_N_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_N_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_N_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_N_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM3_SHIFT)
#define GPIO_N_VM_04_0_VM3_RANGE                        5:4
#define GPIO_N_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_N_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_N_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_N_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM4_SHIFT)
#define GPIO_N_VM_04_0_VM4_RANGE                        7:6
#define GPIO_N_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_N_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_N_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM5_SHIFT)
#define GPIO_N_VM_04_0_VM5_RANGE                        9:8
#define GPIO_N_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_N_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_N_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_N_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM6_SHIFT)
#define GPIO_N_VM_04_0_VM6_RANGE                        11:10
#define GPIO_N_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_N_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_N_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_N_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM7_SHIFT)
#define GPIO_N_VM_04_0_VM7_RANGE                        13:12
#define GPIO_N_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_N_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_N_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_N_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM8_SHIFT)
#define GPIO_N_VM_04_0_VM8_RANGE                        15:14
#define GPIO_N_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_N_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_N_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_04_0
#define GPIO_N_SCR_04_0                 MK_ADDR_CONST(0x2064)
#define GPIO_N_SCR_04_0_SECURE                  0x0
#define GPIO_N_SCR_04_0_DUAL                    0x0
#define GPIO_N_SCR_04_0_SCR                     0
#define GPIO_N_SCR_04_0_SCRREG                  0
#define GPIO_N_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_N_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_N_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_N_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_N_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_N_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_N_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_N_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_N_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR7_SHIFT)
#define GPIO_N_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_N_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR6_SHIFT)
#define GPIO_N_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_N_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR5_SHIFT)
#define GPIO_N_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_N_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR4_SHIFT)
#define GPIO_N_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_N_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR3_SHIFT)
#define GPIO_N_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_N_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR2_SHIFT)
#define GPIO_N_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_N_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR1_SHIFT)
#define GPIO_N_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_N_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR0_SHIFT)
#define GPIO_N_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_N_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G7W_SHIFT)
#define GPIO_N_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_N_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G6W_SHIFT)
#define GPIO_N_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_N_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G5W_SHIFT)
#define GPIO_N_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_N_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G4W_SHIFT)
#define GPIO_N_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_N_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G3W_SHIFT)
#define GPIO_N_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_N_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G2W_SHIFT)
#define GPIO_N_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_N_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G1W_SHIFT)
#define GPIO_N_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_N_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G0W_SHIFT)
#define GPIO_N_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_N_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G7R_SHIFT)
#define GPIO_N_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_N_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G6R_SHIFT)
#define GPIO_N_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G5R_SHIFT)
#define GPIO_N_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_N_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G4R_SHIFT)
#define GPIO_N_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_N_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G3R_SHIFT)
#define GPIO_N_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_N_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G2R_SHIFT)
#define GPIO_N_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_N_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G1R_SHIFT)
#define GPIO_N_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G0R_SHIFT)
#define GPIO_N_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_N_VM_05_0
#define GPIO_N_VM_05_0                  MK_ADDR_CONST(0x2068)
#define GPIO_N_VM_05_0_SECURE                   0x0
#define GPIO_N_VM_05_0_DUAL                     0x0
#define GPIO_N_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_05_0_WORD_COUNT                       0x1
#define GPIO_N_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM1_SHIFT)
#define GPIO_N_VM_05_0_VM1_RANGE                        1:0
#define GPIO_N_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_N_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_N_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM2_SHIFT)
#define GPIO_N_VM_05_0_VM2_RANGE                        3:2
#define GPIO_N_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_N_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_N_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_N_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM3_SHIFT)
#define GPIO_N_VM_05_0_VM3_RANGE                        5:4
#define GPIO_N_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_N_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_N_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_N_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM4_SHIFT)
#define GPIO_N_VM_05_0_VM4_RANGE                        7:6
#define GPIO_N_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_N_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_N_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM5_SHIFT)
#define GPIO_N_VM_05_0_VM5_RANGE                        9:8
#define GPIO_N_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_N_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_N_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_N_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM6_SHIFT)
#define GPIO_N_VM_05_0_VM6_RANGE                        11:10
#define GPIO_N_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_N_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_N_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_N_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM7_SHIFT)
#define GPIO_N_VM_05_0_VM7_RANGE                        13:12
#define GPIO_N_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_N_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_N_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_N_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM8_SHIFT)
#define GPIO_N_VM_05_0_VM8_RANGE                        15:14
#define GPIO_N_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_N_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_N_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_05_0
#define GPIO_N_SCR_05_0                 MK_ADDR_CONST(0x206c)
#define GPIO_N_SCR_05_0_SECURE                  0x0
#define GPIO_N_SCR_05_0_DUAL                    0x0
#define GPIO_N_SCR_05_0_SCR                     0
#define GPIO_N_SCR_05_0_SCRREG                  0
#define GPIO_N_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_N_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_N_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_N_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_N_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_N_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_N_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_N_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_N_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR7_SHIFT)
#define GPIO_N_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_N_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR6_SHIFT)
#define GPIO_N_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_N_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR5_SHIFT)
#define GPIO_N_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_N_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR4_SHIFT)
#define GPIO_N_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_N_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR3_SHIFT)
#define GPIO_N_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_N_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR2_SHIFT)
#define GPIO_N_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_N_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR1_SHIFT)
#define GPIO_N_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_N_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR0_SHIFT)
#define GPIO_N_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_N_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G7W_SHIFT)
#define GPIO_N_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_N_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G6W_SHIFT)
#define GPIO_N_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_N_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G5W_SHIFT)
#define GPIO_N_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_N_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G4W_SHIFT)
#define GPIO_N_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_N_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G3W_SHIFT)
#define GPIO_N_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_N_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G2W_SHIFT)
#define GPIO_N_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_N_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G1W_SHIFT)
#define GPIO_N_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_N_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G0W_SHIFT)
#define GPIO_N_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_N_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G7R_SHIFT)
#define GPIO_N_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_N_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G6R_SHIFT)
#define GPIO_N_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G5R_SHIFT)
#define GPIO_N_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_N_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G4R_SHIFT)
#define GPIO_N_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_N_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G3R_SHIFT)
#define GPIO_N_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_N_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G2R_SHIFT)
#define GPIO_N_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_N_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G1R_SHIFT)
#define GPIO_N_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G0R_SHIFT)
#define GPIO_N_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_N_VM_06_0
#define GPIO_N_VM_06_0                  MK_ADDR_CONST(0x2070)
#define GPIO_N_VM_06_0_SECURE                   0x0
#define GPIO_N_VM_06_0_DUAL                     0x0
#define GPIO_N_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_06_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_06_0_WORD_COUNT                       0x1
#define GPIO_N_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM1_SHIFT)
#define GPIO_N_VM_06_0_VM1_RANGE                        1:0
#define GPIO_N_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_N_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_N_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM2_SHIFT)
#define GPIO_N_VM_06_0_VM2_RANGE                        3:2
#define GPIO_N_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_N_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_N_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_N_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM3_SHIFT)
#define GPIO_N_VM_06_0_VM3_RANGE                        5:4
#define GPIO_N_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_N_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_N_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_N_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM4_SHIFT)
#define GPIO_N_VM_06_0_VM4_RANGE                        7:6
#define GPIO_N_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_N_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_N_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM5_SHIFT)
#define GPIO_N_VM_06_0_VM5_RANGE                        9:8
#define GPIO_N_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_N_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_N_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_N_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM6_SHIFT)
#define GPIO_N_VM_06_0_VM6_RANGE                        11:10
#define GPIO_N_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_N_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_N_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_N_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM7_SHIFT)
#define GPIO_N_VM_06_0_VM7_RANGE                        13:12
#define GPIO_N_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_N_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_N_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_N_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM8_SHIFT)
#define GPIO_N_VM_06_0_VM8_RANGE                        15:14
#define GPIO_N_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_N_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_N_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_06_0
#define GPIO_N_SCR_06_0                 MK_ADDR_CONST(0x2074)
#define GPIO_N_SCR_06_0_SECURE                  0x0
#define GPIO_N_SCR_06_0_DUAL                    0x0
#define GPIO_N_SCR_06_0_SCR                     0
#define GPIO_N_SCR_06_0_SCRREG                  0
#define GPIO_N_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_N_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_N_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_N_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_N_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_N_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_N_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_N_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_N_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR7_SHIFT)
#define GPIO_N_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_N_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR6_SHIFT)
#define GPIO_N_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_N_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR5_SHIFT)
#define GPIO_N_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_N_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR4_SHIFT)
#define GPIO_N_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_N_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR3_SHIFT)
#define GPIO_N_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_N_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR2_SHIFT)
#define GPIO_N_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_N_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR1_SHIFT)
#define GPIO_N_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_N_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR0_SHIFT)
#define GPIO_N_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_N_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G7W_SHIFT)
#define GPIO_N_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_N_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G6W_SHIFT)
#define GPIO_N_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_N_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G5W_SHIFT)
#define GPIO_N_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_N_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G4W_SHIFT)
#define GPIO_N_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_N_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G3W_SHIFT)
#define GPIO_N_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_N_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G2W_SHIFT)
#define GPIO_N_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_N_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G1W_SHIFT)
#define GPIO_N_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_N_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G0W_SHIFT)
#define GPIO_N_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_N_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G7R_SHIFT)
#define GPIO_N_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_N_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G6R_SHIFT)
#define GPIO_N_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G5R_SHIFT)
#define GPIO_N_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_N_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G4R_SHIFT)
#define GPIO_N_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_N_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G3R_SHIFT)
#define GPIO_N_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_N_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G2R_SHIFT)
#define GPIO_N_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_N_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G1R_SHIFT)
#define GPIO_N_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G0R_SHIFT)
#define GPIO_N_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_N_VM_07_0
#define GPIO_N_VM_07_0                  MK_ADDR_CONST(0x2078)
#define GPIO_N_VM_07_0_SECURE                   0x0
#define GPIO_N_VM_07_0_DUAL                     0x0
#define GPIO_N_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_07_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_N_VM_07_0_WORD_COUNT                       0x1
#define GPIO_N_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_N_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_N_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM1_SHIFT)
#define GPIO_N_VM_07_0_VM1_RANGE                        1:0
#define GPIO_N_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_N_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_N_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_N_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM2_SHIFT)
#define GPIO_N_VM_07_0_VM2_RANGE                        3:2
#define GPIO_N_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_N_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_N_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_N_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_N_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM3_SHIFT)
#define GPIO_N_VM_07_0_VM3_RANGE                        5:4
#define GPIO_N_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_N_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_N_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_N_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_N_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM4_SHIFT)
#define GPIO_N_VM_07_0_VM4_RANGE                        7:6
#define GPIO_N_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_N_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_N_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_N_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM5_SHIFT)
#define GPIO_N_VM_07_0_VM5_RANGE                        9:8
#define GPIO_N_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_N_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_N_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_N_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_N_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM6_SHIFT)
#define GPIO_N_VM_07_0_VM6_RANGE                        11:10
#define GPIO_N_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_N_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_N_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_N_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_N_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM7_SHIFT)
#define GPIO_N_VM_07_0_VM7_RANGE                        13:12
#define GPIO_N_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_N_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_N_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_N_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_N_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_N_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM8_SHIFT)
#define GPIO_N_VM_07_0_VM8_RANGE                        15:14
#define GPIO_N_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_N_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_N_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_N_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_N_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_SCR_07_0
#define GPIO_N_SCR_07_0                 MK_ADDR_CONST(0x207c)
#define GPIO_N_SCR_07_0_SECURE                  0x0
#define GPIO_N_SCR_07_0_DUAL                    0x0
#define GPIO_N_SCR_07_0_SCR                     0
#define GPIO_N_SCR_07_0_SCRREG                  0
#define GPIO_N_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_N_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_N_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_N_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_N_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_N_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_N_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_N_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_N_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_N_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_N_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_N_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_N_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_N_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_N_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_N_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_N_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_N_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_N_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_N_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_N_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_N_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_N_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_N_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_N_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_N_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR7_SHIFT)
#define GPIO_N_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_N_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_N_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_N_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR6_SHIFT)
#define GPIO_N_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_N_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_N_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_N_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR5_SHIFT)
#define GPIO_N_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_N_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_N_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_N_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR4_SHIFT)
#define GPIO_N_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_N_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_N_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_N_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR3_SHIFT)
#define GPIO_N_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_N_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_N_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_N_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR2_SHIFT)
#define GPIO_N_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_N_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_N_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_N_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR1_SHIFT)
#define GPIO_N_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_N_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_N_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_N_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR0_SHIFT)
#define GPIO_N_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_N_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_N_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_N_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G7W_SHIFT)
#define GPIO_N_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_N_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_N_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_N_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G6W_SHIFT)
#define GPIO_N_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_N_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_N_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_N_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G5W_SHIFT)
#define GPIO_N_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_N_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_N_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_N_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G4W_SHIFT)
#define GPIO_N_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_N_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_N_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_N_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G3W_SHIFT)
#define GPIO_N_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_N_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_N_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_N_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G2W_SHIFT)
#define GPIO_N_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_N_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_N_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_N_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G1W_SHIFT)
#define GPIO_N_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_N_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_N_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_N_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G0W_SHIFT)
#define GPIO_N_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_N_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_N_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_N_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G7R_SHIFT)
#define GPIO_N_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_N_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_N_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_N_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G6R_SHIFT)
#define GPIO_N_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_N_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_N_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G5R_SHIFT)
#define GPIO_N_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_N_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_N_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G4R_SHIFT)
#define GPIO_N_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_N_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_N_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_N_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G3R_SHIFT)
#define GPIO_N_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_N_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_N_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_N_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G2R_SHIFT)
#define GPIO_N_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_N_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_N_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_N_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G1R_SHIFT)
#define GPIO_N_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_N_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_N_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_N_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G0R_SHIFT)
#define GPIO_N_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_N_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_N_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_N_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_P_VM_00_0
#define GPIO_P_VM_00_0                  MK_ADDR_CONST(0x2080)
#define GPIO_P_VM_00_0_SECURE                   0x0
#define GPIO_P_VM_00_0_DUAL                     0x0
#define GPIO_P_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_00_0_WORD_COUNT                       0x1
#define GPIO_P_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM1_SHIFT)
#define GPIO_P_VM_00_0_VM1_RANGE                        1:0
#define GPIO_P_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_P_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_P_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM2_SHIFT)
#define GPIO_P_VM_00_0_VM2_RANGE                        3:2
#define GPIO_P_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_P_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_P_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_P_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM3_SHIFT)
#define GPIO_P_VM_00_0_VM3_RANGE                        5:4
#define GPIO_P_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_P_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_P_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_P_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM4_SHIFT)
#define GPIO_P_VM_00_0_VM4_RANGE                        7:6
#define GPIO_P_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_P_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_P_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM5_SHIFT)
#define GPIO_P_VM_00_0_VM5_RANGE                        9:8
#define GPIO_P_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_P_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_P_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_P_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM6_SHIFT)
#define GPIO_P_VM_00_0_VM6_RANGE                        11:10
#define GPIO_P_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_P_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_P_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_P_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM7_SHIFT)
#define GPIO_P_VM_00_0_VM7_RANGE                        13:12
#define GPIO_P_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_P_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_P_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_P_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM8_SHIFT)
#define GPIO_P_VM_00_0_VM8_RANGE                        15:14
#define GPIO_P_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_P_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_P_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_00_0
#define GPIO_P_SCR_00_0                 MK_ADDR_CONST(0x2084)
#define GPIO_P_SCR_00_0_SECURE                  0x0
#define GPIO_P_SCR_00_0_DUAL                    0x0
#define GPIO_P_SCR_00_0_SCR                     0
#define GPIO_P_SCR_00_0_SCRREG                  0
#define GPIO_P_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_P_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_P_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_P_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_P_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_P_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_P_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_P_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_P_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR7_SHIFT)
#define GPIO_P_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_P_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR6_SHIFT)
#define GPIO_P_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_P_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR5_SHIFT)
#define GPIO_P_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_P_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR4_SHIFT)
#define GPIO_P_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_P_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR3_SHIFT)
#define GPIO_P_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_P_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR2_SHIFT)
#define GPIO_P_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_P_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR1_SHIFT)
#define GPIO_P_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_P_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR0_SHIFT)
#define GPIO_P_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_P_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G7W_SHIFT)
#define GPIO_P_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_P_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G6W_SHIFT)
#define GPIO_P_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_P_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G5W_SHIFT)
#define GPIO_P_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_P_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G4W_SHIFT)
#define GPIO_P_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_P_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G3W_SHIFT)
#define GPIO_P_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_P_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G2W_SHIFT)
#define GPIO_P_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_P_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G1W_SHIFT)
#define GPIO_P_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_P_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G0W_SHIFT)
#define GPIO_P_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_P_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G7R_SHIFT)
#define GPIO_P_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_P_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G6R_SHIFT)
#define GPIO_P_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G5R_SHIFT)
#define GPIO_P_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_P_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G4R_SHIFT)
#define GPIO_P_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_P_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G3R_SHIFT)
#define GPIO_P_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_P_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G2R_SHIFT)
#define GPIO_P_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_P_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G1R_SHIFT)
#define GPIO_P_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G0R_SHIFT)
#define GPIO_P_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_P_VM_01_0
#define GPIO_P_VM_01_0                  MK_ADDR_CONST(0x2088)
#define GPIO_P_VM_01_0_SECURE                   0x0
#define GPIO_P_VM_01_0_DUAL                     0x0
#define GPIO_P_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_01_0_WORD_COUNT                       0x1
#define GPIO_P_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM1_SHIFT)
#define GPIO_P_VM_01_0_VM1_RANGE                        1:0
#define GPIO_P_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_P_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_P_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM2_SHIFT)
#define GPIO_P_VM_01_0_VM2_RANGE                        3:2
#define GPIO_P_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_P_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_P_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_P_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM3_SHIFT)
#define GPIO_P_VM_01_0_VM3_RANGE                        5:4
#define GPIO_P_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_P_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_P_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_P_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM4_SHIFT)
#define GPIO_P_VM_01_0_VM4_RANGE                        7:6
#define GPIO_P_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_P_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_P_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM5_SHIFT)
#define GPIO_P_VM_01_0_VM5_RANGE                        9:8
#define GPIO_P_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_P_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_P_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_P_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM6_SHIFT)
#define GPIO_P_VM_01_0_VM6_RANGE                        11:10
#define GPIO_P_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_P_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_P_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_P_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM7_SHIFT)
#define GPIO_P_VM_01_0_VM7_RANGE                        13:12
#define GPIO_P_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_P_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_P_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_P_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM8_SHIFT)
#define GPIO_P_VM_01_0_VM8_RANGE                        15:14
#define GPIO_P_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_P_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_P_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_01_0
#define GPIO_P_SCR_01_0                 MK_ADDR_CONST(0x208c)
#define GPIO_P_SCR_01_0_SECURE                  0x0
#define GPIO_P_SCR_01_0_DUAL                    0x0
#define GPIO_P_SCR_01_0_SCR                     0
#define GPIO_P_SCR_01_0_SCRREG                  0
#define GPIO_P_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_P_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_P_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_P_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_P_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_P_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_P_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_P_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_P_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR7_SHIFT)
#define GPIO_P_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_P_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR6_SHIFT)
#define GPIO_P_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_P_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR5_SHIFT)
#define GPIO_P_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_P_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR4_SHIFT)
#define GPIO_P_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_P_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR3_SHIFT)
#define GPIO_P_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_P_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR2_SHIFT)
#define GPIO_P_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_P_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR1_SHIFT)
#define GPIO_P_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_P_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR0_SHIFT)
#define GPIO_P_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_P_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G7W_SHIFT)
#define GPIO_P_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_P_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G6W_SHIFT)
#define GPIO_P_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_P_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G5W_SHIFT)
#define GPIO_P_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_P_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G4W_SHIFT)
#define GPIO_P_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_P_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G3W_SHIFT)
#define GPIO_P_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_P_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G2W_SHIFT)
#define GPIO_P_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_P_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G1W_SHIFT)
#define GPIO_P_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_P_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G0W_SHIFT)
#define GPIO_P_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_P_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G7R_SHIFT)
#define GPIO_P_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_P_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G6R_SHIFT)
#define GPIO_P_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G5R_SHIFT)
#define GPIO_P_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_P_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G4R_SHIFT)
#define GPIO_P_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_P_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G3R_SHIFT)
#define GPIO_P_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_P_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G2R_SHIFT)
#define GPIO_P_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_P_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G1R_SHIFT)
#define GPIO_P_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G0R_SHIFT)
#define GPIO_P_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_P_VM_02_0
#define GPIO_P_VM_02_0                  MK_ADDR_CONST(0x2090)
#define GPIO_P_VM_02_0_SECURE                   0x0
#define GPIO_P_VM_02_0_DUAL                     0x0
#define GPIO_P_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_02_0_WORD_COUNT                       0x1
#define GPIO_P_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM1_SHIFT)
#define GPIO_P_VM_02_0_VM1_RANGE                        1:0
#define GPIO_P_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_P_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_P_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM2_SHIFT)
#define GPIO_P_VM_02_0_VM2_RANGE                        3:2
#define GPIO_P_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_P_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_P_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_P_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM3_SHIFT)
#define GPIO_P_VM_02_0_VM3_RANGE                        5:4
#define GPIO_P_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_P_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_P_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_P_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM4_SHIFT)
#define GPIO_P_VM_02_0_VM4_RANGE                        7:6
#define GPIO_P_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_P_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_P_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM5_SHIFT)
#define GPIO_P_VM_02_0_VM5_RANGE                        9:8
#define GPIO_P_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_P_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_P_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_P_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM6_SHIFT)
#define GPIO_P_VM_02_0_VM6_RANGE                        11:10
#define GPIO_P_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_P_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_P_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_P_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM7_SHIFT)
#define GPIO_P_VM_02_0_VM7_RANGE                        13:12
#define GPIO_P_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_P_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_P_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_P_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM8_SHIFT)
#define GPIO_P_VM_02_0_VM8_RANGE                        15:14
#define GPIO_P_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_P_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_P_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_02_0
#define GPIO_P_SCR_02_0                 MK_ADDR_CONST(0x2094)
#define GPIO_P_SCR_02_0_SECURE                  0x0
#define GPIO_P_SCR_02_0_DUAL                    0x0
#define GPIO_P_SCR_02_0_SCR                     0
#define GPIO_P_SCR_02_0_SCRREG                  0
#define GPIO_P_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_P_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_P_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_P_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_P_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_P_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_P_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_P_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_P_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR7_SHIFT)
#define GPIO_P_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_P_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR6_SHIFT)
#define GPIO_P_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_P_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR5_SHIFT)
#define GPIO_P_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_P_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR4_SHIFT)
#define GPIO_P_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_P_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR3_SHIFT)
#define GPIO_P_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_P_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR2_SHIFT)
#define GPIO_P_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_P_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR1_SHIFT)
#define GPIO_P_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_P_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR0_SHIFT)
#define GPIO_P_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_P_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G7W_SHIFT)
#define GPIO_P_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_P_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G6W_SHIFT)
#define GPIO_P_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_P_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G5W_SHIFT)
#define GPIO_P_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_P_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G4W_SHIFT)
#define GPIO_P_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_P_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G3W_SHIFT)
#define GPIO_P_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_P_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G2W_SHIFT)
#define GPIO_P_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_P_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G1W_SHIFT)
#define GPIO_P_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_P_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G0W_SHIFT)
#define GPIO_P_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_P_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G7R_SHIFT)
#define GPIO_P_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_P_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G6R_SHIFT)
#define GPIO_P_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G5R_SHIFT)
#define GPIO_P_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_P_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G4R_SHIFT)
#define GPIO_P_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_P_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G3R_SHIFT)
#define GPIO_P_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_P_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G2R_SHIFT)
#define GPIO_P_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_P_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G1R_SHIFT)
#define GPIO_P_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G0R_SHIFT)
#define GPIO_P_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_P_VM_03_0
#define GPIO_P_VM_03_0                  MK_ADDR_CONST(0x2098)
#define GPIO_P_VM_03_0_SECURE                   0x0
#define GPIO_P_VM_03_0_DUAL                     0x0
#define GPIO_P_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_03_0_WORD_COUNT                       0x1
#define GPIO_P_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM1_SHIFT)
#define GPIO_P_VM_03_0_VM1_RANGE                        1:0
#define GPIO_P_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_P_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_P_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM2_SHIFT)
#define GPIO_P_VM_03_0_VM2_RANGE                        3:2
#define GPIO_P_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_P_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_P_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_P_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM3_SHIFT)
#define GPIO_P_VM_03_0_VM3_RANGE                        5:4
#define GPIO_P_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_P_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_P_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_P_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM4_SHIFT)
#define GPIO_P_VM_03_0_VM4_RANGE                        7:6
#define GPIO_P_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_P_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_P_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM5_SHIFT)
#define GPIO_P_VM_03_0_VM5_RANGE                        9:8
#define GPIO_P_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_P_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_P_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_P_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM6_SHIFT)
#define GPIO_P_VM_03_0_VM6_RANGE                        11:10
#define GPIO_P_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_P_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_P_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_P_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM7_SHIFT)
#define GPIO_P_VM_03_0_VM7_RANGE                        13:12
#define GPIO_P_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_P_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_P_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_P_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM8_SHIFT)
#define GPIO_P_VM_03_0_VM8_RANGE                        15:14
#define GPIO_P_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_P_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_P_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_03_0
#define GPIO_P_SCR_03_0                 MK_ADDR_CONST(0x209c)
#define GPIO_P_SCR_03_0_SECURE                  0x0
#define GPIO_P_SCR_03_0_DUAL                    0x0
#define GPIO_P_SCR_03_0_SCR                     0
#define GPIO_P_SCR_03_0_SCRREG                  0
#define GPIO_P_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_P_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_P_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_P_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_P_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_P_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_P_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_P_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_P_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR7_SHIFT)
#define GPIO_P_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_P_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR6_SHIFT)
#define GPIO_P_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_P_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR5_SHIFT)
#define GPIO_P_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_P_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR4_SHIFT)
#define GPIO_P_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_P_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR3_SHIFT)
#define GPIO_P_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_P_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR2_SHIFT)
#define GPIO_P_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_P_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR1_SHIFT)
#define GPIO_P_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_P_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR0_SHIFT)
#define GPIO_P_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_P_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G7W_SHIFT)
#define GPIO_P_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_P_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G6W_SHIFT)
#define GPIO_P_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_P_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G5W_SHIFT)
#define GPIO_P_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_P_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G4W_SHIFT)
#define GPIO_P_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_P_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G3W_SHIFT)
#define GPIO_P_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_P_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G2W_SHIFT)
#define GPIO_P_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_P_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G1W_SHIFT)
#define GPIO_P_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_P_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G0W_SHIFT)
#define GPIO_P_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_P_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G7R_SHIFT)
#define GPIO_P_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_P_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G6R_SHIFT)
#define GPIO_P_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G5R_SHIFT)
#define GPIO_P_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_P_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G4R_SHIFT)
#define GPIO_P_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_P_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G3R_SHIFT)
#define GPIO_P_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_P_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G2R_SHIFT)
#define GPIO_P_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_P_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G1R_SHIFT)
#define GPIO_P_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G0R_SHIFT)
#define GPIO_P_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_P_VM_04_0
#define GPIO_P_VM_04_0                  MK_ADDR_CONST(0x20a0)
#define GPIO_P_VM_04_0_SECURE                   0x0
#define GPIO_P_VM_04_0_DUAL                     0x0
#define GPIO_P_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_04_0_WORD_COUNT                       0x1
#define GPIO_P_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM1_SHIFT)
#define GPIO_P_VM_04_0_VM1_RANGE                        1:0
#define GPIO_P_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_P_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_P_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM2_SHIFT)
#define GPIO_P_VM_04_0_VM2_RANGE                        3:2
#define GPIO_P_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_P_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_P_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_P_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM3_SHIFT)
#define GPIO_P_VM_04_0_VM3_RANGE                        5:4
#define GPIO_P_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_P_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_P_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_P_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM4_SHIFT)
#define GPIO_P_VM_04_0_VM4_RANGE                        7:6
#define GPIO_P_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_P_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_P_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM5_SHIFT)
#define GPIO_P_VM_04_0_VM5_RANGE                        9:8
#define GPIO_P_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_P_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_P_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_P_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM6_SHIFT)
#define GPIO_P_VM_04_0_VM6_RANGE                        11:10
#define GPIO_P_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_P_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_P_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_P_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM7_SHIFT)
#define GPIO_P_VM_04_0_VM7_RANGE                        13:12
#define GPIO_P_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_P_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_P_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_P_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM8_SHIFT)
#define GPIO_P_VM_04_0_VM8_RANGE                        15:14
#define GPIO_P_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_P_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_P_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_04_0
#define GPIO_P_SCR_04_0                 MK_ADDR_CONST(0x20a4)
#define GPIO_P_SCR_04_0_SECURE                  0x0
#define GPIO_P_SCR_04_0_DUAL                    0x0
#define GPIO_P_SCR_04_0_SCR                     0
#define GPIO_P_SCR_04_0_SCRREG                  0
#define GPIO_P_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_P_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_P_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_P_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_P_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_P_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_P_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_P_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_P_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR7_SHIFT)
#define GPIO_P_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_P_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR6_SHIFT)
#define GPIO_P_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_P_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR5_SHIFT)
#define GPIO_P_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_P_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR4_SHIFT)
#define GPIO_P_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_P_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR3_SHIFT)
#define GPIO_P_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_P_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR2_SHIFT)
#define GPIO_P_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_P_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR1_SHIFT)
#define GPIO_P_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_P_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR0_SHIFT)
#define GPIO_P_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_P_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G7W_SHIFT)
#define GPIO_P_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_P_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G6W_SHIFT)
#define GPIO_P_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_P_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G5W_SHIFT)
#define GPIO_P_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_P_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G4W_SHIFT)
#define GPIO_P_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_P_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G3W_SHIFT)
#define GPIO_P_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_P_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G2W_SHIFT)
#define GPIO_P_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_P_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G1W_SHIFT)
#define GPIO_P_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_P_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G0W_SHIFT)
#define GPIO_P_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_P_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G7R_SHIFT)
#define GPIO_P_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_P_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G6R_SHIFT)
#define GPIO_P_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G5R_SHIFT)
#define GPIO_P_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_P_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G4R_SHIFT)
#define GPIO_P_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_P_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G3R_SHIFT)
#define GPIO_P_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_P_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G2R_SHIFT)
#define GPIO_P_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_P_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G1R_SHIFT)
#define GPIO_P_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G0R_SHIFT)
#define GPIO_P_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_P_VM_05_0
#define GPIO_P_VM_05_0                  MK_ADDR_CONST(0x20a8)
#define GPIO_P_VM_05_0_SECURE                   0x0
#define GPIO_P_VM_05_0_DUAL                     0x0
#define GPIO_P_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_05_0_WORD_COUNT                       0x1
#define GPIO_P_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM1_SHIFT)
#define GPIO_P_VM_05_0_VM1_RANGE                        1:0
#define GPIO_P_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_P_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_P_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM2_SHIFT)
#define GPIO_P_VM_05_0_VM2_RANGE                        3:2
#define GPIO_P_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_P_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_P_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_P_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM3_SHIFT)
#define GPIO_P_VM_05_0_VM3_RANGE                        5:4
#define GPIO_P_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_P_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_P_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_P_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM4_SHIFT)
#define GPIO_P_VM_05_0_VM4_RANGE                        7:6
#define GPIO_P_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_P_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_P_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM5_SHIFT)
#define GPIO_P_VM_05_0_VM5_RANGE                        9:8
#define GPIO_P_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_P_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_P_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_P_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM6_SHIFT)
#define GPIO_P_VM_05_0_VM6_RANGE                        11:10
#define GPIO_P_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_P_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_P_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_P_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM7_SHIFT)
#define GPIO_P_VM_05_0_VM7_RANGE                        13:12
#define GPIO_P_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_P_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_P_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_P_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM8_SHIFT)
#define GPIO_P_VM_05_0_VM8_RANGE                        15:14
#define GPIO_P_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_P_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_P_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_05_0
#define GPIO_P_SCR_05_0                 MK_ADDR_CONST(0x20ac)
#define GPIO_P_SCR_05_0_SECURE                  0x0
#define GPIO_P_SCR_05_0_DUAL                    0x0
#define GPIO_P_SCR_05_0_SCR                     0
#define GPIO_P_SCR_05_0_SCRREG                  0
#define GPIO_P_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_P_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_P_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_P_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_P_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_P_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_P_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_P_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_P_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR7_SHIFT)
#define GPIO_P_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_P_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR6_SHIFT)
#define GPIO_P_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_P_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR5_SHIFT)
#define GPIO_P_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_P_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR4_SHIFT)
#define GPIO_P_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_P_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR3_SHIFT)
#define GPIO_P_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_P_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR2_SHIFT)
#define GPIO_P_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_P_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR1_SHIFT)
#define GPIO_P_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_P_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR0_SHIFT)
#define GPIO_P_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_P_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G7W_SHIFT)
#define GPIO_P_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_P_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G6W_SHIFT)
#define GPIO_P_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_P_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G5W_SHIFT)
#define GPIO_P_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_P_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G4W_SHIFT)
#define GPIO_P_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_P_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G3W_SHIFT)
#define GPIO_P_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_P_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G2W_SHIFT)
#define GPIO_P_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_P_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G1W_SHIFT)
#define GPIO_P_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_P_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G0W_SHIFT)
#define GPIO_P_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_P_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G7R_SHIFT)
#define GPIO_P_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_P_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G6R_SHIFT)
#define GPIO_P_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G5R_SHIFT)
#define GPIO_P_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_P_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G4R_SHIFT)
#define GPIO_P_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_P_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G3R_SHIFT)
#define GPIO_P_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_P_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G2R_SHIFT)
#define GPIO_P_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_P_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G1R_SHIFT)
#define GPIO_P_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G0R_SHIFT)
#define GPIO_P_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_P_VM_06_0
#define GPIO_P_VM_06_0                  MK_ADDR_CONST(0x20b0)
#define GPIO_P_VM_06_0_SECURE                   0x0
#define GPIO_P_VM_06_0_DUAL                     0x0
#define GPIO_P_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_06_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_06_0_WORD_COUNT                       0x1
#define GPIO_P_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM1_SHIFT)
#define GPIO_P_VM_06_0_VM1_RANGE                        1:0
#define GPIO_P_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_P_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_P_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM2_SHIFT)
#define GPIO_P_VM_06_0_VM2_RANGE                        3:2
#define GPIO_P_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_P_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_P_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_P_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM3_SHIFT)
#define GPIO_P_VM_06_0_VM3_RANGE                        5:4
#define GPIO_P_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_P_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_P_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_P_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM4_SHIFT)
#define GPIO_P_VM_06_0_VM4_RANGE                        7:6
#define GPIO_P_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_P_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_P_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM5_SHIFT)
#define GPIO_P_VM_06_0_VM5_RANGE                        9:8
#define GPIO_P_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_P_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_P_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_P_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM6_SHIFT)
#define GPIO_P_VM_06_0_VM6_RANGE                        11:10
#define GPIO_P_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_P_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_P_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_P_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM7_SHIFT)
#define GPIO_P_VM_06_0_VM7_RANGE                        13:12
#define GPIO_P_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_P_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_P_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_P_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM8_SHIFT)
#define GPIO_P_VM_06_0_VM8_RANGE                        15:14
#define GPIO_P_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_P_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_P_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_06_0
#define GPIO_P_SCR_06_0                 MK_ADDR_CONST(0x20b4)
#define GPIO_P_SCR_06_0_SECURE                  0x0
#define GPIO_P_SCR_06_0_DUAL                    0x0
#define GPIO_P_SCR_06_0_SCR                     0
#define GPIO_P_SCR_06_0_SCRREG                  0
#define GPIO_P_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_P_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_P_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_P_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_P_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_P_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_P_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_P_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_P_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR7_SHIFT)
#define GPIO_P_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_P_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR6_SHIFT)
#define GPIO_P_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_P_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR5_SHIFT)
#define GPIO_P_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_P_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR4_SHIFT)
#define GPIO_P_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_P_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR3_SHIFT)
#define GPIO_P_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_P_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR2_SHIFT)
#define GPIO_P_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_P_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR1_SHIFT)
#define GPIO_P_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_P_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR0_SHIFT)
#define GPIO_P_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_P_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G7W_SHIFT)
#define GPIO_P_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_P_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G6W_SHIFT)
#define GPIO_P_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_P_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G5W_SHIFT)
#define GPIO_P_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_P_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G4W_SHIFT)
#define GPIO_P_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_P_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G3W_SHIFT)
#define GPIO_P_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_P_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G2W_SHIFT)
#define GPIO_P_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_P_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G1W_SHIFT)
#define GPIO_P_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_P_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G0W_SHIFT)
#define GPIO_P_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_P_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G7R_SHIFT)
#define GPIO_P_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_P_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G6R_SHIFT)
#define GPIO_P_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G5R_SHIFT)
#define GPIO_P_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_P_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G4R_SHIFT)
#define GPIO_P_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_P_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G3R_SHIFT)
#define GPIO_P_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_P_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G2R_SHIFT)
#define GPIO_P_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_P_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G1R_SHIFT)
#define GPIO_P_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G0R_SHIFT)
#define GPIO_P_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_P_VM_07_0
#define GPIO_P_VM_07_0                  MK_ADDR_CONST(0x20b8)
#define GPIO_P_VM_07_0_SECURE                   0x0
#define GPIO_P_VM_07_0_DUAL                     0x0
#define GPIO_P_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_07_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_P_VM_07_0_WORD_COUNT                       0x1
#define GPIO_P_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_P_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_P_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM1_SHIFT)
#define GPIO_P_VM_07_0_VM1_RANGE                        1:0
#define GPIO_P_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_P_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_P_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM2_SHIFT)
#define GPIO_P_VM_07_0_VM2_RANGE                        3:2
#define GPIO_P_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_P_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_P_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_P_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM3_SHIFT)
#define GPIO_P_VM_07_0_VM3_RANGE                        5:4
#define GPIO_P_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_P_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_P_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_P_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM4_SHIFT)
#define GPIO_P_VM_07_0_VM4_RANGE                        7:6
#define GPIO_P_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_P_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_P_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM5_SHIFT)
#define GPIO_P_VM_07_0_VM5_RANGE                        9:8
#define GPIO_P_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_P_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_P_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_P_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM6_SHIFT)
#define GPIO_P_VM_07_0_VM6_RANGE                        11:10
#define GPIO_P_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_P_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_P_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_P_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM7_SHIFT)
#define GPIO_P_VM_07_0_VM7_RANGE                        13:12
#define GPIO_P_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_P_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_P_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_P_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_P_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM8_SHIFT)
#define GPIO_P_VM_07_0_VM8_RANGE                        15:14
#define GPIO_P_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_P_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_P_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_P_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_P_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_SCR_07_0
#define GPIO_P_SCR_07_0                 MK_ADDR_CONST(0x20bc)
#define GPIO_P_SCR_07_0_SECURE                  0x0
#define GPIO_P_SCR_07_0_DUAL                    0x0
#define GPIO_P_SCR_07_0_SCR                     0
#define GPIO_P_SCR_07_0_SCRREG                  0
#define GPIO_P_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_P_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_P_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_P_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_P_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_P_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_P_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_P_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_P_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_P_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_P_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_P_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_P_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_P_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_P_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_P_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_P_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_P_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_P_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_P_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_P_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_P_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_P_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_P_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_P_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_P_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR7_SHIFT)
#define GPIO_P_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_P_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_P_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_P_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR6_SHIFT)
#define GPIO_P_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_P_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_P_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_P_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR5_SHIFT)
#define GPIO_P_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_P_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_P_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_P_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR4_SHIFT)
#define GPIO_P_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_P_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_P_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_P_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR3_SHIFT)
#define GPIO_P_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_P_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_P_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_P_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR2_SHIFT)
#define GPIO_P_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_P_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_P_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_P_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR1_SHIFT)
#define GPIO_P_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_P_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_P_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_P_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR0_SHIFT)
#define GPIO_P_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_P_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_P_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_P_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G7W_SHIFT)
#define GPIO_P_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_P_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_P_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_P_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G6W_SHIFT)
#define GPIO_P_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_P_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_P_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_P_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G5W_SHIFT)
#define GPIO_P_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_P_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_P_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_P_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G4W_SHIFT)
#define GPIO_P_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_P_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_P_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_P_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G3W_SHIFT)
#define GPIO_P_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_P_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_P_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_P_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G2W_SHIFT)
#define GPIO_P_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_P_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_P_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_P_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G1W_SHIFT)
#define GPIO_P_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_P_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_P_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_P_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G0W_SHIFT)
#define GPIO_P_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_P_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_P_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_P_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G7R_SHIFT)
#define GPIO_P_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_P_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_P_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_P_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G6R_SHIFT)
#define GPIO_P_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_P_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_P_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G5R_SHIFT)
#define GPIO_P_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_P_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_P_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G4R_SHIFT)
#define GPIO_P_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_P_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_P_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_P_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G3R_SHIFT)
#define GPIO_P_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_P_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_P_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_P_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G2R_SHIFT)
#define GPIO_P_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_P_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_P_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_P_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G1R_SHIFT)
#define GPIO_P_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_P_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_P_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_P_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G0R_SHIFT)
#define GPIO_P_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_P_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_P_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_P_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_00_0
#define GPIO_Q_VM_00_0                  MK_ADDR_CONST(0x20c0)
#define GPIO_Q_VM_00_0_SECURE                   0x0
#define GPIO_Q_VM_00_0_DUAL                     0x0
#define GPIO_Q_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_00_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM1_SHIFT)
#define GPIO_Q_VM_00_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Q_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Q_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM2_SHIFT)
#define GPIO_Q_VM_00_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Q_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Q_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Q_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM3_SHIFT)
#define GPIO_Q_VM_00_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Q_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Q_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Q_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM4_SHIFT)
#define GPIO_Q_VM_00_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Q_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Q_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM5_SHIFT)
#define GPIO_Q_VM_00_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Q_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Q_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Q_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM6_SHIFT)
#define GPIO_Q_VM_00_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Q_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Q_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Q_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM7_SHIFT)
#define GPIO_Q_VM_00_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Q_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Q_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Q_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM8_SHIFT)
#define GPIO_Q_VM_00_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Q_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Q_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_00_0
#define GPIO_Q_SCR_00_0                 MK_ADDR_CONST(0x20c4)
#define GPIO_Q_SCR_00_0_SECURE                  0x0
#define GPIO_Q_SCR_00_0_DUAL                    0x0
#define GPIO_Q_SCR_00_0_SCR                     0
#define GPIO_Q_SCR_00_0_SCRREG                  0
#define GPIO_Q_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Q_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR7_SHIFT)
#define GPIO_Q_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR6_SHIFT)
#define GPIO_Q_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR5_SHIFT)
#define GPIO_Q_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR4_SHIFT)
#define GPIO_Q_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR3_SHIFT)
#define GPIO_Q_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR2_SHIFT)
#define GPIO_Q_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR1_SHIFT)
#define GPIO_Q_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR0_SHIFT)
#define GPIO_Q_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G7W_SHIFT)
#define GPIO_Q_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G6W_SHIFT)
#define GPIO_Q_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G5W_SHIFT)
#define GPIO_Q_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G4W_SHIFT)
#define GPIO_Q_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G3W_SHIFT)
#define GPIO_Q_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G2W_SHIFT)
#define GPIO_Q_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G1W_SHIFT)
#define GPIO_Q_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G0W_SHIFT)
#define GPIO_Q_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G7R_SHIFT)
#define GPIO_Q_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G6R_SHIFT)
#define GPIO_Q_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G5R_SHIFT)
#define GPIO_Q_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G4R_SHIFT)
#define GPIO_Q_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G3R_SHIFT)
#define GPIO_Q_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G2R_SHIFT)
#define GPIO_Q_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G1R_SHIFT)
#define GPIO_Q_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G0R_SHIFT)
#define GPIO_Q_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_01_0
#define GPIO_Q_VM_01_0                  MK_ADDR_CONST(0x20c8)
#define GPIO_Q_VM_01_0_SECURE                   0x0
#define GPIO_Q_VM_01_0_DUAL                     0x0
#define GPIO_Q_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_01_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM1_SHIFT)
#define GPIO_Q_VM_01_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Q_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Q_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM2_SHIFT)
#define GPIO_Q_VM_01_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Q_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Q_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Q_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM3_SHIFT)
#define GPIO_Q_VM_01_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Q_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Q_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Q_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM4_SHIFT)
#define GPIO_Q_VM_01_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Q_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Q_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM5_SHIFT)
#define GPIO_Q_VM_01_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Q_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Q_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Q_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM6_SHIFT)
#define GPIO_Q_VM_01_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Q_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Q_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Q_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM7_SHIFT)
#define GPIO_Q_VM_01_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Q_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Q_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Q_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM8_SHIFT)
#define GPIO_Q_VM_01_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Q_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Q_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_01_0
#define GPIO_Q_SCR_01_0                 MK_ADDR_CONST(0x20cc)
#define GPIO_Q_SCR_01_0_SECURE                  0x0
#define GPIO_Q_SCR_01_0_DUAL                    0x0
#define GPIO_Q_SCR_01_0_SCR                     0
#define GPIO_Q_SCR_01_0_SCRREG                  0
#define GPIO_Q_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Q_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR7_SHIFT)
#define GPIO_Q_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR6_SHIFT)
#define GPIO_Q_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR5_SHIFT)
#define GPIO_Q_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR4_SHIFT)
#define GPIO_Q_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR3_SHIFT)
#define GPIO_Q_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR2_SHIFT)
#define GPIO_Q_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR1_SHIFT)
#define GPIO_Q_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR0_SHIFT)
#define GPIO_Q_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G7W_SHIFT)
#define GPIO_Q_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G6W_SHIFT)
#define GPIO_Q_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G5W_SHIFT)
#define GPIO_Q_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G4W_SHIFT)
#define GPIO_Q_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G3W_SHIFT)
#define GPIO_Q_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G2W_SHIFT)
#define GPIO_Q_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G1W_SHIFT)
#define GPIO_Q_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G0W_SHIFT)
#define GPIO_Q_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G7R_SHIFT)
#define GPIO_Q_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G6R_SHIFT)
#define GPIO_Q_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G5R_SHIFT)
#define GPIO_Q_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G4R_SHIFT)
#define GPIO_Q_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G3R_SHIFT)
#define GPIO_Q_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G2R_SHIFT)
#define GPIO_Q_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G1R_SHIFT)
#define GPIO_Q_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G0R_SHIFT)
#define GPIO_Q_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_02_0
#define GPIO_Q_VM_02_0                  MK_ADDR_CONST(0x20d0)
#define GPIO_Q_VM_02_0_SECURE                   0x0
#define GPIO_Q_VM_02_0_DUAL                     0x0
#define GPIO_Q_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_02_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM1_SHIFT)
#define GPIO_Q_VM_02_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Q_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Q_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM2_SHIFT)
#define GPIO_Q_VM_02_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Q_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Q_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Q_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM3_SHIFT)
#define GPIO_Q_VM_02_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Q_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Q_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Q_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM4_SHIFT)
#define GPIO_Q_VM_02_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Q_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Q_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM5_SHIFT)
#define GPIO_Q_VM_02_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Q_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Q_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Q_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM6_SHIFT)
#define GPIO_Q_VM_02_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Q_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Q_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Q_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM7_SHIFT)
#define GPIO_Q_VM_02_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Q_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Q_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Q_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM8_SHIFT)
#define GPIO_Q_VM_02_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Q_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Q_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_02_0
#define GPIO_Q_SCR_02_0                 MK_ADDR_CONST(0x20d4)
#define GPIO_Q_SCR_02_0_SECURE                  0x0
#define GPIO_Q_SCR_02_0_DUAL                    0x0
#define GPIO_Q_SCR_02_0_SCR                     0
#define GPIO_Q_SCR_02_0_SCRREG                  0
#define GPIO_Q_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Q_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR7_SHIFT)
#define GPIO_Q_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR6_SHIFT)
#define GPIO_Q_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR5_SHIFT)
#define GPIO_Q_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR4_SHIFT)
#define GPIO_Q_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR3_SHIFT)
#define GPIO_Q_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR2_SHIFT)
#define GPIO_Q_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR1_SHIFT)
#define GPIO_Q_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR0_SHIFT)
#define GPIO_Q_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G7W_SHIFT)
#define GPIO_Q_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G6W_SHIFT)
#define GPIO_Q_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G5W_SHIFT)
#define GPIO_Q_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G4W_SHIFT)
#define GPIO_Q_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G3W_SHIFT)
#define GPIO_Q_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G2W_SHIFT)
#define GPIO_Q_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G1W_SHIFT)
#define GPIO_Q_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G0W_SHIFT)
#define GPIO_Q_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G7R_SHIFT)
#define GPIO_Q_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G6R_SHIFT)
#define GPIO_Q_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G5R_SHIFT)
#define GPIO_Q_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G4R_SHIFT)
#define GPIO_Q_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G3R_SHIFT)
#define GPIO_Q_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G2R_SHIFT)
#define GPIO_Q_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G1R_SHIFT)
#define GPIO_Q_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G0R_SHIFT)
#define GPIO_Q_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_03_0
#define GPIO_Q_VM_03_0                  MK_ADDR_CONST(0x20d8)
#define GPIO_Q_VM_03_0_SECURE                   0x0
#define GPIO_Q_VM_03_0_DUAL                     0x0
#define GPIO_Q_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_03_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM1_SHIFT)
#define GPIO_Q_VM_03_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Q_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Q_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM2_SHIFT)
#define GPIO_Q_VM_03_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Q_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Q_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Q_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM3_SHIFT)
#define GPIO_Q_VM_03_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Q_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Q_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Q_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM4_SHIFT)
#define GPIO_Q_VM_03_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Q_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Q_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM5_SHIFT)
#define GPIO_Q_VM_03_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Q_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Q_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Q_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM6_SHIFT)
#define GPIO_Q_VM_03_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Q_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Q_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Q_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM7_SHIFT)
#define GPIO_Q_VM_03_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Q_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Q_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Q_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM8_SHIFT)
#define GPIO_Q_VM_03_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Q_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Q_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_03_0
#define GPIO_Q_SCR_03_0                 MK_ADDR_CONST(0x20dc)
#define GPIO_Q_SCR_03_0_SECURE                  0x0
#define GPIO_Q_SCR_03_0_DUAL                    0x0
#define GPIO_Q_SCR_03_0_SCR                     0
#define GPIO_Q_SCR_03_0_SCRREG                  0
#define GPIO_Q_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Q_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR7_SHIFT)
#define GPIO_Q_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR6_SHIFT)
#define GPIO_Q_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR5_SHIFT)
#define GPIO_Q_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR4_SHIFT)
#define GPIO_Q_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR3_SHIFT)
#define GPIO_Q_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR2_SHIFT)
#define GPIO_Q_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR1_SHIFT)
#define GPIO_Q_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR0_SHIFT)
#define GPIO_Q_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G7W_SHIFT)
#define GPIO_Q_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G6W_SHIFT)
#define GPIO_Q_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G5W_SHIFT)
#define GPIO_Q_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G4W_SHIFT)
#define GPIO_Q_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G3W_SHIFT)
#define GPIO_Q_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G2W_SHIFT)
#define GPIO_Q_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G1W_SHIFT)
#define GPIO_Q_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G0W_SHIFT)
#define GPIO_Q_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G7R_SHIFT)
#define GPIO_Q_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G6R_SHIFT)
#define GPIO_Q_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G5R_SHIFT)
#define GPIO_Q_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G4R_SHIFT)
#define GPIO_Q_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G3R_SHIFT)
#define GPIO_Q_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G2R_SHIFT)
#define GPIO_Q_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G1R_SHIFT)
#define GPIO_Q_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G0R_SHIFT)
#define GPIO_Q_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_04_0
#define GPIO_Q_VM_04_0                  MK_ADDR_CONST(0x20e0)
#define GPIO_Q_VM_04_0_SECURE                   0x0
#define GPIO_Q_VM_04_0_DUAL                     0x0
#define GPIO_Q_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_04_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM1_SHIFT)
#define GPIO_Q_VM_04_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Q_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Q_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM2_SHIFT)
#define GPIO_Q_VM_04_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Q_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Q_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Q_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM3_SHIFT)
#define GPIO_Q_VM_04_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Q_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Q_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Q_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM4_SHIFT)
#define GPIO_Q_VM_04_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Q_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Q_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM5_SHIFT)
#define GPIO_Q_VM_04_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Q_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Q_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Q_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM6_SHIFT)
#define GPIO_Q_VM_04_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Q_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Q_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Q_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM7_SHIFT)
#define GPIO_Q_VM_04_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Q_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Q_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Q_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM8_SHIFT)
#define GPIO_Q_VM_04_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Q_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Q_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_04_0
#define GPIO_Q_SCR_04_0                 MK_ADDR_CONST(0x20e4)
#define GPIO_Q_SCR_04_0_SECURE                  0x0
#define GPIO_Q_SCR_04_0_DUAL                    0x0
#define GPIO_Q_SCR_04_0_SCR                     0
#define GPIO_Q_SCR_04_0_SCRREG                  0
#define GPIO_Q_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Q_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR7_SHIFT)
#define GPIO_Q_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR6_SHIFT)
#define GPIO_Q_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR5_SHIFT)
#define GPIO_Q_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR4_SHIFT)
#define GPIO_Q_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR3_SHIFT)
#define GPIO_Q_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR2_SHIFT)
#define GPIO_Q_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR1_SHIFT)
#define GPIO_Q_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR0_SHIFT)
#define GPIO_Q_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G7W_SHIFT)
#define GPIO_Q_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G6W_SHIFT)
#define GPIO_Q_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G5W_SHIFT)
#define GPIO_Q_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G4W_SHIFT)
#define GPIO_Q_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G3W_SHIFT)
#define GPIO_Q_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G2W_SHIFT)
#define GPIO_Q_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G1W_SHIFT)
#define GPIO_Q_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G0W_SHIFT)
#define GPIO_Q_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G7R_SHIFT)
#define GPIO_Q_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G6R_SHIFT)
#define GPIO_Q_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G5R_SHIFT)
#define GPIO_Q_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G4R_SHIFT)
#define GPIO_Q_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G3R_SHIFT)
#define GPIO_Q_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G2R_SHIFT)
#define GPIO_Q_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G1R_SHIFT)
#define GPIO_Q_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G0R_SHIFT)
#define GPIO_Q_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_05_0
#define GPIO_Q_VM_05_0                  MK_ADDR_CONST(0x20e8)
#define GPIO_Q_VM_05_0_SECURE                   0x0
#define GPIO_Q_VM_05_0_DUAL                     0x0
#define GPIO_Q_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_05_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM1_SHIFT)
#define GPIO_Q_VM_05_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Q_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Q_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM2_SHIFT)
#define GPIO_Q_VM_05_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Q_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Q_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Q_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM3_SHIFT)
#define GPIO_Q_VM_05_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Q_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Q_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Q_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM4_SHIFT)
#define GPIO_Q_VM_05_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Q_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Q_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM5_SHIFT)
#define GPIO_Q_VM_05_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Q_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Q_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Q_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM6_SHIFT)
#define GPIO_Q_VM_05_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Q_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Q_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Q_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM7_SHIFT)
#define GPIO_Q_VM_05_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Q_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Q_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Q_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM8_SHIFT)
#define GPIO_Q_VM_05_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Q_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Q_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_05_0
#define GPIO_Q_SCR_05_0                 MK_ADDR_CONST(0x20ec)
#define GPIO_Q_SCR_05_0_SECURE                  0x0
#define GPIO_Q_SCR_05_0_DUAL                    0x0
#define GPIO_Q_SCR_05_0_SCR                     0
#define GPIO_Q_SCR_05_0_SCRREG                  0
#define GPIO_Q_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Q_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR7_SHIFT)
#define GPIO_Q_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR6_SHIFT)
#define GPIO_Q_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR5_SHIFT)
#define GPIO_Q_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR4_SHIFT)
#define GPIO_Q_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR3_SHIFT)
#define GPIO_Q_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR2_SHIFT)
#define GPIO_Q_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR1_SHIFT)
#define GPIO_Q_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR0_SHIFT)
#define GPIO_Q_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G7W_SHIFT)
#define GPIO_Q_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G6W_SHIFT)
#define GPIO_Q_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G5W_SHIFT)
#define GPIO_Q_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G4W_SHIFT)
#define GPIO_Q_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G3W_SHIFT)
#define GPIO_Q_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G2W_SHIFT)
#define GPIO_Q_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G1W_SHIFT)
#define GPIO_Q_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G0W_SHIFT)
#define GPIO_Q_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G7R_SHIFT)
#define GPIO_Q_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G6R_SHIFT)
#define GPIO_Q_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G5R_SHIFT)
#define GPIO_Q_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G4R_SHIFT)
#define GPIO_Q_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G3R_SHIFT)
#define GPIO_Q_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G2R_SHIFT)
#define GPIO_Q_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G1R_SHIFT)
#define GPIO_Q_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G0R_SHIFT)
#define GPIO_Q_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_06_0
#define GPIO_Q_VM_06_0                  MK_ADDR_CONST(0x20f0)
#define GPIO_Q_VM_06_0_SECURE                   0x0
#define GPIO_Q_VM_06_0_DUAL                     0x0
#define GPIO_Q_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_06_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_06_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM1_SHIFT)
#define GPIO_Q_VM_06_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Q_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Q_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM2_SHIFT)
#define GPIO_Q_VM_06_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Q_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Q_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Q_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM3_SHIFT)
#define GPIO_Q_VM_06_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Q_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Q_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Q_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM4_SHIFT)
#define GPIO_Q_VM_06_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Q_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Q_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM5_SHIFT)
#define GPIO_Q_VM_06_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Q_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Q_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Q_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM6_SHIFT)
#define GPIO_Q_VM_06_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Q_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Q_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Q_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM7_SHIFT)
#define GPIO_Q_VM_06_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Q_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Q_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Q_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM8_SHIFT)
#define GPIO_Q_VM_06_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Q_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Q_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_06_0
#define GPIO_Q_SCR_06_0                 MK_ADDR_CONST(0x20f4)
#define GPIO_Q_SCR_06_0_SECURE                  0x0
#define GPIO_Q_SCR_06_0_DUAL                    0x0
#define GPIO_Q_SCR_06_0_SCR                     0
#define GPIO_Q_SCR_06_0_SCRREG                  0
#define GPIO_Q_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Q_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR7_SHIFT)
#define GPIO_Q_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR6_SHIFT)
#define GPIO_Q_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR5_SHIFT)
#define GPIO_Q_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR4_SHIFT)
#define GPIO_Q_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR3_SHIFT)
#define GPIO_Q_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR2_SHIFT)
#define GPIO_Q_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR1_SHIFT)
#define GPIO_Q_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR0_SHIFT)
#define GPIO_Q_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G7W_SHIFT)
#define GPIO_Q_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G6W_SHIFT)
#define GPIO_Q_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G5W_SHIFT)
#define GPIO_Q_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G4W_SHIFT)
#define GPIO_Q_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G3W_SHIFT)
#define GPIO_Q_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G2W_SHIFT)
#define GPIO_Q_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G1W_SHIFT)
#define GPIO_Q_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G0W_SHIFT)
#define GPIO_Q_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G7R_SHIFT)
#define GPIO_Q_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G6R_SHIFT)
#define GPIO_Q_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G5R_SHIFT)
#define GPIO_Q_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G4R_SHIFT)
#define GPIO_Q_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G3R_SHIFT)
#define GPIO_Q_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G2R_SHIFT)
#define GPIO_Q_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G1R_SHIFT)
#define GPIO_Q_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G0R_SHIFT)
#define GPIO_Q_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_Q_VM_07_0
#define GPIO_Q_VM_07_0                  MK_ADDR_CONST(0x20f8)
#define GPIO_Q_VM_07_0_SECURE                   0x0
#define GPIO_Q_VM_07_0_DUAL                     0x0
#define GPIO_Q_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_07_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_Q_VM_07_0_WORD_COUNT                       0x1
#define GPIO_Q_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_Q_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM1_SHIFT)
#define GPIO_Q_VM_07_0_VM1_RANGE                        1:0
#define GPIO_Q_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_Q_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_Q_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM2_SHIFT)
#define GPIO_Q_VM_07_0_VM2_RANGE                        3:2
#define GPIO_Q_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_Q_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_Q_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_Q_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM3_SHIFT)
#define GPIO_Q_VM_07_0_VM3_RANGE                        5:4
#define GPIO_Q_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_Q_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_Q_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_Q_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM4_SHIFT)
#define GPIO_Q_VM_07_0_VM4_RANGE                        7:6
#define GPIO_Q_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_Q_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_Q_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM5_SHIFT)
#define GPIO_Q_VM_07_0_VM5_RANGE                        9:8
#define GPIO_Q_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_Q_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_Q_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_Q_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM6_SHIFT)
#define GPIO_Q_VM_07_0_VM6_RANGE                        11:10
#define GPIO_Q_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_Q_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_Q_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_Q_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM7_SHIFT)
#define GPIO_Q_VM_07_0_VM7_RANGE                        13:12
#define GPIO_Q_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_Q_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_Q_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_Q_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_Q_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM8_SHIFT)
#define GPIO_Q_VM_07_0_VM8_RANGE                        15:14
#define GPIO_Q_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_Q_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_Q_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_Q_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_Q_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_SCR_07_0
#define GPIO_Q_SCR_07_0                 MK_ADDR_CONST(0x20fc)
#define GPIO_Q_SCR_07_0_SECURE                  0x0
#define GPIO_Q_SCR_07_0_DUAL                    0x0
#define GPIO_Q_SCR_07_0_SCR                     0
#define GPIO_Q_SCR_07_0_SCRREG                  0
#define GPIO_Q_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_Q_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_Q_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_Q_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_Q_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_Q_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_Q_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_Q_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_Q_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_Q_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_Q_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_Q_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_Q_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_Q_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_Q_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_Q_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_Q_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_Q_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_Q_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_Q_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_Q_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR7_SHIFT)
#define GPIO_Q_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_Q_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_Q_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR6_SHIFT)
#define GPIO_Q_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_Q_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_Q_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR5_SHIFT)
#define GPIO_Q_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_Q_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_Q_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR4_SHIFT)
#define GPIO_Q_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_Q_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_Q_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR3_SHIFT)
#define GPIO_Q_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_Q_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_Q_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR2_SHIFT)
#define GPIO_Q_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_Q_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_Q_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR1_SHIFT)
#define GPIO_Q_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_Q_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_Q_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR0_SHIFT)
#define GPIO_Q_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_Q_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_Q_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G7W_SHIFT)
#define GPIO_Q_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_Q_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_Q_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G6W_SHIFT)
#define GPIO_Q_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_Q_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_Q_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G5W_SHIFT)
#define GPIO_Q_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_Q_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_Q_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G4W_SHIFT)
#define GPIO_Q_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_Q_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_Q_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G3W_SHIFT)
#define GPIO_Q_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_Q_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_Q_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G2W_SHIFT)
#define GPIO_Q_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_Q_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_Q_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G1W_SHIFT)
#define GPIO_Q_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_Q_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_Q_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G0W_SHIFT)
#define GPIO_Q_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_Q_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_Q_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G7R_SHIFT)
#define GPIO_Q_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_Q_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_Q_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G6R_SHIFT)
#define GPIO_Q_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_Q_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_Q_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G5R_SHIFT)
#define GPIO_Q_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_Q_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G4R_SHIFT)
#define GPIO_Q_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_Q_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_Q_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G3R_SHIFT)
#define GPIO_Q_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_Q_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_Q_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G2R_SHIFT)
#define GPIO_Q_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_Q_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_Q_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G1R_SHIFT)
#define GPIO_Q_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_Q_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_Q_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_Q_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G0R_SHIFT)
#define GPIO_Q_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_Q_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_Q_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_Q_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_R_VM_00_0
#define GPIO_R_VM_00_0                  MK_ADDR_CONST(0x2100)
#define GPIO_R_VM_00_0_SECURE                   0x0
#define GPIO_R_VM_00_0_DUAL                     0x0
#define GPIO_R_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_00_0_WORD_COUNT                       0x1
#define GPIO_R_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM1_SHIFT)
#define GPIO_R_VM_00_0_VM1_RANGE                        1:0
#define GPIO_R_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_R_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_R_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM2_SHIFT)
#define GPIO_R_VM_00_0_VM2_RANGE                        3:2
#define GPIO_R_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_R_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_R_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_R_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM3_SHIFT)
#define GPIO_R_VM_00_0_VM3_RANGE                        5:4
#define GPIO_R_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_R_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_R_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM4_SHIFT)
#define GPIO_R_VM_00_0_VM4_RANGE                        7:6
#define GPIO_R_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_R_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_R_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_R_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM5_SHIFT)
#define GPIO_R_VM_00_0_VM5_RANGE                        9:8
#define GPIO_R_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_R_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_R_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_R_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM6_SHIFT)
#define GPIO_R_VM_00_0_VM6_RANGE                        11:10
#define GPIO_R_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_R_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_R_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_R_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM7_SHIFT)
#define GPIO_R_VM_00_0_VM7_RANGE                        13:12
#define GPIO_R_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_R_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_R_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_R_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM8_SHIFT)
#define GPIO_R_VM_00_0_VM8_RANGE                        15:14
#define GPIO_R_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_R_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_R_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_00_0
#define GPIO_R_SCR_00_0                 MK_ADDR_CONST(0x2104)
#define GPIO_R_SCR_00_0_SECURE                  0x0
#define GPIO_R_SCR_00_0_DUAL                    0x0
#define GPIO_R_SCR_00_0_SCR                     0
#define GPIO_R_SCR_00_0_SCRREG                  0
#define GPIO_R_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_R_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_R_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_R_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_R_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_R_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_R_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_R_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_R_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR7_SHIFT)
#define GPIO_R_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_R_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR6_SHIFT)
#define GPIO_R_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_R_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR5_SHIFT)
#define GPIO_R_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_R_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR4_SHIFT)
#define GPIO_R_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_R_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR3_SHIFT)
#define GPIO_R_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_R_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR2_SHIFT)
#define GPIO_R_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_R_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR1_SHIFT)
#define GPIO_R_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_R_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR0_SHIFT)
#define GPIO_R_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_R_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G7W_SHIFT)
#define GPIO_R_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_R_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G6W_SHIFT)
#define GPIO_R_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_R_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G5W_SHIFT)
#define GPIO_R_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_R_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G4W_SHIFT)
#define GPIO_R_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_R_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G3W_SHIFT)
#define GPIO_R_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_R_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G2W_SHIFT)
#define GPIO_R_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_R_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G1W_SHIFT)
#define GPIO_R_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_R_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G0W_SHIFT)
#define GPIO_R_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_R_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G7R_SHIFT)
#define GPIO_R_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_R_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G6R_SHIFT)
#define GPIO_R_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G5R_SHIFT)
#define GPIO_R_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_R_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G4R_SHIFT)
#define GPIO_R_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_R_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G3R_SHIFT)
#define GPIO_R_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_R_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G2R_SHIFT)
#define GPIO_R_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_R_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G1R_SHIFT)
#define GPIO_R_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G0R_SHIFT)
#define GPIO_R_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_R_VM_01_0
#define GPIO_R_VM_01_0                  MK_ADDR_CONST(0x2108)
#define GPIO_R_VM_01_0_SECURE                   0x0
#define GPIO_R_VM_01_0_DUAL                     0x0
#define GPIO_R_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_01_0_WORD_COUNT                       0x1
#define GPIO_R_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM1_SHIFT)
#define GPIO_R_VM_01_0_VM1_RANGE                        1:0
#define GPIO_R_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_R_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_R_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM2_SHIFT)
#define GPIO_R_VM_01_0_VM2_RANGE                        3:2
#define GPIO_R_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_R_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_R_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_R_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM3_SHIFT)
#define GPIO_R_VM_01_0_VM3_RANGE                        5:4
#define GPIO_R_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_R_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_R_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM4_SHIFT)
#define GPIO_R_VM_01_0_VM4_RANGE                        7:6
#define GPIO_R_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_R_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_R_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_R_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM5_SHIFT)
#define GPIO_R_VM_01_0_VM5_RANGE                        9:8
#define GPIO_R_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_R_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_R_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_R_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM6_SHIFT)
#define GPIO_R_VM_01_0_VM6_RANGE                        11:10
#define GPIO_R_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_R_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_R_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_R_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM7_SHIFT)
#define GPIO_R_VM_01_0_VM7_RANGE                        13:12
#define GPIO_R_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_R_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_R_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_R_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM8_SHIFT)
#define GPIO_R_VM_01_0_VM8_RANGE                        15:14
#define GPIO_R_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_R_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_R_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_01_0
#define GPIO_R_SCR_01_0                 MK_ADDR_CONST(0x210c)
#define GPIO_R_SCR_01_0_SECURE                  0x0
#define GPIO_R_SCR_01_0_DUAL                    0x0
#define GPIO_R_SCR_01_0_SCR                     0
#define GPIO_R_SCR_01_0_SCRREG                  0
#define GPIO_R_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_R_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_R_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_R_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_R_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_R_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_R_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_R_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_R_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR7_SHIFT)
#define GPIO_R_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_R_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR6_SHIFT)
#define GPIO_R_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_R_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR5_SHIFT)
#define GPIO_R_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_R_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR4_SHIFT)
#define GPIO_R_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_R_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR3_SHIFT)
#define GPIO_R_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_R_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR2_SHIFT)
#define GPIO_R_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_R_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR1_SHIFT)
#define GPIO_R_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_R_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR0_SHIFT)
#define GPIO_R_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_R_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G7W_SHIFT)
#define GPIO_R_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_R_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G6W_SHIFT)
#define GPIO_R_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_R_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G5W_SHIFT)
#define GPIO_R_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_R_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G4W_SHIFT)
#define GPIO_R_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_R_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G3W_SHIFT)
#define GPIO_R_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_R_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G2W_SHIFT)
#define GPIO_R_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_R_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G1W_SHIFT)
#define GPIO_R_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_R_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G0W_SHIFT)
#define GPIO_R_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_R_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G7R_SHIFT)
#define GPIO_R_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_R_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G6R_SHIFT)
#define GPIO_R_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G5R_SHIFT)
#define GPIO_R_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_R_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G4R_SHIFT)
#define GPIO_R_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_R_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G3R_SHIFT)
#define GPIO_R_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_R_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G2R_SHIFT)
#define GPIO_R_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_R_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G1R_SHIFT)
#define GPIO_R_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G0R_SHIFT)
#define GPIO_R_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_R_VM_02_0
#define GPIO_R_VM_02_0                  MK_ADDR_CONST(0x2110)
#define GPIO_R_VM_02_0_SECURE                   0x0
#define GPIO_R_VM_02_0_DUAL                     0x0
#define GPIO_R_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_02_0_WORD_COUNT                       0x1
#define GPIO_R_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM1_SHIFT)
#define GPIO_R_VM_02_0_VM1_RANGE                        1:0
#define GPIO_R_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_R_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_R_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM2_SHIFT)
#define GPIO_R_VM_02_0_VM2_RANGE                        3:2
#define GPIO_R_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_R_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_R_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_R_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM3_SHIFT)
#define GPIO_R_VM_02_0_VM3_RANGE                        5:4
#define GPIO_R_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_R_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_R_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM4_SHIFT)
#define GPIO_R_VM_02_0_VM4_RANGE                        7:6
#define GPIO_R_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_R_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_R_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_R_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM5_SHIFT)
#define GPIO_R_VM_02_0_VM5_RANGE                        9:8
#define GPIO_R_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_R_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_R_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_R_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM6_SHIFT)
#define GPIO_R_VM_02_0_VM6_RANGE                        11:10
#define GPIO_R_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_R_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_R_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_R_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM7_SHIFT)
#define GPIO_R_VM_02_0_VM7_RANGE                        13:12
#define GPIO_R_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_R_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_R_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_R_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM8_SHIFT)
#define GPIO_R_VM_02_0_VM8_RANGE                        15:14
#define GPIO_R_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_R_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_R_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_02_0
#define GPIO_R_SCR_02_0                 MK_ADDR_CONST(0x2114)
#define GPIO_R_SCR_02_0_SECURE                  0x0
#define GPIO_R_SCR_02_0_DUAL                    0x0
#define GPIO_R_SCR_02_0_SCR                     0
#define GPIO_R_SCR_02_0_SCRREG                  0
#define GPIO_R_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_R_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_R_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_R_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_R_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_R_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_R_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_R_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_R_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR7_SHIFT)
#define GPIO_R_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_R_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR6_SHIFT)
#define GPIO_R_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_R_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR5_SHIFT)
#define GPIO_R_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_R_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR4_SHIFT)
#define GPIO_R_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_R_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR3_SHIFT)
#define GPIO_R_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_R_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR2_SHIFT)
#define GPIO_R_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_R_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR1_SHIFT)
#define GPIO_R_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_R_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR0_SHIFT)
#define GPIO_R_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_R_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G7W_SHIFT)
#define GPIO_R_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_R_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G6W_SHIFT)
#define GPIO_R_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_R_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G5W_SHIFT)
#define GPIO_R_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_R_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G4W_SHIFT)
#define GPIO_R_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_R_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G3W_SHIFT)
#define GPIO_R_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_R_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G2W_SHIFT)
#define GPIO_R_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_R_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G1W_SHIFT)
#define GPIO_R_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_R_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G0W_SHIFT)
#define GPIO_R_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_R_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G7R_SHIFT)
#define GPIO_R_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_R_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G6R_SHIFT)
#define GPIO_R_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G5R_SHIFT)
#define GPIO_R_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_R_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G4R_SHIFT)
#define GPIO_R_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_R_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G3R_SHIFT)
#define GPIO_R_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_R_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G2R_SHIFT)
#define GPIO_R_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_R_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G1R_SHIFT)
#define GPIO_R_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G0R_SHIFT)
#define GPIO_R_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_R_VM_03_0
#define GPIO_R_VM_03_0                  MK_ADDR_CONST(0x2118)
#define GPIO_R_VM_03_0_SECURE                   0x0
#define GPIO_R_VM_03_0_DUAL                     0x0
#define GPIO_R_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_03_0_WORD_COUNT                       0x1
#define GPIO_R_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM1_SHIFT)
#define GPIO_R_VM_03_0_VM1_RANGE                        1:0
#define GPIO_R_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_R_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_R_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM2_SHIFT)
#define GPIO_R_VM_03_0_VM2_RANGE                        3:2
#define GPIO_R_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_R_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_R_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_R_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM3_SHIFT)
#define GPIO_R_VM_03_0_VM3_RANGE                        5:4
#define GPIO_R_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_R_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_R_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM4_SHIFT)
#define GPIO_R_VM_03_0_VM4_RANGE                        7:6
#define GPIO_R_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_R_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_R_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_R_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM5_SHIFT)
#define GPIO_R_VM_03_0_VM5_RANGE                        9:8
#define GPIO_R_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_R_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_R_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_R_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM6_SHIFT)
#define GPIO_R_VM_03_0_VM6_RANGE                        11:10
#define GPIO_R_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_R_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_R_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_R_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM7_SHIFT)
#define GPIO_R_VM_03_0_VM7_RANGE                        13:12
#define GPIO_R_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_R_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_R_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_R_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM8_SHIFT)
#define GPIO_R_VM_03_0_VM8_RANGE                        15:14
#define GPIO_R_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_R_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_R_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_03_0
#define GPIO_R_SCR_03_0                 MK_ADDR_CONST(0x211c)
#define GPIO_R_SCR_03_0_SECURE                  0x0
#define GPIO_R_SCR_03_0_DUAL                    0x0
#define GPIO_R_SCR_03_0_SCR                     0
#define GPIO_R_SCR_03_0_SCRREG                  0
#define GPIO_R_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_R_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_R_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_R_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_R_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_R_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_R_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_R_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_R_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR7_SHIFT)
#define GPIO_R_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_R_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR6_SHIFT)
#define GPIO_R_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_R_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR5_SHIFT)
#define GPIO_R_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_R_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR4_SHIFT)
#define GPIO_R_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_R_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR3_SHIFT)
#define GPIO_R_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_R_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR2_SHIFT)
#define GPIO_R_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_R_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR1_SHIFT)
#define GPIO_R_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_R_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR0_SHIFT)
#define GPIO_R_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_R_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G7W_SHIFT)
#define GPIO_R_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_R_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G6W_SHIFT)
#define GPIO_R_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_R_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G5W_SHIFT)
#define GPIO_R_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_R_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G4W_SHIFT)
#define GPIO_R_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_R_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G3W_SHIFT)
#define GPIO_R_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_R_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G2W_SHIFT)
#define GPIO_R_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_R_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G1W_SHIFT)
#define GPIO_R_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_R_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G0W_SHIFT)
#define GPIO_R_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_R_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G7R_SHIFT)
#define GPIO_R_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_R_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G6R_SHIFT)
#define GPIO_R_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G5R_SHIFT)
#define GPIO_R_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_R_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G4R_SHIFT)
#define GPIO_R_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_R_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G3R_SHIFT)
#define GPIO_R_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_R_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G2R_SHIFT)
#define GPIO_R_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_R_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G1R_SHIFT)
#define GPIO_R_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G0R_SHIFT)
#define GPIO_R_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_R_VM_04_0
#define GPIO_R_VM_04_0                  MK_ADDR_CONST(0x2120)
#define GPIO_R_VM_04_0_SECURE                   0x0
#define GPIO_R_VM_04_0_DUAL                     0x0
#define GPIO_R_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_04_0_WORD_COUNT                       0x1
#define GPIO_R_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM1_SHIFT)
#define GPIO_R_VM_04_0_VM1_RANGE                        1:0
#define GPIO_R_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_R_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_R_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM2_SHIFT)
#define GPIO_R_VM_04_0_VM2_RANGE                        3:2
#define GPIO_R_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_R_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_R_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_R_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM3_SHIFT)
#define GPIO_R_VM_04_0_VM3_RANGE                        5:4
#define GPIO_R_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_R_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_R_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM4_SHIFT)
#define GPIO_R_VM_04_0_VM4_RANGE                        7:6
#define GPIO_R_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_R_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_R_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_R_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM5_SHIFT)
#define GPIO_R_VM_04_0_VM5_RANGE                        9:8
#define GPIO_R_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_R_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_R_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_R_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM6_SHIFT)
#define GPIO_R_VM_04_0_VM6_RANGE                        11:10
#define GPIO_R_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_R_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_R_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_R_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM7_SHIFT)
#define GPIO_R_VM_04_0_VM7_RANGE                        13:12
#define GPIO_R_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_R_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_R_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_R_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM8_SHIFT)
#define GPIO_R_VM_04_0_VM8_RANGE                        15:14
#define GPIO_R_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_R_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_R_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_04_0
#define GPIO_R_SCR_04_0                 MK_ADDR_CONST(0x2124)
#define GPIO_R_SCR_04_0_SECURE                  0x0
#define GPIO_R_SCR_04_0_DUAL                    0x0
#define GPIO_R_SCR_04_0_SCR                     0
#define GPIO_R_SCR_04_0_SCRREG                  0
#define GPIO_R_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_R_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_R_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_R_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_R_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_R_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_R_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_R_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_R_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR7_SHIFT)
#define GPIO_R_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_R_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR6_SHIFT)
#define GPIO_R_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_R_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR5_SHIFT)
#define GPIO_R_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_R_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR4_SHIFT)
#define GPIO_R_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_R_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR3_SHIFT)
#define GPIO_R_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_R_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR2_SHIFT)
#define GPIO_R_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_R_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR1_SHIFT)
#define GPIO_R_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_R_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR0_SHIFT)
#define GPIO_R_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_R_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G7W_SHIFT)
#define GPIO_R_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_R_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G6W_SHIFT)
#define GPIO_R_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_R_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G5W_SHIFT)
#define GPIO_R_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_R_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G4W_SHIFT)
#define GPIO_R_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_R_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G3W_SHIFT)
#define GPIO_R_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_R_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G2W_SHIFT)
#define GPIO_R_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_R_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G1W_SHIFT)
#define GPIO_R_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_R_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G0W_SHIFT)
#define GPIO_R_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_R_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G7R_SHIFT)
#define GPIO_R_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_R_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G6R_SHIFT)
#define GPIO_R_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G5R_SHIFT)
#define GPIO_R_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_R_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G4R_SHIFT)
#define GPIO_R_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_R_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G3R_SHIFT)
#define GPIO_R_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_R_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G2R_SHIFT)
#define GPIO_R_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_R_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G1R_SHIFT)
#define GPIO_R_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G0R_SHIFT)
#define GPIO_R_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_R_VM_05_0
#define GPIO_R_VM_05_0                  MK_ADDR_CONST(0x2128)
#define GPIO_R_VM_05_0_SECURE                   0x0
#define GPIO_R_VM_05_0_DUAL                     0x0
#define GPIO_R_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
#define GPIO_R_VM_05_0_WORD_COUNT                       0x1
#define GPIO_R_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_R_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM1_SHIFT)
#define GPIO_R_VM_05_0_VM1_RANGE                        1:0
#define GPIO_R_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_R_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_R_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM2_SHIFT)
#define GPIO_R_VM_05_0_VM2_RANGE                        3:2
#define GPIO_R_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_R_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_R_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_R_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM3_SHIFT)
#define GPIO_R_VM_05_0_VM3_RANGE                        5:4
#define GPIO_R_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_R_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_R_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM4_SHIFT)
#define GPIO_R_VM_05_0_VM4_RANGE                        7:6
#define GPIO_R_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_R_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_R_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_R_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM5_SHIFT)
#define GPIO_R_VM_05_0_VM5_RANGE                        9:8
#define GPIO_R_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_R_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_R_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_R_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM6_SHIFT)
#define GPIO_R_VM_05_0_VM6_RANGE                        11:10
#define GPIO_R_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_R_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_R_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_R_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM7_SHIFT)
#define GPIO_R_VM_05_0_VM7_RANGE                        13:12
#define GPIO_R_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_R_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_R_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_R_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_R_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM8_SHIFT)
#define GPIO_R_VM_05_0_VM8_RANGE                        15:14
#define GPIO_R_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_R_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_R_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_R_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_R_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_SCR_05_0
#define GPIO_R_SCR_05_0                 MK_ADDR_CONST(0x212c)
#define GPIO_R_SCR_05_0_SECURE                  0x0
#define GPIO_R_SCR_05_0_DUAL                    0x0
#define GPIO_R_SCR_05_0_SCR                     0
#define GPIO_R_SCR_05_0_SCRREG                  0
#define GPIO_R_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_R_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_R_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_R_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_R_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_R_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_R_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_R_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_R_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_R_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_R_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_R_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_R_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_R_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_R_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_R_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_R_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_R_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_R_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_R_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_R_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_R_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_R_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_R_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR7_SHIFT)
#define GPIO_R_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_R_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_R_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_R_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR6_SHIFT)
#define GPIO_R_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_R_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_R_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_R_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR5_SHIFT)
#define GPIO_R_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_R_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_R_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_R_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR4_SHIFT)
#define GPIO_R_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_R_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_R_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_R_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR3_SHIFT)
#define GPIO_R_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_R_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_R_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_R_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR2_SHIFT)
#define GPIO_R_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_R_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_R_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_R_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR1_SHIFT)
#define GPIO_R_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_R_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_R_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_R_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR0_SHIFT)
#define GPIO_R_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_R_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_R_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_R_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G7W_SHIFT)
#define GPIO_R_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_R_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_R_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_R_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G6W_SHIFT)
#define GPIO_R_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_R_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_R_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_R_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G5W_SHIFT)
#define GPIO_R_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_R_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_R_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_R_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G4W_SHIFT)
#define GPIO_R_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_R_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_R_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_R_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G3W_SHIFT)
#define GPIO_R_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_R_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_R_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_R_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G2W_SHIFT)
#define GPIO_R_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_R_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_R_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_R_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G1W_SHIFT)
#define GPIO_R_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_R_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_R_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_R_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G0W_SHIFT)
#define GPIO_R_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_R_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_R_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_R_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G7R_SHIFT)
#define GPIO_R_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_R_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_R_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_R_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G6R_SHIFT)
#define GPIO_R_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_R_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_R_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G5R_SHIFT)
#define GPIO_R_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_R_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_R_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G4R_SHIFT)
#define GPIO_R_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_R_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_R_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_R_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G3R_SHIFT)
#define GPIO_R_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_R_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_R_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_R_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G2R_SHIFT)
#define GPIO_R_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_R_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_R_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_R_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G1R_SHIFT)
#define GPIO_R_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_R_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_R_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_R_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G0R_SHIFT)
#define GPIO_R_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_R_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_R_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_R_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x2130

// Reserved address 0x2134

// Reserved address 0x2138

// Reserved address 0x213c

// Register GPIO_CTL2_VM_SCR_0
#define GPIO_CTL2_VM_SCR_0                      MK_ADDR_CONST(0x2800)
#define GPIO_CTL2_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL2_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL2_VM_SCR_0_SCR                  0
#define GPIO_CTL2_VM_SCR_0_SCRREG                       0
#define GPIO_CTL2_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL2_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL2_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL2_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL2_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define GPIO_CTL2_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL2_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL2_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL2_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define GPIO_CTL2_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL2_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL2_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL2_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define GPIO_CTL2_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL2_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL2_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL2_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define GPIO_CTL2_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL2_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL2_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL2_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define GPIO_CTL2_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL2_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL2_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL2_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define GPIO_CTL2_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL2_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL2_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL2_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define GPIO_CTL2_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL2_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL2_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL2_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define GPIO_CTL2_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL2_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL2_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL2_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define GPIO_CTL2_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL2_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL2_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL2_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define GPIO_CTL2_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL2_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL2_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL2_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define GPIO_CTL2_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL2_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL2_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL2_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define GPIO_CTL2_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL2_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL2_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL2_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define GPIO_CTL2_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL2_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL2_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL2_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define GPIO_CTL2_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL2_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL2_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL2_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define GPIO_CTL2_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL2_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL2_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL2_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define GPIO_CTL2_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL2_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL2_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL2_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define GPIO_CTL2_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL2_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL2_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL2_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define GPIO_CTL2_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL2_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL2_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL2_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define GPIO_CTL2_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL2_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL2_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL2_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define GPIO_CTL2_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL2_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL2_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL2_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define GPIO_CTL2_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL2_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL2_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL2_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_CTL2_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL2_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL2_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL2_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define GPIO_CTL2_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL2_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL2_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL2_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL2_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CTL2_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL2_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL2_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL2_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL2_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL2_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x2804)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL2_INTERRUPT_STATUS_VM_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x2808)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_CTL2_SCR_0
#define GPIO_CTL2_SCR_0                 MK_ADDR_CONST(0x280c)
#define GPIO_CTL2_SCR_0_SECURE                  0x0
#define GPIO_CTL2_SCR_0_DUAL                    0x0
#define GPIO_CTL2_SCR_0_SCR                     0
#define GPIO_CTL2_SCR_0_SCRREG                  0
#define GPIO_CTL2_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL2_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL2_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_CTL2_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL2_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL2_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL2_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_CTL2_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL2_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL2_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL2_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_CTL2_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL2_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL2_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL2_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL2_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_CTL2_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL2_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL2_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL2_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_CTL2_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_CTL2_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL2_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_CTL2_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_CTL2_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR7_SHIFT)
#define GPIO_CTL2_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL2_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL2_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL2_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_CTL2_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR6_SHIFT)
#define GPIO_CTL2_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL2_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL2_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL2_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_CTL2_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR5_SHIFT)
#define GPIO_CTL2_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL2_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL2_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL2_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_CTL2_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR4_SHIFT)
#define GPIO_CTL2_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL2_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL2_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL2_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_CTL2_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR3_SHIFT)
#define GPIO_CTL2_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL2_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL2_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL2_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_CTL2_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR2_SHIFT)
#define GPIO_CTL2_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL2_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL2_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL2_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_CTL2_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR1_SHIFT)
#define GPIO_CTL2_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL2_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL2_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL2_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_CTL2_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR0_SHIFT)
#define GPIO_CTL2_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL2_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL2_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL2_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_CTL2_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G7W_SHIFT)
#define GPIO_CTL2_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL2_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL2_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL2_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_CTL2_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G6W_SHIFT)
#define GPIO_CTL2_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL2_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL2_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL2_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_CTL2_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G5W_SHIFT)
#define GPIO_CTL2_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL2_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL2_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL2_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_CTL2_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G4W_SHIFT)
#define GPIO_CTL2_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL2_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL2_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL2_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_CTL2_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G3W_SHIFT)
#define GPIO_CTL2_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL2_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL2_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL2_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_CTL2_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G2W_SHIFT)
#define GPIO_CTL2_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL2_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL2_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL2_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_CTL2_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G1W_SHIFT)
#define GPIO_CTL2_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL2_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL2_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL2_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_CTL2_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G0W_SHIFT)
#define GPIO_CTL2_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL2_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL2_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL2_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_CTL2_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G7R_SHIFT)
#define GPIO_CTL2_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL2_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL2_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL2_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_CTL2_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G6R_SHIFT)
#define GPIO_CTL2_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL2_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL2_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL2_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_CTL2_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G5R_SHIFT)
#define GPIO_CTL2_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL2_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL2_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL2_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_CTL2_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G4R_SHIFT)
#define GPIO_CTL2_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL2_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL2_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL2_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_CTL2_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G3R_SHIFT)
#define GPIO_CTL2_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL2_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL2_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL2_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_CTL2_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G2R_SHIFT)
#define GPIO_CTL2_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL2_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL2_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL2_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_CTL2_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G1R_SHIFT)
#define GPIO_CTL2_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL2_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL2_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL2_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL2_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CTL2_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G0R_SHIFT)
#define GPIO_CTL2_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL2_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL2_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL2_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL2_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL2_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CTL2_ICG_EN_OVERRIDE_0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x2810)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_M_INT0_ROUTE_MAPPING_0
#define GPIO_M_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2814)
#define GPIO_M_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_M_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_M_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_M_INT1_ROUTE_MAPPING_0
#define GPIO_M_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2818)
#define GPIO_M_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_M_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_M_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_M_INT2_ROUTE_MAPPING_0
#define GPIO_M_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x281c)
#define GPIO_M_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_M_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_M_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_M_INT3_ROUTE_MAPPING_0
#define GPIO_M_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2820)
#define GPIO_M_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_M_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_M_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_M_INT4_ROUTE_MAPPING_0
#define GPIO_M_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2824)
#define GPIO_M_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_M_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_M_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_M_INT5_ROUTE_MAPPING_0
#define GPIO_M_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2828)
#define GPIO_M_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_M_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_M_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_M_INT6_ROUTE_MAPPING_0
#define GPIO_M_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x282c)
#define GPIO_M_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_M_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_M_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_M_INT7_ROUTE_MAPPING_0
#define GPIO_M_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2830)
#define GPIO_M_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_M_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_M_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_M_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_M_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_M_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_M_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_N_INT0_ROUTE_MAPPING_0
#define GPIO_N_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2834)
#define GPIO_N_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_N_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_N_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_N_INT1_ROUTE_MAPPING_0
#define GPIO_N_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2838)
#define GPIO_N_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_N_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_N_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_N_INT2_ROUTE_MAPPING_0
#define GPIO_N_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x283c)
#define GPIO_N_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_N_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_N_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_N_INT3_ROUTE_MAPPING_0
#define GPIO_N_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2840)
#define GPIO_N_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_N_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_N_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_N_INT4_ROUTE_MAPPING_0
#define GPIO_N_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2844)
#define GPIO_N_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_N_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_N_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_N_INT5_ROUTE_MAPPING_0
#define GPIO_N_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2848)
#define GPIO_N_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_N_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_N_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_N_INT6_ROUTE_MAPPING_0
#define GPIO_N_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x284c)
#define GPIO_N_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_N_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_N_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_N_INT7_ROUTE_MAPPING_0
#define GPIO_N_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2850)
#define GPIO_N_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_N_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_N_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_N_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_N_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_N_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_N_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_P_INT0_ROUTE_MAPPING_0
#define GPIO_P_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2854)
#define GPIO_P_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_P_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_P_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_P_INT1_ROUTE_MAPPING_0
#define GPIO_P_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2858)
#define GPIO_P_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_P_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_P_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_P_INT2_ROUTE_MAPPING_0
#define GPIO_P_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x285c)
#define GPIO_P_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_P_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_P_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_P_INT3_ROUTE_MAPPING_0
#define GPIO_P_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2860)
#define GPIO_P_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_P_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_P_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_P_INT4_ROUTE_MAPPING_0
#define GPIO_P_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2864)
#define GPIO_P_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_P_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_P_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_P_INT5_ROUTE_MAPPING_0
#define GPIO_P_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2868)
#define GPIO_P_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_P_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_P_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_P_INT6_ROUTE_MAPPING_0
#define GPIO_P_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x286c)
#define GPIO_P_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_P_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_P_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_P_INT7_ROUTE_MAPPING_0
#define GPIO_P_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2870)
#define GPIO_P_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_P_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_P_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_P_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_P_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_P_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_P_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Q_INT0_ROUTE_MAPPING_0
#define GPIO_Q_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2874)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Q_INT1_ROUTE_MAPPING_0
#define GPIO_Q_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2878)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Q_INT2_ROUTE_MAPPING_0
#define GPIO_Q_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x287c)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Q_INT3_ROUTE_MAPPING_0
#define GPIO_Q_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2880)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Q_INT4_ROUTE_MAPPING_0
#define GPIO_Q_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2884)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Q_INT5_ROUTE_MAPPING_0
#define GPIO_Q_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2888)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Q_INT6_ROUTE_MAPPING_0
#define GPIO_Q_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x288c)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_Q_INT7_ROUTE_MAPPING_0
#define GPIO_Q_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2890)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_Q_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_R_INT0_ROUTE_MAPPING_0
#define GPIO_R_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2894)
#define GPIO_R_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_R_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_R_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_R_INT1_ROUTE_MAPPING_0
#define GPIO_R_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2898)
#define GPIO_R_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_R_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_R_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_R_INT2_ROUTE_MAPPING_0
#define GPIO_R_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x289c)
#define GPIO_R_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_R_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_R_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_R_INT3_ROUTE_MAPPING_0
#define GPIO_R_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28a0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_R_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_R_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_R_INT4_ROUTE_MAPPING_0
#define GPIO_R_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28a4)
#define GPIO_R_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_R_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_R_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_R_INT5_ROUTE_MAPPING_0
#define GPIO_R_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28a8)
#define GPIO_R_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_R_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_R_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_R_INT6_ROUTE_MAPPING_0
#define GPIO_R_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28ac)
#define GPIO_R_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_R_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_R_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_R_INT7_ROUTE_MAPPING_0
#define GPIO_R_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28b0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_R_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_R_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
#define GPIO_R_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
#define GPIO_R_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_R_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_R_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL2_SPARE_0
#define GPIO_CTL2_SPARE_0                       MK_ADDR_CONST(0x28b4)
#define GPIO_CTL2_SPARE_0_SECURE                        0x0
#define GPIO_CTL2_SPARE_0_DUAL                  0x0
#define GPIO_CTL2_SPARE_0_SCR                   0
#define GPIO_CTL2_SPARE_0_SCRREG                        0
#define GPIO_CTL2_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL2_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL2_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL2_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL2_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL2_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL2_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL2_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL2_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL2_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL2_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_K_VM_00_0
#define GPIO_K_VM_00_0                  MK_ADDR_CONST(0x3000)
#define GPIO_K_VM_00_0_SECURE                   0x0
#define GPIO_K_VM_00_0_DUAL                     0x0
#define GPIO_K_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_00_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_00_0_WORD_COUNT                       0x1
#define GPIO_K_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM1_SHIFT)
#define GPIO_K_VM_00_0_VM1_RANGE                        1:0
#define GPIO_K_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_K_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_K_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM2_SHIFT)
#define GPIO_K_VM_00_0_VM2_RANGE                        3:2
#define GPIO_K_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_K_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_K_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_K_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM3_SHIFT)
#define GPIO_K_VM_00_0_VM3_RANGE                        5:4
#define GPIO_K_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_K_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_K_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_K_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM4_SHIFT)
#define GPIO_K_VM_00_0_VM4_RANGE                        7:6
#define GPIO_K_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_K_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_K_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM5_SHIFT)
#define GPIO_K_VM_00_0_VM5_RANGE                        9:8
#define GPIO_K_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_K_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_K_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_K_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM6_SHIFT)
#define GPIO_K_VM_00_0_VM6_RANGE                        11:10
#define GPIO_K_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_K_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_K_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_K_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM7_SHIFT)
#define GPIO_K_VM_00_0_VM7_RANGE                        13:12
#define GPIO_K_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_K_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_K_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_K_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM8_SHIFT)
#define GPIO_K_VM_00_0_VM8_RANGE                        15:14
#define GPIO_K_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_K_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_K_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_00_0
#define GPIO_K_SCR_00_0                 MK_ADDR_CONST(0x3004)
#define GPIO_K_SCR_00_0_SECURE                  0x0
#define GPIO_K_SCR_00_0_DUAL                    0x0
#define GPIO_K_SCR_00_0_SCR                     0
#define GPIO_K_SCR_00_0_SCRREG                  0
#define GPIO_K_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_K_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_K_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_K_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_K_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_K_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_K_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_K_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_K_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR7_SHIFT)
#define GPIO_K_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_K_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR6_SHIFT)
#define GPIO_K_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_K_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR5_SHIFT)
#define GPIO_K_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_K_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR4_SHIFT)
#define GPIO_K_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_K_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR3_SHIFT)
#define GPIO_K_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_K_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR2_SHIFT)
#define GPIO_K_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_K_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR1_SHIFT)
#define GPIO_K_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_K_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR0_SHIFT)
#define GPIO_K_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_K_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G7W_SHIFT)
#define GPIO_K_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_K_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G6W_SHIFT)
#define GPIO_K_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_K_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G5W_SHIFT)
#define GPIO_K_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_K_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G4W_SHIFT)
#define GPIO_K_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_K_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G3W_SHIFT)
#define GPIO_K_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_K_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G2W_SHIFT)
#define GPIO_K_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_K_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G1W_SHIFT)
#define GPIO_K_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_K_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G0W_SHIFT)
#define GPIO_K_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_K_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G7R_SHIFT)
#define GPIO_K_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_K_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G6R_SHIFT)
#define GPIO_K_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G5R_SHIFT)
#define GPIO_K_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_K_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G4R_SHIFT)
#define GPIO_K_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_K_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G3R_SHIFT)
#define GPIO_K_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_K_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G2R_SHIFT)
#define GPIO_K_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_K_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G1R_SHIFT)
#define GPIO_K_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G0R_SHIFT)
#define GPIO_K_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_K_VM_01_0
#define GPIO_K_VM_01_0                  MK_ADDR_CONST(0x3008)
#define GPIO_K_VM_01_0_SECURE                   0x0
#define GPIO_K_VM_01_0_DUAL                     0x0
#define GPIO_K_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_01_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_01_0_WORD_COUNT                       0x1
#define GPIO_K_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM1_SHIFT)
#define GPIO_K_VM_01_0_VM1_RANGE                        1:0
#define GPIO_K_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_K_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_K_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM2_SHIFT)
#define GPIO_K_VM_01_0_VM2_RANGE                        3:2
#define GPIO_K_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_K_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_K_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_K_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM3_SHIFT)
#define GPIO_K_VM_01_0_VM3_RANGE                        5:4
#define GPIO_K_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_K_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_K_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_K_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM4_SHIFT)
#define GPIO_K_VM_01_0_VM4_RANGE                        7:6
#define GPIO_K_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_K_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_K_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM5_SHIFT)
#define GPIO_K_VM_01_0_VM5_RANGE                        9:8
#define GPIO_K_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_K_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_K_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_K_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM6_SHIFT)
#define GPIO_K_VM_01_0_VM6_RANGE                        11:10
#define GPIO_K_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_K_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_K_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_K_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM7_SHIFT)
#define GPIO_K_VM_01_0_VM7_RANGE                        13:12
#define GPIO_K_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_K_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_K_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_K_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM8_SHIFT)
#define GPIO_K_VM_01_0_VM8_RANGE                        15:14
#define GPIO_K_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_K_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_K_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_01_0
#define GPIO_K_SCR_01_0                 MK_ADDR_CONST(0x300c)
#define GPIO_K_SCR_01_0_SECURE                  0x0
#define GPIO_K_SCR_01_0_DUAL                    0x0
#define GPIO_K_SCR_01_0_SCR                     0
#define GPIO_K_SCR_01_0_SCRREG                  0
#define GPIO_K_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_K_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_K_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_K_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_K_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_K_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_K_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_K_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_K_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR7_SHIFT)
#define GPIO_K_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_K_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR6_SHIFT)
#define GPIO_K_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_K_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR5_SHIFT)
#define GPIO_K_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_K_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR4_SHIFT)
#define GPIO_K_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_K_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR3_SHIFT)
#define GPIO_K_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_K_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR2_SHIFT)
#define GPIO_K_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_K_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR1_SHIFT)
#define GPIO_K_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_K_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR0_SHIFT)
#define GPIO_K_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_K_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G7W_SHIFT)
#define GPIO_K_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_K_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G6W_SHIFT)
#define GPIO_K_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_K_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G5W_SHIFT)
#define GPIO_K_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_K_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G4W_SHIFT)
#define GPIO_K_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_K_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G3W_SHIFT)
#define GPIO_K_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_K_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G2W_SHIFT)
#define GPIO_K_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_K_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G1W_SHIFT)
#define GPIO_K_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_K_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G0W_SHIFT)
#define GPIO_K_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_K_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G7R_SHIFT)
#define GPIO_K_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_K_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G6R_SHIFT)
#define GPIO_K_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G5R_SHIFT)
#define GPIO_K_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_K_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G4R_SHIFT)
#define GPIO_K_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_K_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G3R_SHIFT)
#define GPIO_K_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_K_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G2R_SHIFT)
#define GPIO_K_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_K_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G1R_SHIFT)
#define GPIO_K_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G0R_SHIFT)
#define GPIO_K_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_K_VM_02_0
#define GPIO_K_VM_02_0                  MK_ADDR_CONST(0x3010)
#define GPIO_K_VM_02_0_SECURE                   0x0
#define GPIO_K_VM_02_0_DUAL                     0x0
#define GPIO_K_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_02_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_02_0_WORD_COUNT                       0x1
#define GPIO_K_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM1_SHIFT)
#define GPIO_K_VM_02_0_VM1_RANGE                        1:0
#define GPIO_K_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_K_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_K_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM2_SHIFT)
#define GPIO_K_VM_02_0_VM2_RANGE                        3:2
#define GPIO_K_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_K_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_K_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_K_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM3_SHIFT)
#define GPIO_K_VM_02_0_VM3_RANGE                        5:4
#define GPIO_K_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_K_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_K_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_K_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM4_SHIFT)
#define GPIO_K_VM_02_0_VM4_RANGE                        7:6
#define GPIO_K_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_K_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_K_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM5_SHIFT)
#define GPIO_K_VM_02_0_VM5_RANGE                        9:8
#define GPIO_K_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_K_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_K_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_K_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM6_SHIFT)
#define GPIO_K_VM_02_0_VM6_RANGE                        11:10
#define GPIO_K_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_K_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_K_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_K_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM7_SHIFT)
#define GPIO_K_VM_02_0_VM7_RANGE                        13:12
#define GPIO_K_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_K_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_K_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_K_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM8_SHIFT)
#define GPIO_K_VM_02_0_VM8_RANGE                        15:14
#define GPIO_K_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_K_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_K_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_02_0
#define GPIO_K_SCR_02_0                 MK_ADDR_CONST(0x3014)
#define GPIO_K_SCR_02_0_SECURE                  0x0
#define GPIO_K_SCR_02_0_DUAL                    0x0
#define GPIO_K_SCR_02_0_SCR                     0
#define GPIO_K_SCR_02_0_SCRREG                  0
#define GPIO_K_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_K_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_K_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_K_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_K_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_K_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_K_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_K_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_K_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR7_SHIFT)
#define GPIO_K_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_K_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR6_SHIFT)
#define GPIO_K_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_K_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR5_SHIFT)
#define GPIO_K_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_K_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR4_SHIFT)
#define GPIO_K_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_K_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR3_SHIFT)
#define GPIO_K_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_K_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR2_SHIFT)
#define GPIO_K_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_K_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR1_SHIFT)
#define GPIO_K_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_K_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR0_SHIFT)
#define GPIO_K_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_K_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G7W_SHIFT)
#define GPIO_K_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_K_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G6W_SHIFT)
#define GPIO_K_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_K_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G5W_SHIFT)
#define GPIO_K_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_K_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G4W_SHIFT)
#define GPIO_K_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_K_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G3W_SHIFT)
#define GPIO_K_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_K_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G2W_SHIFT)
#define GPIO_K_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_K_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G1W_SHIFT)
#define GPIO_K_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_K_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G0W_SHIFT)
#define GPIO_K_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_K_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G7R_SHIFT)
#define GPIO_K_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_K_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G6R_SHIFT)
#define GPIO_K_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G5R_SHIFT)
#define GPIO_K_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_K_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G4R_SHIFT)
#define GPIO_K_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_K_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G3R_SHIFT)
#define GPIO_K_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_K_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G2R_SHIFT)
#define GPIO_K_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_K_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G1R_SHIFT)
#define GPIO_K_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G0R_SHIFT)
#define GPIO_K_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_K_VM_03_0
#define GPIO_K_VM_03_0                  MK_ADDR_CONST(0x3018)
#define GPIO_K_VM_03_0_SECURE                   0x0
#define GPIO_K_VM_03_0_DUAL                     0x0
#define GPIO_K_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_03_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_03_0_WORD_COUNT                       0x1
#define GPIO_K_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM1_SHIFT)
#define GPIO_K_VM_03_0_VM1_RANGE                        1:0
#define GPIO_K_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_K_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_K_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM2_SHIFT)
#define GPIO_K_VM_03_0_VM2_RANGE                        3:2
#define GPIO_K_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_K_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_K_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_K_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM3_SHIFT)
#define GPIO_K_VM_03_0_VM3_RANGE                        5:4
#define GPIO_K_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_K_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_K_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_K_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM4_SHIFT)
#define GPIO_K_VM_03_0_VM4_RANGE                        7:6
#define GPIO_K_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_K_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_K_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM5_SHIFT)
#define GPIO_K_VM_03_0_VM5_RANGE                        9:8
#define GPIO_K_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_K_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_K_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_K_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM6_SHIFT)
#define GPIO_K_VM_03_0_VM6_RANGE                        11:10
#define GPIO_K_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_K_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_K_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_K_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM7_SHIFT)
#define GPIO_K_VM_03_0_VM7_RANGE                        13:12
#define GPIO_K_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_K_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_K_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_K_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM8_SHIFT)
#define GPIO_K_VM_03_0_VM8_RANGE                        15:14
#define GPIO_K_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_K_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_K_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_03_0
#define GPIO_K_SCR_03_0                 MK_ADDR_CONST(0x301c)
#define GPIO_K_SCR_03_0_SECURE                  0x0
#define GPIO_K_SCR_03_0_DUAL                    0x0
#define GPIO_K_SCR_03_0_SCR                     0
#define GPIO_K_SCR_03_0_SCRREG                  0
#define GPIO_K_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_K_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_K_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_K_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_K_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_K_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_K_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_K_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_K_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR7_SHIFT)
#define GPIO_K_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_K_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR6_SHIFT)
#define GPIO_K_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_K_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR5_SHIFT)
#define GPIO_K_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_K_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR4_SHIFT)
#define GPIO_K_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_K_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR3_SHIFT)
#define GPIO_K_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_K_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR2_SHIFT)
#define GPIO_K_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_K_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR1_SHIFT)
#define GPIO_K_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_K_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR0_SHIFT)
#define GPIO_K_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_K_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G7W_SHIFT)
#define GPIO_K_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_K_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G6W_SHIFT)
#define GPIO_K_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_K_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G5W_SHIFT)
#define GPIO_K_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_K_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G4W_SHIFT)
#define GPIO_K_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_K_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G3W_SHIFT)
#define GPIO_K_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_K_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G2W_SHIFT)
#define GPIO_K_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_K_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G1W_SHIFT)
#define GPIO_K_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_K_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G0W_SHIFT)
#define GPIO_K_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_K_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G7R_SHIFT)
#define GPIO_K_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_K_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G6R_SHIFT)
#define GPIO_K_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G5R_SHIFT)
#define GPIO_K_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_K_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G4R_SHIFT)
#define GPIO_K_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_K_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G3R_SHIFT)
#define GPIO_K_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_K_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G2R_SHIFT)
#define GPIO_K_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_K_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G1R_SHIFT)
#define GPIO_K_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G0R_SHIFT)
#define GPIO_K_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_K_VM_04_0
#define GPIO_K_VM_04_0                  MK_ADDR_CONST(0x3020)
#define GPIO_K_VM_04_0_SECURE                   0x0
#define GPIO_K_VM_04_0_DUAL                     0x0
#define GPIO_K_VM_04_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_04_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_04_0_WORD_COUNT                       0x1
#define GPIO_K_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM1_SHIFT)
#define GPIO_K_VM_04_0_VM1_RANGE                        1:0
#define GPIO_K_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_K_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_K_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM2_SHIFT)
#define GPIO_K_VM_04_0_VM2_RANGE                        3:2
#define GPIO_K_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_K_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_K_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_K_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM3_SHIFT)
#define GPIO_K_VM_04_0_VM3_RANGE                        5:4
#define GPIO_K_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_K_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_K_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_K_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM4_SHIFT)
#define GPIO_K_VM_04_0_VM4_RANGE                        7:6
#define GPIO_K_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_K_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_K_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM5_SHIFT)
#define GPIO_K_VM_04_0_VM5_RANGE                        9:8
#define GPIO_K_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_K_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_K_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_K_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM6_SHIFT)
#define GPIO_K_VM_04_0_VM6_RANGE                        11:10
#define GPIO_K_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_K_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_K_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_K_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM7_SHIFT)
#define GPIO_K_VM_04_0_VM7_RANGE                        13:12
#define GPIO_K_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_K_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_K_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_K_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM8_SHIFT)
#define GPIO_K_VM_04_0_VM8_RANGE                        15:14
#define GPIO_K_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_K_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_K_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_04_0
#define GPIO_K_SCR_04_0                 MK_ADDR_CONST(0x3024)
#define GPIO_K_SCR_04_0_SECURE                  0x0
#define GPIO_K_SCR_04_0_DUAL                    0x0
#define GPIO_K_SCR_04_0_SCR                     0
#define GPIO_K_SCR_04_0_SCRREG                  0
#define GPIO_K_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_K_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_K_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_K_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_K_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_K_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_K_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_K_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_K_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR7_SHIFT)
#define GPIO_K_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_K_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR6_SHIFT)
#define GPIO_K_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_K_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR5_SHIFT)
#define GPIO_K_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_K_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR4_SHIFT)
#define GPIO_K_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_K_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR3_SHIFT)
#define GPIO_K_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_K_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR2_SHIFT)
#define GPIO_K_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_K_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR1_SHIFT)
#define GPIO_K_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_K_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR0_SHIFT)
#define GPIO_K_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_K_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G7W_SHIFT)
#define GPIO_K_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_K_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G6W_SHIFT)
#define GPIO_K_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_K_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G5W_SHIFT)
#define GPIO_K_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_K_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G4W_SHIFT)
#define GPIO_K_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_K_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G3W_SHIFT)
#define GPIO_K_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_K_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G2W_SHIFT)
#define GPIO_K_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_K_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G1W_SHIFT)
#define GPIO_K_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_K_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G0W_SHIFT)
#define GPIO_K_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_K_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G7R_SHIFT)
#define GPIO_K_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_K_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G6R_SHIFT)
#define GPIO_K_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G5R_SHIFT)
#define GPIO_K_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_K_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G4R_SHIFT)
#define GPIO_K_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_K_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G3R_SHIFT)
#define GPIO_K_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_K_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G2R_SHIFT)
#define GPIO_K_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_K_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G1R_SHIFT)
#define GPIO_K_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G0R_SHIFT)
#define GPIO_K_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_K_VM_05_0
#define GPIO_K_VM_05_0                  MK_ADDR_CONST(0x3028)
#define GPIO_K_VM_05_0_SECURE                   0x0
#define GPIO_K_VM_05_0_DUAL                     0x0
#define GPIO_K_VM_05_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_05_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_05_0_WORD_COUNT                       0x1
#define GPIO_K_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM1_SHIFT)
#define GPIO_K_VM_05_0_VM1_RANGE                        1:0
#define GPIO_K_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_K_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_K_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM2_SHIFT)
#define GPIO_K_VM_05_0_VM2_RANGE                        3:2
#define GPIO_K_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_K_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_K_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_K_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM3_SHIFT)
#define GPIO_K_VM_05_0_VM3_RANGE                        5:4
#define GPIO_K_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_K_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_K_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_K_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM4_SHIFT)
#define GPIO_K_VM_05_0_VM4_RANGE                        7:6
#define GPIO_K_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_K_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_K_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM5_SHIFT)
#define GPIO_K_VM_05_0_VM5_RANGE                        9:8
#define GPIO_K_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_K_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_K_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_K_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM6_SHIFT)
#define GPIO_K_VM_05_0_VM6_RANGE                        11:10
#define GPIO_K_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_K_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_K_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_K_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM7_SHIFT)
#define GPIO_K_VM_05_0_VM7_RANGE                        13:12
#define GPIO_K_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_K_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_K_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_K_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM8_SHIFT)
#define GPIO_K_VM_05_0_VM8_RANGE                        15:14
#define GPIO_K_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_K_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_K_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_05_0
#define GPIO_K_SCR_05_0                 MK_ADDR_CONST(0x302c)
#define GPIO_K_SCR_05_0_SECURE                  0x0
#define GPIO_K_SCR_05_0_DUAL                    0x0
#define GPIO_K_SCR_05_0_SCR                     0
#define GPIO_K_SCR_05_0_SCRREG                  0
#define GPIO_K_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_K_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_K_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_K_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_K_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_K_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_K_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_K_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_K_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR7_SHIFT)
#define GPIO_K_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_K_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR6_SHIFT)
#define GPIO_K_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_K_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR5_SHIFT)
#define GPIO_K_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_K_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR4_SHIFT)
#define GPIO_K_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_K_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR3_SHIFT)
#define GPIO_K_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_K_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR2_SHIFT)
#define GPIO_K_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_K_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR1_SHIFT)
#define GPIO_K_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_K_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR0_SHIFT)
#define GPIO_K_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_K_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G7W_SHIFT)
#define GPIO_K_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_K_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G6W_SHIFT)
#define GPIO_K_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_K_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G5W_SHIFT)
#define GPIO_K_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_K_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G4W_SHIFT)
#define GPIO_K_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_K_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G3W_SHIFT)
#define GPIO_K_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_K_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G2W_SHIFT)
#define GPIO_K_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_K_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G1W_SHIFT)
#define GPIO_K_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_K_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G0W_SHIFT)
#define GPIO_K_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_K_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G7R_SHIFT)
#define GPIO_K_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_K_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G6R_SHIFT)
#define GPIO_K_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G5R_SHIFT)
#define GPIO_K_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_K_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G4R_SHIFT)
#define GPIO_K_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_K_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G3R_SHIFT)
#define GPIO_K_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_K_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G2R_SHIFT)
#define GPIO_K_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_K_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G1R_SHIFT)
#define GPIO_K_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G0R_SHIFT)
#define GPIO_K_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_K_VM_06_0
#define GPIO_K_VM_06_0                  MK_ADDR_CONST(0x3030)
#define GPIO_K_VM_06_0_SECURE                   0x0
#define GPIO_K_VM_06_0_DUAL                     0x0
#define GPIO_K_VM_06_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_06_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_06_0_WORD_COUNT                       0x1
#define GPIO_K_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM1_SHIFT)
#define GPIO_K_VM_06_0_VM1_RANGE                        1:0
#define GPIO_K_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_K_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_K_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM2_SHIFT)
#define GPIO_K_VM_06_0_VM2_RANGE                        3:2
#define GPIO_K_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_K_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_K_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_K_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM3_SHIFT)
#define GPIO_K_VM_06_0_VM3_RANGE                        5:4
#define GPIO_K_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_K_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_K_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_K_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM4_SHIFT)
#define GPIO_K_VM_06_0_VM4_RANGE                        7:6
#define GPIO_K_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_K_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_K_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM5_SHIFT)
#define GPIO_K_VM_06_0_VM5_RANGE                        9:8
#define GPIO_K_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_K_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_K_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_K_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM6_SHIFT)
#define GPIO_K_VM_06_0_VM6_RANGE                        11:10
#define GPIO_K_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_K_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_K_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_K_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM7_SHIFT)
#define GPIO_K_VM_06_0_VM7_RANGE                        13:12
#define GPIO_K_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_K_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_K_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_K_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM8_SHIFT)
#define GPIO_K_VM_06_0_VM8_RANGE                        15:14
#define GPIO_K_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_K_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_K_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_06_0
#define GPIO_K_SCR_06_0                 MK_ADDR_CONST(0x3034)
#define GPIO_K_SCR_06_0_SECURE                  0x0
#define GPIO_K_SCR_06_0_DUAL                    0x0
#define GPIO_K_SCR_06_0_SCR                     0
#define GPIO_K_SCR_06_0_SCRREG                  0
#define GPIO_K_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_K_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_K_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_K_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_K_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_K_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_K_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_K_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_K_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR7_SHIFT)
#define GPIO_K_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_K_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR6_SHIFT)
#define GPIO_K_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_K_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR5_SHIFT)
#define GPIO_K_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_K_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR4_SHIFT)
#define GPIO_K_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_K_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR3_SHIFT)
#define GPIO_K_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_K_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR2_SHIFT)
#define GPIO_K_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_K_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR1_SHIFT)
#define GPIO_K_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_K_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR0_SHIFT)
#define GPIO_K_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_K_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G7W_SHIFT)
#define GPIO_K_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_K_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G6W_SHIFT)
#define GPIO_K_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_K_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G5W_SHIFT)
#define GPIO_K_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_K_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G4W_SHIFT)
#define GPIO_K_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_K_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G3W_SHIFT)
#define GPIO_K_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_K_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G2W_SHIFT)
#define GPIO_K_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_K_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G1W_SHIFT)
#define GPIO_K_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_K_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G0W_SHIFT)
#define GPIO_K_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_K_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G7R_SHIFT)
#define GPIO_K_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_K_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G6R_SHIFT)
#define GPIO_K_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G5R_SHIFT)
#define GPIO_K_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_K_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G4R_SHIFT)
#define GPIO_K_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_K_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G3R_SHIFT)
#define GPIO_K_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_K_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G2R_SHIFT)
#define GPIO_K_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_K_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G1R_SHIFT)
#define GPIO_K_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G0R_SHIFT)
#define GPIO_K_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_K_VM_07_0
#define GPIO_K_VM_07_0                  MK_ADDR_CONST(0x3038)
#define GPIO_K_VM_07_0_SECURE                   0x0
#define GPIO_K_VM_07_0_DUAL                     0x0
#define GPIO_K_VM_07_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_07_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_K_VM_07_0_WORD_COUNT                       0x1
#define GPIO_K_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_K_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_K_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM1_SHIFT)
#define GPIO_K_VM_07_0_VM1_RANGE                        1:0
#define GPIO_K_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_K_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_K_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM2_SHIFT)
#define GPIO_K_VM_07_0_VM2_RANGE                        3:2
#define GPIO_K_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_K_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_K_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_K_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM3_SHIFT)
#define GPIO_K_VM_07_0_VM3_RANGE                        5:4
#define GPIO_K_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_K_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_K_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_K_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM4_SHIFT)
#define GPIO_K_VM_07_0_VM4_RANGE                        7:6
#define GPIO_K_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_K_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_K_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM5_SHIFT)
#define GPIO_K_VM_07_0_VM5_RANGE                        9:8
#define GPIO_K_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_K_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_K_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_K_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM6_SHIFT)
#define GPIO_K_VM_07_0_VM6_RANGE                        11:10
#define GPIO_K_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_K_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_K_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_K_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM7_SHIFT)
#define GPIO_K_VM_07_0_VM7_RANGE                        13:12
#define GPIO_K_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_K_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_K_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_K_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_K_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM8_SHIFT)
#define GPIO_K_VM_07_0_VM8_RANGE                        15:14
#define GPIO_K_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_K_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_K_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_K_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_K_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_SCR_07_0
#define GPIO_K_SCR_07_0                 MK_ADDR_CONST(0x303c)
#define GPIO_K_SCR_07_0_SECURE                  0x0
#define GPIO_K_SCR_07_0_DUAL                    0x0
#define GPIO_K_SCR_07_0_SCR                     0
#define GPIO_K_SCR_07_0_SCRREG                  0
#define GPIO_K_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_K_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_K_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_K_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_K_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_K_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_K_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_K_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_K_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_K_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_K_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_K_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_K_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_K_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_K_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_K_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_K_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_K_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_K_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_K_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_K_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_K_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_K_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_K_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_K_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_K_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR7_SHIFT)
#define GPIO_K_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_K_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_K_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_K_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR6_SHIFT)
#define GPIO_K_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_K_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_K_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_K_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR5_SHIFT)
#define GPIO_K_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_K_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_K_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_K_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR4_SHIFT)
#define GPIO_K_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_K_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_K_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_K_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR3_SHIFT)
#define GPIO_K_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_K_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_K_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_K_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR2_SHIFT)
#define GPIO_K_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_K_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_K_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_K_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR1_SHIFT)
#define GPIO_K_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_K_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_K_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_K_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR0_SHIFT)
#define GPIO_K_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_K_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_K_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_K_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G7W_SHIFT)
#define GPIO_K_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_K_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_K_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_K_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G6W_SHIFT)
#define GPIO_K_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_K_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_K_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_K_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G5W_SHIFT)
#define GPIO_K_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_K_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_K_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_K_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G4W_SHIFT)
#define GPIO_K_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_K_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_K_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_K_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G3W_SHIFT)
#define GPIO_K_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_K_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_K_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_K_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G2W_SHIFT)
#define GPIO_K_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_K_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_K_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_K_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G1W_SHIFT)
#define GPIO_K_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_K_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_K_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_K_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G0W_SHIFT)
#define GPIO_K_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_K_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_K_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_K_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G7R_SHIFT)
#define GPIO_K_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_K_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_K_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_K_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G6R_SHIFT)
#define GPIO_K_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_K_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_K_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G5R_SHIFT)
#define GPIO_K_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_K_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_K_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G4R_SHIFT)
#define GPIO_K_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_K_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_K_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_K_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G3R_SHIFT)
#define GPIO_K_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_K_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_K_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_K_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G2R_SHIFT)
#define GPIO_K_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_K_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_K_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_K_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G1R_SHIFT)
#define GPIO_K_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_K_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_K_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_K_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G0R_SHIFT)
#define GPIO_K_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_K_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_K_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_K_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_L_VM_00_0
#define GPIO_L_VM_00_0                  MK_ADDR_CONST(0x3040)
#define GPIO_L_VM_00_0_SECURE                   0x0
#define GPIO_L_VM_00_0_DUAL                     0x0
#define GPIO_L_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_00_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_00_0_WORD_COUNT                       0x1
#define GPIO_L_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_L_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM1_SHIFT)
#define GPIO_L_VM_00_0_VM1_RANGE                        1:0
#define GPIO_L_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_L_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_L_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM2_SHIFT)
#define GPIO_L_VM_00_0_VM2_RANGE                        3:2
#define GPIO_L_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_L_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_L_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM3_SHIFT)
#define GPIO_L_VM_00_0_VM3_RANGE                        5:4
#define GPIO_L_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_L_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_L_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_L_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM4_SHIFT)
#define GPIO_L_VM_00_0_VM4_RANGE                        7:6
#define GPIO_L_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_L_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_L_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_L_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM5_SHIFT)
#define GPIO_L_VM_00_0_VM5_RANGE                        9:8
#define GPIO_L_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_L_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_L_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_L_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM6_SHIFT)
#define GPIO_L_VM_00_0_VM6_RANGE                        11:10
#define GPIO_L_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_L_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_L_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_L_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM7_SHIFT)
#define GPIO_L_VM_00_0_VM7_RANGE                        13:12
#define GPIO_L_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_L_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_L_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_L_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM8_SHIFT)
#define GPIO_L_VM_00_0_VM8_RANGE                        15:14
#define GPIO_L_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_L_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_L_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_SCR_00_0
#define GPIO_L_SCR_00_0                 MK_ADDR_CONST(0x3044)
#define GPIO_L_SCR_00_0_SECURE                  0x0
#define GPIO_L_SCR_00_0_DUAL                    0x0
#define GPIO_L_SCR_00_0_SCR                     0
#define GPIO_L_SCR_00_0_SCRREG                  0
#define GPIO_L_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_L_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_L_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_L_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_L_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_L_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_L_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_L_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_L_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_L_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_L_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_L_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_L_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_L_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_L_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_L_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR7_SHIFT)
#define GPIO_L_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_L_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_L_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_L_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR6_SHIFT)
#define GPIO_L_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_L_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_L_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_L_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR5_SHIFT)
#define GPIO_L_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_L_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_L_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_L_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR4_SHIFT)
#define GPIO_L_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_L_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_L_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_L_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR3_SHIFT)
#define GPIO_L_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_L_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_L_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_L_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR2_SHIFT)
#define GPIO_L_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_L_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_L_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_L_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR1_SHIFT)
#define GPIO_L_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_L_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_L_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_L_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR0_SHIFT)
#define GPIO_L_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_L_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_L_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_L_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G7W_SHIFT)
#define GPIO_L_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_L_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_L_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_L_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G6W_SHIFT)
#define GPIO_L_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_L_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_L_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_L_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G5W_SHIFT)
#define GPIO_L_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_L_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_L_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_L_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G4W_SHIFT)
#define GPIO_L_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_L_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_L_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_L_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G3W_SHIFT)
#define GPIO_L_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_L_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_L_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_L_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G2W_SHIFT)
#define GPIO_L_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_L_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_L_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_L_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G1W_SHIFT)
#define GPIO_L_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_L_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_L_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_L_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G0W_SHIFT)
#define GPIO_L_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_L_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_L_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_L_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G7R_SHIFT)
#define GPIO_L_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_L_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_L_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_L_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G6R_SHIFT)
#define GPIO_L_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_L_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_L_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_L_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G5R_SHIFT)
#define GPIO_L_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_L_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_L_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_L_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G4R_SHIFT)
#define GPIO_L_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_L_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_L_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_L_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G3R_SHIFT)
#define GPIO_L_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_L_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_L_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_L_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G2R_SHIFT)
#define GPIO_L_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_L_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_L_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_L_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G1R_SHIFT)
#define GPIO_L_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_L_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_L_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_L_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G0R_SHIFT)
#define GPIO_L_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_L_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_L_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_L_VM_01_0
#define GPIO_L_VM_01_0                  MK_ADDR_CONST(0x3048)
#define GPIO_L_VM_01_0_SECURE                   0x0
#define GPIO_L_VM_01_0_DUAL                     0x0
#define GPIO_L_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_01_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_01_0_WORD_COUNT                       0x1
#define GPIO_L_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_L_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM1_SHIFT)
#define GPIO_L_VM_01_0_VM1_RANGE                        1:0
#define GPIO_L_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_L_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_L_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM2_SHIFT)
#define GPIO_L_VM_01_0_VM2_RANGE                        3:2
#define GPIO_L_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_L_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_L_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM3_SHIFT)
#define GPIO_L_VM_01_0_VM3_RANGE                        5:4
#define GPIO_L_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_L_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_L_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_L_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM4_SHIFT)
#define GPIO_L_VM_01_0_VM4_RANGE                        7:6
#define GPIO_L_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_L_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_L_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_L_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM5_SHIFT)
#define GPIO_L_VM_01_0_VM5_RANGE                        9:8
#define GPIO_L_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_L_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_L_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_L_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM6_SHIFT)
#define GPIO_L_VM_01_0_VM6_RANGE                        11:10
#define GPIO_L_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_L_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_L_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_L_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM7_SHIFT)
#define GPIO_L_VM_01_0_VM7_RANGE                        13:12
#define GPIO_L_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_L_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_L_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_L_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM8_SHIFT)
#define GPIO_L_VM_01_0_VM8_RANGE                        15:14
#define GPIO_L_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_L_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_L_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_SCR_01_0
#define GPIO_L_SCR_01_0                 MK_ADDR_CONST(0x304c)
#define GPIO_L_SCR_01_0_SECURE                  0x0
#define GPIO_L_SCR_01_0_DUAL                    0x0
#define GPIO_L_SCR_01_0_SCR                     0
#define GPIO_L_SCR_01_0_SCRREG                  0
#define GPIO_L_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_L_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_L_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_L_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_L_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_L_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_L_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_L_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_L_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_L_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_L_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_L_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_L_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_L_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_L_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_L_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR7_SHIFT)
#define GPIO_L_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_L_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_L_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_L_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR6_SHIFT)
#define GPIO_L_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_L_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_L_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_L_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR5_SHIFT)
#define GPIO_L_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_L_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_L_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_L_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR4_SHIFT)
#define GPIO_L_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_L_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_L_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_L_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR3_SHIFT)
#define GPIO_L_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_L_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_L_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_L_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR2_SHIFT)
#define GPIO_L_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_L_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_L_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_L_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR1_SHIFT)
#define GPIO_L_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_L_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_L_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_L_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR0_SHIFT)
#define GPIO_L_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_L_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_L_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_L_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G7W_SHIFT)
#define GPIO_L_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_L_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_L_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_L_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G6W_SHIFT)
#define GPIO_L_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_L_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_L_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_L_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G5W_SHIFT)
#define GPIO_L_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_L_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_L_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_L_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G4W_SHIFT)
#define GPIO_L_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_L_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_L_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_L_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G3W_SHIFT)
#define GPIO_L_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_L_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_L_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_L_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G2W_SHIFT)
#define GPIO_L_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_L_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_L_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_L_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G1W_SHIFT)
#define GPIO_L_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_L_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_L_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_L_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G0W_SHIFT)
#define GPIO_L_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_L_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_L_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_L_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G7R_SHIFT)
#define GPIO_L_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_L_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_L_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_L_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G6R_SHIFT)
#define GPIO_L_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_L_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_L_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_L_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G5R_SHIFT)
#define GPIO_L_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_L_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_L_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_L_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G4R_SHIFT)
#define GPIO_L_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_L_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_L_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_L_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G3R_SHIFT)
#define GPIO_L_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_L_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_L_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_L_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G2R_SHIFT)
#define GPIO_L_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_L_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_L_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_L_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G1R_SHIFT)
#define GPIO_L_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_L_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_L_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_L_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G0R_SHIFT)
#define GPIO_L_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_L_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_L_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_L_VM_02_0
#define GPIO_L_VM_02_0                  MK_ADDR_CONST(0x3050)
#define GPIO_L_VM_02_0_SECURE                   0x0
#define GPIO_L_VM_02_0_DUAL                     0x0
#define GPIO_L_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_02_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_02_0_WORD_COUNT                       0x1
#define GPIO_L_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_L_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM1_SHIFT)
#define GPIO_L_VM_02_0_VM1_RANGE                        1:0
#define GPIO_L_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_L_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_L_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM2_SHIFT)
#define GPIO_L_VM_02_0_VM2_RANGE                        3:2
#define GPIO_L_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_L_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_L_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM3_SHIFT)
#define GPIO_L_VM_02_0_VM3_RANGE                        5:4
#define GPIO_L_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_L_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_L_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_L_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM4_SHIFT)
#define GPIO_L_VM_02_0_VM4_RANGE                        7:6
#define GPIO_L_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_L_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_L_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_L_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM5_SHIFT)
#define GPIO_L_VM_02_0_VM5_RANGE                        9:8
#define GPIO_L_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_L_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_L_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_L_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM6_SHIFT)
#define GPIO_L_VM_02_0_VM6_RANGE                        11:10
#define GPIO_L_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_L_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_L_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_L_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM7_SHIFT)
#define GPIO_L_VM_02_0_VM7_RANGE                        13:12
#define GPIO_L_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_L_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_L_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_L_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM8_SHIFT)
#define GPIO_L_VM_02_0_VM8_RANGE                        15:14
#define GPIO_L_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_L_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_L_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_SCR_02_0
#define GPIO_L_SCR_02_0                 MK_ADDR_CONST(0x3054)
#define GPIO_L_SCR_02_0_SECURE                  0x0
#define GPIO_L_SCR_02_0_DUAL                    0x0
#define GPIO_L_SCR_02_0_SCR                     0
#define GPIO_L_SCR_02_0_SCRREG                  0
#define GPIO_L_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_L_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_L_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_L_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_L_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_L_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_L_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_L_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_L_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_L_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_L_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_L_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_L_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_L_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_L_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_L_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR7_SHIFT)
#define GPIO_L_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_L_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_L_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_L_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR6_SHIFT)
#define GPIO_L_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_L_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_L_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_L_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR5_SHIFT)
#define GPIO_L_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_L_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_L_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_L_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR4_SHIFT)
#define GPIO_L_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_L_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_L_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_L_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR3_SHIFT)
#define GPIO_L_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_L_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_L_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_L_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR2_SHIFT)
#define GPIO_L_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_L_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_L_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_L_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR1_SHIFT)
#define GPIO_L_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_L_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_L_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_L_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR0_SHIFT)
#define GPIO_L_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_L_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_L_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_L_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G7W_SHIFT)
#define GPIO_L_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_L_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_L_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_L_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G6W_SHIFT)
#define GPIO_L_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_L_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_L_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_L_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G5W_SHIFT)
#define GPIO_L_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_L_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_L_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_L_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G4W_SHIFT)
#define GPIO_L_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_L_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_L_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_L_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G3W_SHIFT)
#define GPIO_L_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_L_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_L_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_L_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G2W_SHIFT)
#define GPIO_L_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_L_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_L_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_L_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G1W_SHIFT)
#define GPIO_L_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_L_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_L_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_L_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G0W_SHIFT)
#define GPIO_L_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_L_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_L_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_L_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G7R_SHIFT)
#define GPIO_L_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_L_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_L_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_L_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G6R_SHIFT)
#define GPIO_L_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_L_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_L_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_L_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G5R_SHIFT)
#define GPIO_L_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_L_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_L_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_L_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G4R_SHIFT)
#define GPIO_L_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_L_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_L_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_L_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G3R_SHIFT)
#define GPIO_L_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_L_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_L_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_L_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G2R_SHIFT)
#define GPIO_L_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_L_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_L_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_L_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G1R_SHIFT)
#define GPIO_L_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_L_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_L_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_L_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G0R_SHIFT)
#define GPIO_L_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_L_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_L_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_L_VM_03_0
#define GPIO_L_VM_03_0                  MK_ADDR_CONST(0x3058)
#define GPIO_L_VM_03_0_SECURE                   0x0
#define GPIO_L_VM_03_0_DUAL                     0x0
#define GPIO_L_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_03_0_SCRREG                   GPIO_CTL3_VM_SCR_0
#define GPIO_L_VM_03_0_WORD_COUNT                       0x1
#define GPIO_L_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_L_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM1_SHIFT)
#define GPIO_L_VM_03_0_VM1_RANGE                        1:0
#define GPIO_L_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_L_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_L_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM2_SHIFT)
#define GPIO_L_VM_03_0_VM2_RANGE                        3:2
#define GPIO_L_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_L_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_L_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM3_SHIFT)
#define GPIO_L_VM_03_0_VM3_RANGE                        5:4
#define GPIO_L_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_L_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_L_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_L_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM4_SHIFT)
#define GPIO_L_VM_03_0_VM4_RANGE                        7:6
#define GPIO_L_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_L_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_L_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_L_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM5_SHIFT)
#define GPIO_L_VM_03_0_VM5_RANGE                        9:8
#define GPIO_L_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_L_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_L_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_L_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM6_SHIFT)
#define GPIO_L_VM_03_0_VM6_RANGE                        11:10
#define GPIO_L_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_L_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_L_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_L_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM7_SHIFT)
#define GPIO_L_VM_03_0_VM7_RANGE                        13:12
#define GPIO_L_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_L_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_L_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_L_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_L_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM8_SHIFT)
#define GPIO_L_VM_03_0_VM8_RANGE                        15:14
#define GPIO_L_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_L_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_L_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_L_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_L_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_SCR_03_0
#define GPIO_L_SCR_03_0                 MK_ADDR_CONST(0x305c)
#define GPIO_L_SCR_03_0_SECURE                  0x0
#define GPIO_L_SCR_03_0_DUAL                    0x0
#define GPIO_L_SCR_03_0_SCR                     0
#define GPIO_L_SCR_03_0_SCRREG                  0
#define GPIO_L_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_L_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_L_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_L_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_L_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_L_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_L_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_L_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_L_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_L_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_L_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_L_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_L_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_L_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_L_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_L_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_L_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_L_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_L_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_L_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_L_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_L_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_L_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_L_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_L_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_L_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_L_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_L_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR7_SHIFT)
#define GPIO_L_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_L_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_L_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_L_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_L_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR6_SHIFT)
#define GPIO_L_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_L_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_L_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_L_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_L_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR5_SHIFT)
#define GPIO_L_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_L_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_L_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_L_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_L_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR4_SHIFT)
#define GPIO_L_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_L_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_L_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_L_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_L_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR3_SHIFT)
#define GPIO_L_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_L_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_L_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_L_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_L_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR2_SHIFT)
#define GPIO_L_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_L_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_L_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_L_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_L_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR1_SHIFT)
#define GPIO_L_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_L_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_L_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_L_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_L_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR0_SHIFT)
#define GPIO_L_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_L_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_L_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_L_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_L_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G7W_SHIFT)
#define GPIO_L_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_L_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_L_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_L_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_L_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G6W_SHIFT)
#define GPIO_L_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_L_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_L_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_L_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_L_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G5W_SHIFT)
#define GPIO_L_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_L_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_L_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_L_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_L_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G4W_SHIFT)
#define GPIO_L_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_L_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_L_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_L_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_L_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G3W_SHIFT)
#define GPIO_L_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_L_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_L_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_L_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_L_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G2W_SHIFT)
#define GPIO_L_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_L_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_L_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_L_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_L_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G1W_SHIFT)
#define GPIO_L_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_L_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_L_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_L_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_L_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G0W_SHIFT)
#define GPIO_L_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_L_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_L_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_L_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_L_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G7R_SHIFT)
#define GPIO_L_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_L_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_L_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_L_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_L_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G6R_SHIFT)
#define GPIO_L_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_L_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_L_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_L_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_L_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G5R_SHIFT)
#define GPIO_L_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_L_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_L_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_L_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_L_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G4R_SHIFT)
#define GPIO_L_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_L_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_L_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_L_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_L_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G3R_SHIFT)
#define GPIO_L_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_L_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_L_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_L_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_L_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G2R_SHIFT)
#define GPIO_L_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_L_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_L_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_L_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_L_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G1R_SHIFT)
#define GPIO_L_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_L_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_L_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_L_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_L_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_L_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G0R_SHIFT)
#define GPIO_L_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_L_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_L_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_L_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_L_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_L_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x3060

// Reserved address 0x3064

// Reserved address 0x3068

// Reserved address 0x306c

// Reserved address 0x3070

// Reserved address 0x3074

// Reserved address 0x3078

// Reserved address 0x307c

// Register GPIO_AG_VM_00_0
#define GPIO_AG_VM_00_0                 MK_ADDR_CONST(0x3080)
#define GPIO_AG_VM_00_0_SECURE                  0x0
#define GPIO_AG_VM_00_0_DUAL                    0x0
#define GPIO_AG_VM_00_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_00_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_00_0_WORD_COUNT                      0x1
#define GPIO_AG_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM1_SHIFT)
#define GPIO_AG_VM_00_0_VM1_RANGE                       1:0
#define GPIO_AG_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AG_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_AG_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AG_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM2_SHIFT)
#define GPIO_AG_VM_00_0_VM2_RANGE                       3:2
#define GPIO_AG_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AG_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AG_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_AG_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AG_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM3_SHIFT)
#define GPIO_AG_VM_00_0_VM3_RANGE                       5:4
#define GPIO_AG_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AG_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AG_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_AG_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AG_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM4_SHIFT)
#define GPIO_AG_VM_00_0_VM4_RANGE                       7:6
#define GPIO_AG_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AG_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_AG_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AG_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM5_SHIFT)
#define GPIO_AG_VM_00_0_VM5_RANGE                       9:8
#define GPIO_AG_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AG_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AG_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_AG_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AG_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM6_SHIFT)
#define GPIO_AG_VM_00_0_VM6_RANGE                       11:10
#define GPIO_AG_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AG_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AG_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_AG_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AG_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM7_SHIFT)
#define GPIO_AG_VM_00_0_VM7_RANGE                       13:12
#define GPIO_AG_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AG_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AG_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_AG_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AG_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM8_SHIFT)
#define GPIO_AG_VM_00_0_VM8_RANGE                       15:14
#define GPIO_AG_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AG_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AG_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_AG_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_SCR_00_0
#define GPIO_AG_SCR_00_0                        MK_ADDR_CONST(0x3084)
#define GPIO_AG_SCR_00_0_SECURE                         0x0
#define GPIO_AG_SCR_00_0_DUAL                   0x0
#define GPIO_AG_SCR_00_0_SCR                    0
#define GPIO_AG_SCR_00_0_SCRREG                         0
#define GPIO_AG_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_AG_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_AG_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_AG_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AG_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_AG_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_AG_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AG_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_AG_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_AG_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AG_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_AG_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AG_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AG_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AG_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AG_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR7_SHIFT)
#define GPIO_AG_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_AG_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR6_SHIFT)
#define GPIO_AG_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_AG_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR5_SHIFT)
#define GPIO_AG_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_AG_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR4_SHIFT)
#define GPIO_AG_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_AG_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR3_SHIFT)
#define GPIO_AG_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_AG_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR2_SHIFT)
#define GPIO_AG_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_AG_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR1_SHIFT)
#define GPIO_AG_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_AG_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR0_SHIFT)
#define GPIO_AG_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_AG_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G7W_SHIFT)
#define GPIO_AG_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_AG_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G6W_SHIFT)
#define GPIO_AG_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_AG_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G5W_SHIFT)
#define GPIO_AG_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_AG_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G4W_SHIFT)
#define GPIO_AG_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_AG_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G3W_SHIFT)
#define GPIO_AG_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_AG_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G2W_SHIFT)
#define GPIO_AG_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_AG_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G1W_SHIFT)
#define GPIO_AG_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_AG_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G0W_SHIFT)
#define GPIO_AG_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_AG_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G7R_SHIFT)
#define GPIO_AG_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_AG_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G6R_SHIFT)
#define GPIO_AG_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_AG_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G5R_SHIFT)
#define GPIO_AG_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_AG_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G4R_SHIFT)
#define GPIO_AG_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_AG_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G3R_SHIFT)
#define GPIO_AG_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_AG_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G2R_SHIFT)
#define GPIO_AG_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_AG_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G1R_SHIFT)
#define GPIO_AG_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_AG_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G0R_SHIFT)
#define GPIO_AG_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_AG_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_AG_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AG_VM_01_0
#define GPIO_AG_VM_01_0                 MK_ADDR_CONST(0x3088)
#define GPIO_AG_VM_01_0_SECURE                  0x0
#define GPIO_AG_VM_01_0_DUAL                    0x0
#define GPIO_AG_VM_01_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_01_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_01_0_WORD_COUNT                      0x1
#define GPIO_AG_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM1_SHIFT)
#define GPIO_AG_VM_01_0_VM1_RANGE                       1:0
#define GPIO_AG_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AG_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_AG_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AG_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM2_SHIFT)
#define GPIO_AG_VM_01_0_VM2_RANGE                       3:2
#define GPIO_AG_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AG_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AG_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_AG_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AG_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM3_SHIFT)
#define GPIO_AG_VM_01_0_VM3_RANGE                       5:4
#define GPIO_AG_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AG_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AG_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_AG_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AG_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM4_SHIFT)
#define GPIO_AG_VM_01_0_VM4_RANGE                       7:6
#define GPIO_AG_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AG_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_AG_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AG_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM5_SHIFT)
#define GPIO_AG_VM_01_0_VM5_RANGE                       9:8
#define GPIO_AG_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AG_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AG_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_AG_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AG_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM6_SHIFT)
#define GPIO_AG_VM_01_0_VM6_RANGE                       11:10
#define GPIO_AG_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AG_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AG_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_AG_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AG_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM7_SHIFT)
#define GPIO_AG_VM_01_0_VM7_RANGE                       13:12
#define GPIO_AG_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AG_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AG_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_AG_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AG_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM8_SHIFT)
#define GPIO_AG_VM_01_0_VM8_RANGE                       15:14
#define GPIO_AG_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AG_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AG_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_AG_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_SCR_01_0
#define GPIO_AG_SCR_01_0                        MK_ADDR_CONST(0x308c)
#define GPIO_AG_SCR_01_0_SECURE                         0x0
#define GPIO_AG_SCR_01_0_DUAL                   0x0
#define GPIO_AG_SCR_01_0_SCR                    0
#define GPIO_AG_SCR_01_0_SCRREG                         0
#define GPIO_AG_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_AG_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_AG_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_AG_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AG_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_AG_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_AG_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AG_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_AG_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_AG_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AG_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_AG_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AG_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AG_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AG_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AG_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR7_SHIFT)
#define GPIO_AG_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_AG_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR6_SHIFT)
#define GPIO_AG_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_AG_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR5_SHIFT)
#define GPIO_AG_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_AG_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR4_SHIFT)
#define GPIO_AG_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_AG_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR3_SHIFT)
#define GPIO_AG_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_AG_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR2_SHIFT)
#define GPIO_AG_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_AG_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR1_SHIFT)
#define GPIO_AG_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_AG_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR0_SHIFT)
#define GPIO_AG_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_AG_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G7W_SHIFT)
#define GPIO_AG_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_AG_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G6W_SHIFT)
#define GPIO_AG_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_AG_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G5W_SHIFT)
#define GPIO_AG_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_AG_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G4W_SHIFT)
#define GPIO_AG_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_AG_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G3W_SHIFT)
#define GPIO_AG_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_AG_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G2W_SHIFT)
#define GPIO_AG_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_AG_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G1W_SHIFT)
#define GPIO_AG_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_AG_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G0W_SHIFT)
#define GPIO_AG_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_AG_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G7R_SHIFT)
#define GPIO_AG_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_AG_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G6R_SHIFT)
#define GPIO_AG_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_AG_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G5R_SHIFT)
#define GPIO_AG_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_AG_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G4R_SHIFT)
#define GPIO_AG_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_AG_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G3R_SHIFT)
#define GPIO_AG_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_AG_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G2R_SHIFT)
#define GPIO_AG_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_AG_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G1R_SHIFT)
#define GPIO_AG_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_AG_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G0R_SHIFT)
#define GPIO_AG_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_AG_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_AG_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AG_VM_02_0
#define GPIO_AG_VM_02_0                 MK_ADDR_CONST(0x3090)
#define GPIO_AG_VM_02_0_SECURE                  0x0
#define GPIO_AG_VM_02_0_DUAL                    0x0
#define GPIO_AG_VM_02_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_02_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_02_0_WORD_COUNT                      0x1
#define GPIO_AG_VM_02_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_02_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_02_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_02_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_VM_02_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM1_SHIFT)
#define GPIO_AG_VM_02_0_VM1_RANGE                       1:0
#define GPIO_AG_VM_02_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AG_VM_02_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_VM_02_0_VM1_WOFFSET                     0x0
#define GPIO_AG_VM_02_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_02_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AG_VM_02_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM2_SHIFT)
#define GPIO_AG_VM_02_0_VM2_RANGE                       3:2
#define GPIO_AG_VM_02_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AG_VM_02_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AG_VM_02_0_VM2_WOFFSET                     0x0
#define GPIO_AG_VM_02_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_02_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AG_VM_02_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM3_SHIFT)
#define GPIO_AG_VM_02_0_VM3_RANGE                       5:4
#define GPIO_AG_VM_02_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AG_VM_02_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AG_VM_02_0_VM3_WOFFSET                     0x0
#define GPIO_AG_VM_02_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_02_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AG_VM_02_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM4_SHIFT)
#define GPIO_AG_VM_02_0_VM4_RANGE                       7:6
#define GPIO_AG_VM_02_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_VM_02_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AG_VM_02_0_VM4_WOFFSET                     0x0
#define GPIO_AG_VM_02_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_02_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AG_VM_02_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM5_SHIFT)
#define GPIO_AG_VM_02_0_VM5_RANGE                       9:8
#define GPIO_AG_VM_02_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AG_VM_02_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AG_VM_02_0_VM5_WOFFSET                     0x0
#define GPIO_AG_VM_02_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_02_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AG_VM_02_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM6_SHIFT)
#define GPIO_AG_VM_02_0_VM6_RANGE                       11:10
#define GPIO_AG_VM_02_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AG_VM_02_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AG_VM_02_0_VM6_WOFFSET                     0x0
#define GPIO_AG_VM_02_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_02_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AG_VM_02_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM7_SHIFT)
#define GPIO_AG_VM_02_0_VM7_RANGE                       13:12
#define GPIO_AG_VM_02_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AG_VM_02_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AG_VM_02_0_VM7_WOFFSET                     0x0
#define GPIO_AG_VM_02_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_02_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AG_VM_02_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM8_SHIFT)
#define GPIO_AG_VM_02_0_VM8_RANGE                       15:14
#define GPIO_AG_VM_02_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AG_VM_02_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AG_VM_02_0_VM8_WOFFSET                     0x0
#define GPIO_AG_VM_02_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_02_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_02_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_SCR_02_0
#define GPIO_AG_SCR_02_0                        MK_ADDR_CONST(0x3094)
#define GPIO_AG_SCR_02_0_SECURE                         0x0
#define GPIO_AG_SCR_02_0_DUAL                   0x0
#define GPIO_AG_SCR_02_0_SCR                    0
#define GPIO_AG_SCR_02_0_SCRREG                         0
#define GPIO_AG_SCR_02_0_WORD_COUNT                     0x1
#define GPIO_AG_SCR_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_02_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_02_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_02_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_AG_SCR_02_0_SEC_LCK_RANGE                  29:29
#define GPIO_AG_SCR_02_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_02_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_02_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AG_SCR_02_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_02_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_AG_SCR_02_0_SEC_WEN_RANGE                  28:28
#define GPIO_AG_SCR_02_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_02_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_02_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AG_SCR_02_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_02_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_AG_SCR_02_0_SEC_REN_RANGE                  27:27
#define GPIO_AG_SCR_02_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_02_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_02_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AG_SCR_02_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_02_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_AG_SCR_02_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AG_SCR_02_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AG_SCR_02_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AG_SCR_02_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AG_SCR_02_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_02_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR7_SHIFT)
#define GPIO_AG_SCR_02_0_PR7_RANGE                      23:23
#define GPIO_AG_SCR_02_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_02_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_02_0_PR7_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_02_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR6_SHIFT)
#define GPIO_AG_SCR_02_0_PR6_RANGE                      22:22
#define GPIO_AG_SCR_02_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_02_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_02_0_PR6_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_02_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR5_SHIFT)
#define GPIO_AG_SCR_02_0_PR5_RANGE                      21:21
#define GPIO_AG_SCR_02_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_02_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_02_0_PR5_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_02_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR4_SHIFT)
#define GPIO_AG_SCR_02_0_PR4_RANGE                      20:20
#define GPIO_AG_SCR_02_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_02_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_02_0_PR4_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_02_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR3_SHIFT)
#define GPIO_AG_SCR_02_0_PR3_RANGE                      19:19
#define GPIO_AG_SCR_02_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_02_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_02_0_PR3_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_02_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR2_SHIFT)
#define GPIO_AG_SCR_02_0_PR2_RANGE                      18:18
#define GPIO_AG_SCR_02_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_02_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_02_0_PR2_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_02_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR1_SHIFT)
#define GPIO_AG_SCR_02_0_PR1_RANGE                      17:17
#define GPIO_AG_SCR_02_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_02_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_02_0_PR1_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_02_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR0_SHIFT)
#define GPIO_AG_SCR_02_0_PR0_RANGE                      16:16
#define GPIO_AG_SCR_02_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_02_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_02_0_PR0_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_02_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G7W_SHIFT)
#define GPIO_AG_SCR_02_0_G7W_RANGE                      15:15
#define GPIO_AG_SCR_02_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_02_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_02_0_G7W_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_02_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G6W_SHIFT)
#define GPIO_AG_SCR_02_0_G6W_RANGE                      14:14
#define GPIO_AG_SCR_02_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_02_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_02_0_G6W_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_02_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G5W_SHIFT)
#define GPIO_AG_SCR_02_0_G5W_RANGE                      13:13
#define GPIO_AG_SCR_02_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_02_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_02_0_G5W_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_02_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G4W_SHIFT)
#define GPIO_AG_SCR_02_0_G4W_RANGE                      12:12
#define GPIO_AG_SCR_02_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_02_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_02_0_G4W_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_02_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G3W_SHIFT)
#define GPIO_AG_SCR_02_0_G3W_RANGE                      11:11
#define GPIO_AG_SCR_02_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_02_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_02_0_G3W_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_02_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G2W_SHIFT)
#define GPIO_AG_SCR_02_0_G2W_RANGE                      10:10
#define GPIO_AG_SCR_02_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_02_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_02_0_G2W_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_02_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G1W_SHIFT)
#define GPIO_AG_SCR_02_0_G1W_RANGE                      9:9
#define GPIO_AG_SCR_02_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_02_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_02_0_G1W_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_02_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G0W_SHIFT)
#define GPIO_AG_SCR_02_0_G0W_RANGE                      8:8
#define GPIO_AG_SCR_02_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_02_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_02_0_G0W_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_02_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G7R_SHIFT)
#define GPIO_AG_SCR_02_0_G7R_RANGE                      7:7
#define GPIO_AG_SCR_02_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_02_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_02_0_G7R_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_02_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G6R_SHIFT)
#define GPIO_AG_SCR_02_0_G6R_RANGE                      6:6
#define GPIO_AG_SCR_02_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_02_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_02_0_G6R_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_02_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G5R_SHIFT)
#define GPIO_AG_SCR_02_0_G5R_RANGE                      5:5
#define GPIO_AG_SCR_02_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_02_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_02_0_G5R_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_02_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G4R_SHIFT)
#define GPIO_AG_SCR_02_0_G4R_RANGE                      4:4
#define GPIO_AG_SCR_02_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_02_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_02_0_G4R_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_02_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G3R_SHIFT)
#define GPIO_AG_SCR_02_0_G3R_RANGE                      3:3
#define GPIO_AG_SCR_02_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_02_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_02_0_G3R_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_02_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G2R_SHIFT)
#define GPIO_AG_SCR_02_0_G2R_RANGE                      2:2
#define GPIO_AG_SCR_02_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_02_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_02_0_G2R_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_02_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G1R_SHIFT)
#define GPIO_AG_SCR_02_0_G1R_RANGE                      1:1
#define GPIO_AG_SCR_02_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_02_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_02_0_G1R_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_02_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_02_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G0R_SHIFT)
#define GPIO_AG_SCR_02_0_G0R_RANGE                      0:0
#define GPIO_AG_SCR_02_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_02_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_02_0_G0R_WOFFSET                    0x0
#define GPIO_AG_SCR_02_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_02_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_02_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AG_VM_03_0
#define GPIO_AG_VM_03_0                 MK_ADDR_CONST(0x3098)
#define GPIO_AG_VM_03_0_SECURE                  0x0
#define GPIO_AG_VM_03_0_DUAL                    0x0
#define GPIO_AG_VM_03_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_03_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_03_0_WORD_COUNT                      0x1
#define GPIO_AG_VM_03_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_03_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_03_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_03_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_VM_03_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM1_SHIFT)
#define GPIO_AG_VM_03_0_VM1_RANGE                       1:0
#define GPIO_AG_VM_03_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AG_VM_03_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_VM_03_0_VM1_WOFFSET                     0x0
#define GPIO_AG_VM_03_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_03_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AG_VM_03_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM2_SHIFT)
#define GPIO_AG_VM_03_0_VM2_RANGE                       3:2
#define GPIO_AG_VM_03_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AG_VM_03_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AG_VM_03_0_VM2_WOFFSET                     0x0
#define GPIO_AG_VM_03_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_03_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AG_VM_03_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM3_SHIFT)
#define GPIO_AG_VM_03_0_VM3_RANGE                       5:4
#define GPIO_AG_VM_03_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AG_VM_03_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AG_VM_03_0_VM3_WOFFSET                     0x0
#define GPIO_AG_VM_03_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_03_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AG_VM_03_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM4_SHIFT)
#define GPIO_AG_VM_03_0_VM4_RANGE                       7:6
#define GPIO_AG_VM_03_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_VM_03_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AG_VM_03_0_VM4_WOFFSET                     0x0
#define GPIO_AG_VM_03_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_03_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AG_VM_03_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM5_SHIFT)
#define GPIO_AG_VM_03_0_VM5_RANGE                       9:8
#define GPIO_AG_VM_03_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AG_VM_03_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AG_VM_03_0_VM5_WOFFSET                     0x0
#define GPIO_AG_VM_03_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_03_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AG_VM_03_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM6_SHIFT)
#define GPIO_AG_VM_03_0_VM6_RANGE                       11:10
#define GPIO_AG_VM_03_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AG_VM_03_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AG_VM_03_0_VM6_WOFFSET                     0x0
#define GPIO_AG_VM_03_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_03_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AG_VM_03_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM7_SHIFT)
#define GPIO_AG_VM_03_0_VM7_RANGE                       13:12
#define GPIO_AG_VM_03_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AG_VM_03_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AG_VM_03_0_VM7_WOFFSET                     0x0
#define GPIO_AG_VM_03_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_03_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AG_VM_03_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM8_SHIFT)
#define GPIO_AG_VM_03_0_VM8_RANGE                       15:14
#define GPIO_AG_VM_03_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AG_VM_03_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AG_VM_03_0_VM8_WOFFSET                     0x0
#define GPIO_AG_VM_03_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_03_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_03_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_SCR_03_0
#define GPIO_AG_SCR_03_0                        MK_ADDR_CONST(0x309c)
#define GPIO_AG_SCR_03_0_SECURE                         0x0
#define GPIO_AG_SCR_03_0_DUAL                   0x0
#define GPIO_AG_SCR_03_0_SCR                    0
#define GPIO_AG_SCR_03_0_SCRREG                         0
#define GPIO_AG_SCR_03_0_WORD_COUNT                     0x1
#define GPIO_AG_SCR_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_03_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_03_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_03_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_AG_SCR_03_0_SEC_LCK_RANGE                  29:29
#define GPIO_AG_SCR_03_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_03_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_03_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AG_SCR_03_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_03_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_AG_SCR_03_0_SEC_WEN_RANGE                  28:28
#define GPIO_AG_SCR_03_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_03_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_03_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AG_SCR_03_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_03_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_AG_SCR_03_0_SEC_REN_RANGE                  27:27
#define GPIO_AG_SCR_03_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_03_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_03_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AG_SCR_03_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_03_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_AG_SCR_03_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AG_SCR_03_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AG_SCR_03_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AG_SCR_03_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AG_SCR_03_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_03_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR7_SHIFT)
#define GPIO_AG_SCR_03_0_PR7_RANGE                      23:23
#define GPIO_AG_SCR_03_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_03_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_03_0_PR7_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_03_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR6_SHIFT)
#define GPIO_AG_SCR_03_0_PR6_RANGE                      22:22
#define GPIO_AG_SCR_03_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_03_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_03_0_PR6_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_03_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR5_SHIFT)
#define GPIO_AG_SCR_03_0_PR5_RANGE                      21:21
#define GPIO_AG_SCR_03_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_03_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_03_0_PR5_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_03_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR4_SHIFT)
#define GPIO_AG_SCR_03_0_PR4_RANGE                      20:20
#define GPIO_AG_SCR_03_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_03_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_03_0_PR4_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_03_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR3_SHIFT)
#define GPIO_AG_SCR_03_0_PR3_RANGE                      19:19
#define GPIO_AG_SCR_03_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_03_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_03_0_PR3_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_03_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR2_SHIFT)
#define GPIO_AG_SCR_03_0_PR2_RANGE                      18:18
#define GPIO_AG_SCR_03_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_03_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_03_0_PR2_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_03_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR1_SHIFT)
#define GPIO_AG_SCR_03_0_PR1_RANGE                      17:17
#define GPIO_AG_SCR_03_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_03_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_03_0_PR1_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_03_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR0_SHIFT)
#define GPIO_AG_SCR_03_0_PR0_RANGE                      16:16
#define GPIO_AG_SCR_03_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_03_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_03_0_PR0_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_03_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G7W_SHIFT)
#define GPIO_AG_SCR_03_0_G7W_RANGE                      15:15
#define GPIO_AG_SCR_03_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_03_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_03_0_G7W_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_03_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G6W_SHIFT)
#define GPIO_AG_SCR_03_0_G6W_RANGE                      14:14
#define GPIO_AG_SCR_03_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_03_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_03_0_G6W_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_03_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G5W_SHIFT)
#define GPIO_AG_SCR_03_0_G5W_RANGE                      13:13
#define GPIO_AG_SCR_03_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_03_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_03_0_G5W_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_03_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G4W_SHIFT)
#define GPIO_AG_SCR_03_0_G4W_RANGE                      12:12
#define GPIO_AG_SCR_03_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_03_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_03_0_G4W_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_03_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G3W_SHIFT)
#define GPIO_AG_SCR_03_0_G3W_RANGE                      11:11
#define GPIO_AG_SCR_03_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_03_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_03_0_G3W_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_03_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G2W_SHIFT)
#define GPIO_AG_SCR_03_0_G2W_RANGE                      10:10
#define GPIO_AG_SCR_03_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_03_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_03_0_G2W_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_03_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G1W_SHIFT)
#define GPIO_AG_SCR_03_0_G1W_RANGE                      9:9
#define GPIO_AG_SCR_03_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_03_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_03_0_G1W_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_03_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G0W_SHIFT)
#define GPIO_AG_SCR_03_0_G0W_RANGE                      8:8
#define GPIO_AG_SCR_03_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_03_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_03_0_G0W_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_03_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G7R_SHIFT)
#define GPIO_AG_SCR_03_0_G7R_RANGE                      7:7
#define GPIO_AG_SCR_03_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_03_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_03_0_G7R_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_03_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G6R_SHIFT)
#define GPIO_AG_SCR_03_0_G6R_RANGE                      6:6
#define GPIO_AG_SCR_03_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_03_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_03_0_G6R_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_03_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G5R_SHIFT)
#define GPIO_AG_SCR_03_0_G5R_RANGE                      5:5
#define GPIO_AG_SCR_03_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_03_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_03_0_G5R_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_03_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G4R_SHIFT)
#define GPIO_AG_SCR_03_0_G4R_RANGE                      4:4
#define GPIO_AG_SCR_03_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_03_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_03_0_G4R_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_03_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G3R_SHIFT)
#define GPIO_AG_SCR_03_0_G3R_RANGE                      3:3
#define GPIO_AG_SCR_03_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_03_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_03_0_G3R_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_03_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G2R_SHIFT)
#define GPIO_AG_SCR_03_0_G2R_RANGE                      2:2
#define GPIO_AG_SCR_03_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_03_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_03_0_G2R_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_03_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G1R_SHIFT)
#define GPIO_AG_SCR_03_0_G1R_RANGE                      1:1
#define GPIO_AG_SCR_03_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_03_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_03_0_G1R_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_03_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_03_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G0R_SHIFT)
#define GPIO_AG_SCR_03_0_G0R_RANGE                      0:0
#define GPIO_AG_SCR_03_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_03_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_03_0_G0R_WOFFSET                    0x0
#define GPIO_AG_SCR_03_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_03_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_03_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AG_VM_04_0
#define GPIO_AG_VM_04_0                 MK_ADDR_CONST(0x30a0)
#define GPIO_AG_VM_04_0_SECURE                  0x0
#define GPIO_AG_VM_04_0_DUAL                    0x0
#define GPIO_AG_VM_04_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_04_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_04_0_WORD_COUNT                      0x1
#define GPIO_AG_VM_04_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_04_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_04_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_04_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_VM_04_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM1_SHIFT)
#define GPIO_AG_VM_04_0_VM1_RANGE                       1:0
#define GPIO_AG_VM_04_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AG_VM_04_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_VM_04_0_VM1_WOFFSET                     0x0
#define GPIO_AG_VM_04_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_04_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AG_VM_04_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM2_SHIFT)
#define GPIO_AG_VM_04_0_VM2_RANGE                       3:2
#define GPIO_AG_VM_04_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AG_VM_04_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AG_VM_04_0_VM2_WOFFSET                     0x0
#define GPIO_AG_VM_04_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_04_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AG_VM_04_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM3_SHIFT)
#define GPIO_AG_VM_04_0_VM3_RANGE                       5:4
#define GPIO_AG_VM_04_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AG_VM_04_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AG_VM_04_0_VM3_WOFFSET                     0x0
#define GPIO_AG_VM_04_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_04_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AG_VM_04_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM4_SHIFT)
#define GPIO_AG_VM_04_0_VM4_RANGE                       7:6
#define GPIO_AG_VM_04_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_VM_04_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AG_VM_04_0_VM4_WOFFSET                     0x0
#define GPIO_AG_VM_04_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_04_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AG_VM_04_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM5_SHIFT)
#define GPIO_AG_VM_04_0_VM5_RANGE                       9:8
#define GPIO_AG_VM_04_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AG_VM_04_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AG_VM_04_0_VM5_WOFFSET                     0x0
#define GPIO_AG_VM_04_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_04_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AG_VM_04_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM6_SHIFT)
#define GPIO_AG_VM_04_0_VM6_RANGE                       11:10
#define GPIO_AG_VM_04_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AG_VM_04_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AG_VM_04_0_VM6_WOFFSET                     0x0
#define GPIO_AG_VM_04_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_04_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AG_VM_04_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM7_SHIFT)
#define GPIO_AG_VM_04_0_VM7_RANGE                       13:12
#define GPIO_AG_VM_04_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AG_VM_04_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AG_VM_04_0_VM7_WOFFSET                     0x0
#define GPIO_AG_VM_04_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_04_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AG_VM_04_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM8_SHIFT)
#define GPIO_AG_VM_04_0_VM8_RANGE                       15:14
#define GPIO_AG_VM_04_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AG_VM_04_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AG_VM_04_0_VM8_WOFFSET                     0x0
#define GPIO_AG_VM_04_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_04_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_04_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_SCR_04_0
#define GPIO_AG_SCR_04_0                        MK_ADDR_CONST(0x30a4)
#define GPIO_AG_SCR_04_0_SECURE                         0x0
#define GPIO_AG_SCR_04_0_DUAL                   0x0
#define GPIO_AG_SCR_04_0_SCR                    0
#define GPIO_AG_SCR_04_0_SCRREG                         0
#define GPIO_AG_SCR_04_0_WORD_COUNT                     0x1
#define GPIO_AG_SCR_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_04_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_04_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_04_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_AG_SCR_04_0_SEC_LCK_RANGE                  29:29
#define GPIO_AG_SCR_04_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_04_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_04_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AG_SCR_04_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_04_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_AG_SCR_04_0_SEC_WEN_RANGE                  28:28
#define GPIO_AG_SCR_04_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_04_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_04_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AG_SCR_04_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_04_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_AG_SCR_04_0_SEC_REN_RANGE                  27:27
#define GPIO_AG_SCR_04_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_04_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_04_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AG_SCR_04_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_04_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_AG_SCR_04_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AG_SCR_04_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AG_SCR_04_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_04_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AG_SCR_04_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AG_SCR_04_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_04_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR7_SHIFT)
#define GPIO_AG_SCR_04_0_PR7_RANGE                      23:23
#define GPIO_AG_SCR_04_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_04_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_04_0_PR7_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_04_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR6_SHIFT)
#define GPIO_AG_SCR_04_0_PR6_RANGE                      22:22
#define GPIO_AG_SCR_04_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_04_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_04_0_PR6_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_04_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR5_SHIFT)
#define GPIO_AG_SCR_04_0_PR5_RANGE                      21:21
#define GPIO_AG_SCR_04_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_04_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_04_0_PR5_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_04_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR4_SHIFT)
#define GPIO_AG_SCR_04_0_PR4_RANGE                      20:20
#define GPIO_AG_SCR_04_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_04_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_04_0_PR4_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_04_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR3_SHIFT)
#define GPIO_AG_SCR_04_0_PR3_RANGE                      19:19
#define GPIO_AG_SCR_04_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_04_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_04_0_PR3_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_04_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR2_SHIFT)
#define GPIO_AG_SCR_04_0_PR2_RANGE                      18:18
#define GPIO_AG_SCR_04_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_04_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_04_0_PR2_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_04_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR1_SHIFT)
#define GPIO_AG_SCR_04_0_PR1_RANGE                      17:17
#define GPIO_AG_SCR_04_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_04_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_04_0_PR1_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_04_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR0_SHIFT)
#define GPIO_AG_SCR_04_0_PR0_RANGE                      16:16
#define GPIO_AG_SCR_04_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_04_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_04_0_PR0_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_04_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G7W_SHIFT)
#define GPIO_AG_SCR_04_0_G7W_RANGE                      15:15
#define GPIO_AG_SCR_04_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_04_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_04_0_G7W_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_04_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G6W_SHIFT)
#define GPIO_AG_SCR_04_0_G6W_RANGE                      14:14
#define GPIO_AG_SCR_04_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_04_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_04_0_G6W_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_04_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G5W_SHIFT)
#define GPIO_AG_SCR_04_0_G5W_RANGE                      13:13
#define GPIO_AG_SCR_04_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_04_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_04_0_G5W_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_04_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G4W_SHIFT)
#define GPIO_AG_SCR_04_0_G4W_RANGE                      12:12
#define GPIO_AG_SCR_04_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_04_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_04_0_G4W_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_04_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G3W_SHIFT)
#define GPIO_AG_SCR_04_0_G3W_RANGE                      11:11
#define GPIO_AG_SCR_04_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_04_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_04_0_G3W_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_04_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G2W_SHIFT)
#define GPIO_AG_SCR_04_0_G2W_RANGE                      10:10
#define GPIO_AG_SCR_04_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_04_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_04_0_G2W_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_04_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G1W_SHIFT)
#define GPIO_AG_SCR_04_0_G1W_RANGE                      9:9
#define GPIO_AG_SCR_04_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_04_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_04_0_G1W_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_04_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G0W_SHIFT)
#define GPIO_AG_SCR_04_0_G0W_RANGE                      8:8
#define GPIO_AG_SCR_04_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_04_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_04_0_G0W_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_04_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G7R_SHIFT)
#define GPIO_AG_SCR_04_0_G7R_RANGE                      7:7
#define GPIO_AG_SCR_04_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_04_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_04_0_G7R_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_04_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G6R_SHIFT)
#define GPIO_AG_SCR_04_0_G6R_RANGE                      6:6
#define GPIO_AG_SCR_04_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_04_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_04_0_G6R_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_04_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G5R_SHIFT)
#define GPIO_AG_SCR_04_0_G5R_RANGE                      5:5
#define GPIO_AG_SCR_04_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_04_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_04_0_G5R_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_04_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G4R_SHIFT)
#define GPIO_AG_SCR_04_0_G4R_RANGE                      4:4
#define GPIO_AG_SCR_04_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_04_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_04_0_G4R_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_04_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G3R_SHIFT)
#define GPIO_AG_SCR_04_0_G3R_RANGE                      3:3
#define GPIO_AG_SCR_04_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_04_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_04_0_G3R_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_04_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G2R_SHIFT)
#define GPIO_AG_SCR_04_0_G2R_RANGE                      2:2
#define GPIO_AG_SCR_04_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_04_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_04_0_G2R_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_04_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G1R_SHIFT)
#define GPIO_AG_SCR_04_0_G1R_RANGE                      1:1
#define GPIO_AG_SCR_04_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_04_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_04_0_G1R_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_04_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_04_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G0R_SHIFT)
#define GPIO_AG_SCR_04_0_G0R_RANGE                      0:0
#define GPIO_AG_SCR_04_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_04_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_04_0_G0R_WOFFSET                    0x0
#define GPIO_AG_SCR_04_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_04_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_04_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AG_VM_05_0
#define GPIO_AG_VM_05_0                 MK_ADDR_CONST(0x30a8)
#define GPIO_AG_VM_05_0_SECURE                  0x0
#define GPIO_AG_VM_05_0_DUAL                    0x0
#define GPIO_AG_VM_05_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_05_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_05_0_WORD_COUNT                      0x1
#define GPIO_AG_VM_05_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_05_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_05_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_05_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_VM_05_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM1_SHIFT)
#define GPIO_AG_VM_05_0_VM1_RANGE                       1:0
#define GPIO_AG_VM_05_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AG_VM_05_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_VM_05_0_VM1_WOFFSET                     0x0
#define GPIO_AG_VM_05_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_05_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AG_VM_05_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM2_SHIFT)
#define GPIO_AG_VM_05_0_VM2_RANGE                       3:2
#define GPIO_AG_VM_05_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AG_VM_05_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AG_VM_05_0_VM2_WOFFSET                     0x0
#define GPIO_AG_VM_05_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_05_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AG_VM_05_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM3_SHIFT)
#define GPIO_AG_VM_05_0_VM3_RANGE                       5:4
#define GPIO_AG_VM_05_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AG_VM_05_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AG_VM_05_0_VM3_WOFFSET                     0x0
#define GPIO_AG_VM_05_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_05_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AG_VM_05_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM4_SHIFT)
#define GPIO_AG_VM_05_0_VM4_RANGE                       7:6
#define GPIO_AG_VM_05_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_VM_05_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AG_VM_05_0_VM4_WOFFSET                     0x0
#define GPIO_AG_VM_05_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_05_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AG_VM_05_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM5_SHIFT)
#define GPIO_AG_VM_05_0_VM5_RANGE                       9:8
#define GPIO_AG_VM_05_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AG_VM_05_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AG_VM_05_0_VM5_WOFFSET                     0x0
#define GPIO_AG_VM_05_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_05_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AG_VM_05_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM6_SHIFT)
#define GPIO_AG_VM_05_0_VM6_RANGE                       11:10
#define GPIO_AG_VM_05_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AG_VM_05_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AG_VM_05_0_VM6_WOFFSET                     0x0
#define GPIO_AG_VM_05_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_05_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AG_VM_05_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM7_SHIFT)
#define GPIO_AG_VM_05_0_VM7_RANGE                       13:12
#define GPIO_AG_VM_05_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AG_VM_05_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AG_VM_05_0_VM7_WOFFSET                     0x0
#define GPIO_AG_VM_05_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_05_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AG_VM_05_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM8_SHIFT)
#define GPIO_AG_VM_05_0_VM8_RANGE                       15:14
#define GPIO_AG_VM_05_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AG_VM_05_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AG_VM_05_0_VM8_WOFFSET                     0x0
#define GPIO_AG_VM_05_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_05_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_05_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_SCR_05_0
#define GPIO_AG_SCR_05_0                        MK_ADDR_CONST(0x30ac)
#define GPIO_AG_SCR_05_0_SECURE                         0x0
#define GPIO_AG_SCR_05_0_DUAL                   0x0
#define GPIO_AG_SCR_05_0_SCR                    0
#define GPIO_AG_SCR_05_0_SCRREG                         0
#define GPIO_AG_SCR_05_0_WORD_COUNT                     0x1
#define GPIO_AG_SCR_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_05_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_05_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_05_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_AG_SCR_05_0_SEC_LCK_RANGE                  29:29
#define GPIO_AG_SCR_05_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_05_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_05_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AG_SCR_05_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_05_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_AG_SCR_05_0_SEC_WEN_RANGE                  28:28
#define GPIO_AG_SCR_05_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_05_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_05_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AG_SCR_05_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_05_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_AG_SCR_05_0_SEC_REN_RANGE                  27:27
#define GPIO_AG_SCR_05_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_05_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_05_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AG_SCR_05_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_05_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_AG_SCR_05_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AG_SCR_05_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AG_SCR_05_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_05_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AG_SCR_05_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AG_SCR_05_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_05_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR7_SHIFT)
#define GPIO_AG_SCR_05_0_PR7_RANGE                      23:23
#define GPIO_AG_SCR_05_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_05_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_05_0_PR7_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_05_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR6_SHIFT)
#define GPIO_AG_SCR_05_0_PR6_RANGE                      22:22
#define GPIO_AG_SCR_05_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_05_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_05_0_PR6_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_05_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR5_SHIFT)
#define GPIO_AG_SCR_05_0_PR5_RANGE                      21:21
#define GPIO_AG_SCR_05_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_05_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_05_0_PR5_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_05_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR4_SHIFT)
#define GPIO_AG_SCR_05_0_PR4_RANGE                      20:20
#define GPIO_AG_SCR_05_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_05_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_05_0_PR4_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_05_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR3_SHIFT)
#define GPIO_AG_SCR_05_0_PR3_RANGE                      19:19
#define GPIO_AG_SCR_05_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_05_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_05_0_PR3_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_05_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR2_SHIFT)
#define GPIO_AG_SCR_05_0_PR2_RANGE                      18:18
#define GPIO_AG_SCR_05_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_05_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_05_0_PR2_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_05_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR1_SHIFT)
#define GPIO_AG_SCR_05_0_PR1_RANGE                      17:17
#define GPIO_AG_SCR_05_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_05_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_05_0_PR1_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_05_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR0_SHIFT)
#define GPIO_AG_SCR_05_0_PR0_RANGE                      16:16
#define GPIO_AG_SCR_05_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_05_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_05_0_PR0_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_05_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G7W_SHIFT)
#define GPIO_AG_SCR_05_0_G7W_RANGE                      15:15
#define GPIO_AG_SCR_05_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_05_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_05_0_G7W_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_05_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G6W_SHIFT)
#define GPIO_AG_SCR_05_0_G6W_RANGE                      14:14
#define GPIO_AG_SCR_05_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_05_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_05_0_G6W_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_05_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G5W_SHIFT)
#define GPIO_AG_SCR_05_0_G5W_RANGE                      13:13
#define GPIO_AG_SCR_05_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_05_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_05_0_G5W_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_05_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G4W_SHIFT)
#define GPIO_AG_SCR_05_0_G4W_RANGE                      12:12
#define GPIO_AG_SCR_05_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_05_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_05_0_G4W_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_05_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G3W_SHIFT)
#define GPIO_AG_SCR_05_0_G3W_RANGE                      11:11
#define GPIO_AG_SCR_05_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_05_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_05_0_G3W_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_05_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G2W_SHIFT)
#define GPIO_AG_SCR_05_0_G2W_RANGE                      10:10
#define GPIO_AG_SCR_05_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_05_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_05_0_G2W_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_05_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G1W_SHIFT)
#define GPIO_AG_SCR_05_0_G1W_RANGE                      9:9
#define GPIO_AG_SCR_05_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_05_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_05_0_G1W_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_05_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G0W_SHIFT)
#define GPIO_AG_SCR_05_0_G0W_RANGE                      8:8
#define GPIO_AG_SCR_05_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_05_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_05_0_G0W_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_05_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G7R_SHIFT)
#define GPIO_AG_SCR_05_0_G7R_RANGE                      7:7
#define GPIO_AG_SCR_05_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_05_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_05_0_G7R_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_05_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G6R_SHIFT)
#define GPIO_AG_SCR_05_0_G6R_RANGE                      6:6
#define GPIO_AG_SCR_05_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_05_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_05_0_G6R_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_05_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G5R_SHIFT)
#define GPIO_AG_SCR_05_0_G5R_RANGE                      5:5
#define GPIO_AG_SCR_05_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_05_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_05_0_G5R_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_05_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G4R_SHIFT)
#define GPIO_AG_SCR_05_0_G4R_RANGE                      4:4
#define GPIO_AG_SCR_05_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_05_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_05_0_G4R_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_05_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G3R_SHIFT)
#define GPIO_AG_SCR_05_0_G3R_RANGE                      3:3
#define GPIO_AG_SCR_05_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_05_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_05_0_G3R_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_05_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G2R_SHIFT)
#define GPIO_AG_SCR_05_0_G2R_RANGE                      2:2
#define GPIO_AG_SCR_05_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_05_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_05_0_G2R_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_05_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G1R_SHIFT)
#define GPIO_AG_SCR_05_0_G1R_RANGE                      1:1
#define GPIO_AG_SCR_05_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_05_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_05_0_G1R_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_05_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_05_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G0R_SHIFT)
#define GPIO_AG_SCR_05_0_G0R_RANGE                      0:0
#define GPIO_AG_SCR_05_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_05_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_05_0_G0R_WOFFSET                    0x0
#define GPIO_AG_SCR_05_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_05_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_05_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AG_VM_06_0
#define GPIO_AG_VM_06_0                 MK_ADDR_CONST(0x30b0)
#define GPIO_AG_VM_06_0_SECURE                  0x0
#define GPIO_AG_VM_06_0_DUAL                    0x0
#define GPIO_AG_VM_06_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_06_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_06_0_WORD_COUNT                      0x1
#define GPIO_AG_VM_06_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_06_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_06_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_06_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_VM_06_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM1_SHIFT)
#define GPIO_AG_VM_06_0_VM1_RANGE                       1:0
#define GPIO_AG_VM_06_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AG_VM_06_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_VM_06_0_VM1_WOFFSET                     0x0
#define GPIO_AG_VM_06_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_06_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AG_VM_06_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM2_SHIFT)
#define GPIO_AG_VM_06_0_VM2_RANGE                       3:2
#define GPIO_AG_VM_06_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AG_VM_06_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AG_VM_06_0_VM2_WOFFSET                     0x0
#define GPIO_AG_VM_06_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_06_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AG_VM_06_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM3_SHIFT)
#define GPIO_AG_VM_06_0_VM3_RANGE                       5:4
#define GPIO_AG_VM_06_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AG_VM_06_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AG_VM_06_0_VM3_WOFFSET                     0x0
#define GPIO_AG_VM_06_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_06_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AG_VM_06_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM4_SHIFT)
#define GPIO_AG_VM_06_0_VM4_RANGE                       7:6
#define GPIO_AG_VM_06_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_VM_06_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AG_VM_06_0_VM4_WOFFSET                     0x0
#define GPIO_AG_VM_06_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_06_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AG_VM_06_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM5_SHIFT)
#define GPIO_AG_VM_06_0_VM5_RANGE                       9:8
#define GPIO_AG_VM_06_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AG_VM_06_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AG_VM_06_0_VM5_WOFFSET                     0x0
#define GPIO_AG_VM_06_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_06_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AG_VM_06_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM6_SHIFT)
#define GPIO_AG_VM_06_0_VM6_RANGE                       11:10
#define GPIO_AG_VM_06_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AG_VM_06_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AG_VM_06_0_VM6_WOFFSET                     0x0
#define GPIO_AG_VM_06_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_06_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AG_VM_06_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM7_SHIFT)
#define GPIO_AG_VM_06_0_VM7_RANGE                       13:12
#define GPIO_AG_VM_06_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AG_VM_06_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AG_VM_06_0_VM7_WOFFSET                     0x0
#define GPIO_AG_VM_06_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_06_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AG_VM_06_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM8_SHIFT)
#define GPIO_AG_VM_06_0_VM8_RANGE                       15:14
#define GPIO_AG_VM_06_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AG_VM_06_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AG_VM_06_0_VM8_WOFFSET                     0x0
#define GPIO_AG_VM_06_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_06_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_06_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_SCR_06_0
#define GPIO_AG_SCR_06_0                        MK_ADDR_CONST(0x30b4)
#define GPIO_AG_SCR_06_0_SECURE                         0x0
#define GPIO_AG_SCR_06_0_DUAL                   0x0
#define GPIO_AG_SCR_06_0_SCR                    0
#define GPIO_AG_SCR_06_0_SCRREG                         0
#define GPIO_AG_SCR_06_0_WORD_COUNT                     0x1
#define GPIO_AG_SCR_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_06_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_06_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_06_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_AG_SCR_06_0_SEC_LCK_RANGE                  29:29
#define GPIO_AG_SCR_06_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_06_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_06_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AG_SCR_06_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_06_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_AG_SCR_06_0_SEC_WEN_RANGE                  28:28
#define GPIO_AG_SCR_06_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_06_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_06_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AG_SCR_06_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_06_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_AG_SCR_06_0_SEC_REN_RANGE                  27:27
#define GPIO_AG_SCR_06_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_06_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_06_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AG_SCR_06_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_06_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_AG_SCR_06_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AG_SCR_06_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AG_SCR_06_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_06_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AG_SCR_06_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AG_SCR_06_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_06_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR7_SHIFT)
#define GPIO_AG_SCR_06_0_PR7_RANGE                      23:23
#define GPIO_AG_SCR_06_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_06_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_06_0_PR7_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_06_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR6_SHIFT)
#define GPIO_AG_SCR_06_0_PR6_RANGE                      22:22
#define GPIO_AG_SCR_06_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_06_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_06_0_PR6_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_06_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR5_SHIFT)
#define GPIO_AG_SCR_06_0_PR5_RANGE                      21:21
#define GPIO_AG_SCR_06_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_06_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_06_0_PR5_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_06_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR4_SHIFT)
#define GPIO_AG_SCR_06_0_PR4_RANGE                      20:20
#define GPIO_AG_SCR_06_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_06_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_06_0_PR4_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_06_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR3_SHIFT)
#define GPIO_AG_SCR_06_0_PR3_RANGE                      19:19
#define GPIO_AG_SCR_06_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_06_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_06_0_PR3_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_06_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR2_SHIFT)
#define GPIO_AG_SCR_06_0_PR2_RANGE                      18:18
#define GPIO_AG_SCR_06_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_06_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_06_0_PR2_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_06_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR1_SHIFT)
#define GPIO_AG_SCR_06_0_PR1_RANGE                      17:17
#define GPIO_AG_SCR_06_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_06_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_06_0_PR1_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_06_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR0_SHIFT)
#define GPIO_AG_SCR_06_0_PR0_RANGE                      16:16
#define GPIO_AG_SCR_06_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_06_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_06_0_PR0_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_06_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G7W_SHIFT)
#define GPIO_AG_SCR_06_0_G7W_RANGE                      15:15
#define GPIO_AG_SCR_06_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_06_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_06_0_G7W_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_06_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G6W_SHIFT)
#define GPIO_AG_SCR_06_0_G6W_RANGE                      14:14
#define GPIO_AG_SCR_06_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_06_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_06_0_G6W_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_06_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G5W_SHIFT)
#define GPIO_AG_SCR_06_0_G5W_RANGE                      13:13
#define GPIO_AG_SCR_06_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_06_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_06_0_G5W_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_06_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G4W_SHIFT)
#define GPIO_AG_SCR_06_0_G4W_RANGE                      12:12
#define GPIO_AG_SCR_06_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_06_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_06_0_G4W_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_06_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G3W_SHIFT)
#define GPIO_AG_SCR_06_0_G3W_RANGE                      11:11
#define GPIO_AG_SCR_06_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_06_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_06_0_G3W_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_06_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G2W_SHIFT)
#define GPIO_AG_SCR_06_0_G2W_RANGE                      10:10
#define GPIO_AG_SCR_06_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_06_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_06_0_G2W_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_06_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G1W_SHIFT)
#define GPIO_AG_SCR_06_0_G1W_RANGE                      9:9
#define GPIO_AG_SCR_06_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_06_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_06_0_G1W_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_06_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G0W_SHIFT)
#define GPIO_AG_SCR_06_0_G0W_RANGE                      8:8
#define GPIO_AG_SCR_06_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_06_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_06_0_G0W_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_06_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G7R_SHIFT)
#define GPIO_AG_SCR_06_0_G7R_RANGE                      7:7
#define GPIO_AG_SCR_06_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_06_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_06_0_G7R_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_06_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G6R_SHIFT)
#define GPIO_AG_SCR_06_0_G6R_RANGE                      6:6
#define GPIO_AG_SCR_06_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_06_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_06_0_G6R_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_06_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G5R_SHIFT)
#define GPIO_AG_SCR_06_0_G5R_RANGE                      5:5
#define GPIO_AG_SCR_06_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_06_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_06_0_G5R_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_06_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G4R_SHIFT)
#define GPIO_AG_SCR_06_0_G4R_RANGE                      4:4
#define GPIO_AG_SCR_06_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_06_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_06_0_G4R_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_06_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G3R_SHIFT)
#define GPIO_AG_SCR_06_0_G3R_RANGE                      3:3
#define GPIO_AG_SCR_06_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_06_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_06_0_G3R_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_06_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G2R_SHIFT)
#define GPIO_AG_SCR_06_0_G2R_RANGE                      2:2
#define GPIO_AG_SCR_06_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_06_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_06_0_G2R_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_06_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G1R_SHIFT)
#define GPIO_AG_SCR_06_0_G1R_RANGE                      1:1
#define GPIO_AG_SCR_06_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_06_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_06_0_G1R_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_06_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_06_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G0R_SHIFT)
#define GPIO_AG_SCR_06_0_G0R_RANGE                      0:0
#define GPIO_AG_SCR_06_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_06_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_06_0_G0R_WOFFSET                    0x0
#define GPIO_AG_SCR_06_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_06_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_06_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AG_VM_07_0
#define GPIO_AG_VM_07_0                 MK_ADDR_CONST(0x30b8)
#define GPIO_AG_VM_07_0_SECURE                  0x0
#define GPIO_AG_VM_07_0_DUAL                    0x0
#define GPIO_AG_VM_07_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_07_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AG_VM_07_0_WORD_COUNT                      0x1
#define GPIO_AG_VM_07_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_07_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_07_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AG_VM_07_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_VM_07_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM1_SHIFT)
#define GPIO_AG_VM_07_0_VM1_RANGE                       1:0
#define GPIO_AG_VM_07_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AG_VM_07_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_VM_07_0_VM1_WOFFSET                     0x0
#define GPIO_AG_VM_07_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_07_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AG_VM_07_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM2_SHIFT)
#define GPIO_AG_VM_07_0_VM2_RANGE                       3:2
#define GPIO_AG_VM_07_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AG_VM_07_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AG_VM_07_0_VM2_WOFFSET                     0x0
#define GPIO_AG_VM_07_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_07_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AG_VM_07_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM3_SHIFT)
#define GPIO_AG_VM_07_0_VM3_RANGE                       5:4
#define GPIO_AG_VM_07_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AG_VM_07_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AG_VM_07_0_VM3_WOFFSET                     0x0
#define GPIO_AG_VM_07_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_07_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AG_VM_07_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM4_SHIFT)
#define GPIO_AG_VM_07_0_VM4_RANGE                       7:6
#define GPIO_AG_VM_07_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_VM_07_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AG_VM_07_0_VM4_WOFFSET                     0x0
#define GPIO_AG_VM_07_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_07_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AG_VM_07_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM5_SHIFT)
#define GPIO_AG_VM_07_0_VM5_RANGE                       9:8
#define GPIO_AG_VM_07_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AG_VM_07_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AG_VM_07_0_VM5_WOFFSET                     0x0
#define GPIO_AG_VM_07_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_07_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AG_VM_07_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM6_SHIFT)
#define GPIO_AG_VM_07_0_VM6_RANGE                       11:10
#define GPIO_AG_VM_07_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AG_VM_07_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AG_VM_07_0_VM6_WOFFSET                     0x0
#define GPIO_AG_VM_07_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_07_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AG_VM_07_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM7_SHIFT)
#define GPIO_AG_VM_07_0_VM7_RANGE                       13:12
#define GPIO_AG_VM_07_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AG_VM_07_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AG_VM_07_0_VM7_WOFFSET                     0x0
#define GPIO_AG_VM_07_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AG_VM_07_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AG_VM_07_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM8_SHIFT)
#define GPIO_AG_VM_07_0_VM8_RANGE                       15:14
#define GPIO_AG_VM_07_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AG_VM_07_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AG_VM_07_0_VM8_WOFFSET                     0x0
#define GPIO_AG_VM_07_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AG_VM_07_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_VM_07_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_SCR_07_0
#define GPIO_AG_SCR_07_0                        MK_ADDR_CONST(0x30bc)
#define GPIO_AG_SCR_07_0_SECURE                         0x0
#define GPIO_AG_SCR_07_0_DUAL                   0x0
#define GPIO_AG_SCR_07_0_SCR                    0
#define GPIO_AG_SCR_07_0_SCRREG                         0
#define GPIO_AG_SCR_07_0_WORD_COUNT                     0x1
#define GPIO_AG_SCR_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_07_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AG_SCR_07_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_07_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_AG_SCR_07_0_SEC_LCK_RANGE                  29:29
#define GPIO_AG_SCR_07_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_07_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AG_SCR_07_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AG_SCR_07_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_07_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_AG_SCR_07_0_SEC_WEN_RANGE                  28:28
#define GPIO_AG_SCR_07_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_07_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AG_SCR_07_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AG_SCR_07_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_07_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_AG_SCR_07_0_SEC_REN_RANGE                  27:27
#define GPIO_AG_SCR_07_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_07_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AG_SCR_07_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AG_SCR_07_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_07_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_AG_SCR_07_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AG_SCR_07_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AG_SCR_07_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AG_SCR_07_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AG_SCR_07_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AG_SCR_07_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_07_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR7_SHIFT)
#define GPIO_AG_SCR_07_0_PR7_RANGE                      23:23
#define GPIO_AG_SCR_07_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_07_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AG_SCR_07_0_PR7_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_07_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR6_SHIFT)
#define GPIO_AG_SCR_07_0_PR6_RANGE                      22:22
#define GPIO_AG_SCR_07_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_07_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AG_SCR_07_0_PR6_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_07_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR5_SHIFT)
#define GPIO_AG_SCR_07_0_PR5_RANGE                      21:21
#define GPIO_AG_SCR_07_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_07_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AG_SCR_07_0_PR5_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_07_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR4_SHIFT)
#define GPIO_AG_SCR_07_0_PR4_RANGE                      20:20
#define GPIO_AG_SCR_07_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_07_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AG_SCR_07_0_PR4_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_07_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR3_SHIFT)
#define GPIO_AG_SCR_07_0_PR3_RANGE                      19:19
#define GPIO_AG_SCR_07_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_07_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AG_SCR_07_0_PR3_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_07_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR2_SHIFT)
#define GPIO_AG_SCR_07_0_PR2_RANGE                      18:18
#define GPIO_AG_SCR_07_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_07_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AG_SCR_07_0_PR2_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_07_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR1_SHIFT)
#define GPIO_AG_SCR_07_0_PR1_RANGE                      17:17
#define GPIO_AG_SCR_07_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_07_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AG_SCR_07_0_PR1_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_07_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR0_SHIFT)
#define GPIO_AG_SCR_07_0_PR0_RANGE                      16:16
#define GPIO_AG_SCR_07_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_07_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AG_SCR_07_0_PR0_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_07_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G7W_SHIFT)
#define GPIO_AG_SCR_07_0_G7W_RANGE                      15:15
#define GPIO_AG_SCR_07_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_07_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AG_SCR_07_0_G7W_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_07_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G6W_SHIFT)
#define GPIO_AG_SCR_07_0_G6W_RANGE                      14:14
#define GPIO_AG_SCR_07_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_07_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AG_SCR_07_0_G6W_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_07_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G5W_SHIFT)
#define GPIO_AG_SCR_07_0_G5W_RANGE                      13:13
#define GPIO_AG_SCR_07_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_07_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AG_SCR_07_0_G5W_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_07_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G4W_SHIFT)
#define GPIO_AG_SCR_07_0_G4W_RANGE                      12:12
#define GPIO_AG_SCR_07_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_07_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AG_SCR_07_0_G4W_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_07_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G3W_SHIFT)
#define GPIO_AG_SCR_07_0_G3W_RANGE                      11:11
#define GPIO_AG_SCR_07_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_07_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AG_SCR_07_0_G3W_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_07_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G2W_SHIFT)
#define GPIO_AG_SCR_07_0_G2W_RANGE                      10:10
#define GPIO_AG_SCR_07_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_07_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AG_SCR_07_0_G2W_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_07_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G1W_SHIFT)
#define GPIO_AG_SCR_07_0_G1W_RANGE                      9:9
#define GPIO_AG_SCR_07_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_07_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AG_SCR_07_0_G1W_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_07_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G0W_SHIFT)
#define GPIO_AG_SCR_07_0_G0W_RANGE                      8:8
#define GPIO_AG_SCR_07_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_07_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AG_SCR_07_0_G0W_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_07_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G7R_SHIFT)
#define GPIO_AG_SCR_07_0_G7R_RANGE                      7:7
#define GPIO_AG_SCR_07_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_07_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AG_SCR_07_0_G7R_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_07_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G6R_SHIFT)
#define GPIO_AG_SCR_07_0_G6R_RANGE                      6:6
#define GPIO_AG_SCR_07_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_07_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AG_SCR_07_0_G6R_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_07_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G5R_SHIFT)
#define GPIO_AG_SCR_07_0_G5R_RANGE                      5:5
#define GPIO_AG_SCR_07_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_07_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_SCR_07_0_G5R_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_07_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G4R_SHIFT)
#define GPIO_AG_SCR_07_0_G4R_RANGE                      4:4
#define GPIO_AG_SCR_07_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_07_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AG_SCR_07_0_G4R_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_07_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G3R_SHIFT)
#define GPIO_AG_SCR_07_0_G3R_RANGE                      3:3
#define GPIO_AG_SCR_07_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_07_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AG_SCR_07_0_G3R_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_07_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G2R_SHIFT)
#define GPIO_AG_SCR_07_0_G2R_RANGE                      2:2
#define GPIO_AG_SCR_07_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_07_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AG_SCR_07_0_G2R_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_07_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G1R_SHIFT)
#define GPIO_AG_SCR_07_0_G1R_RANGE                      1:1
#define GPIO_AG_SCR_07_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_07_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AG_SCR_07_0_G1R_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AG_SCR_07_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_07_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G0R_SHIFT)
#define GPIO_AG_SCR_07_0_G0R_RANGE                      0:0
#define GPIO_AG_SCR_07_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_07_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_SCR_07_0_G0R_WOFFSET                    0x0
#define GPIO_AG_SCR_07_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_SCR_07_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AG_SCR_07_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AE_VM_00_0
#define GPIO_AE_VM_00_0                 MK_ADDR_CONST(0x30c0)
#define GPIO_AE_VM_00_0_SECURE                  0x0
#define GPIO_AE_VM_00_0_DUAL                    0x0
#define GPIO_AE_VM_00_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AE_VM_00_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AE_VM_00_0_WORD_COUNT                      0x1
#define GPIO_AE_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AE_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AE_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AE_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AE_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM1_SHIFT)
#define GPIO_AE_VM_00_0_VM1_RANGE                       1:0
#define GPIO_AE_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_AE_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AE_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM2_SHIFT)
#define GPIO_AE_VM_00_0_VM2_RANGE                       3:2
#define GPIO_AE_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AE_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AE_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_AE_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AE_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM3_SHIFT)
#define GPIO_AE_VM_00_0_VM3_RANGE                       5:4
#define GPIO_AE_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AE_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AE_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_AE_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AE_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM4_SHIFT)
#define GPIO_AE_VM_00_0_VM4_RANGE                       7:6
#define GPIO_AE_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AE_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AE_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_AE_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AE_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM5_SHIFT)
#define GPIO_AE_VM_00_0_VM5_RANGE                       9:8
#define GPIO_AE_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AE_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AE_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_AE_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AE_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM6_SHIFT)
#define GPIO_AE_VM_00_0_VM6_RANGE                       11:10
#define GPIO_AE_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AE_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AE_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_AE_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AE_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM7_SHIFT)
#define GPIO_AE_VM_00_0_VM7_RANGE                       13:12
#define GPIO_AE_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AE_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AE_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_AE_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AE_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM8_SHIFT)
#define GPIO_AE_VM_00_0_VM8_RANGE                       15:14
#define GPIO_AE_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AE_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AE_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_AE_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_SCR_00_0
#define GPIO_AE_SCR_00_0                        MK_ADDR_CONST(0x30c4)
#define GPIO_AE_SCR_00_0_SECURE                         0x0
#define GPIO_AE_SCR_00_0_DUAL                   0x0
#define GPIO_AE_SCR_00_0_SCR                    0
#define GPIO_AE_SCR_00_0_SCRREG                         0
#define GPIO_AE_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_AE_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AE_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AE_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AE_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AE_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_AE_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_AE_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AE_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AE_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AE_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AE_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_AE_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_AE_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AE_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AE_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AE_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AE_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_AE_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_AE_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AE_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AE_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AE_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AE_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AE_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_AE_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AE_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AE_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AE_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AE_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AE_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AE_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR7_SHIFT)
#define GPIO_AE_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_AE_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AE_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AE_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AE_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR6_SHIFT)
#define GPIO_AE_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_AE_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AE_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AE_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AE_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR5_SHIFT)
#define GPIO_AE_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_AE_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AE_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AE_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AE_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR4_SHIFT)
#define GPIO_AE_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_AE_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AE_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AE_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AE_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR3_SHIFT)
#define GPIO_AE_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_AE_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AE_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AE_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AE_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR2_SHIFT)
#define GPIO_AE_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_AE_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AE_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AE_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AE_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR1_SHIFT)
#define GPIO_AE_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_AE_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AE_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AE_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AE_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR0_SHIFT)
#define GPIO_AE_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_AE_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AE_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AE_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AE_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G7W_SHIFT)
#define GPIO_AE_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_AE_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AE_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AE_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AE_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G6W_SHIFT)
#define GPIO_AE_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_AE_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AE_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AE_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AE_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G5W_SHIFT)
#define GPIO_AE_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_AE_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AE_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AE_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AE_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G4W_SHIFT)
#define GPIO_AE_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_AE_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AE_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AE_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AE_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G3W_SHIFT)
#define GPIO_AE_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_AE_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AE_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AE_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AE_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G2W_SHIFT)
#define GPIO_AE_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_AE_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AE_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AE_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AE_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G1W_SHIFT)
#define GPIO_AE_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_AE_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AE_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AE_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AE_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G0W_SHIFT)
#define GPIO_AE_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_AE_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AE_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AE_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AE_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G7R_SHIFT)
#define GPIO_AE_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_AE_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AE_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AE_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AE_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G6R_SHIFT)
#define GPIO_AE_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_AE_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AE_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AE_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AE_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G5R_SHIFT)
#define GPIO_AE_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_AE_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AE_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AE_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AE_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G4R_SHIFT)
#define GPIO_AE_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_AE_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AE_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AE_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AE_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G3R_SHIFT)
#define GPIO_AE_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_AE_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AE_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AE_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AE_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G2R_SHIFT)
#define GPIO_AE_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_AE_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AE_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AE_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AE_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G1R_SHIFT)
#define GPIO_AE_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_AE_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AE_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AE_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AE_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G0R_SHIFT)
#define GPIO_AE_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_AE_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AE_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AE_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_AE_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AE_VM_01_0
#define GPIO_AE_VM_01_0                 MK_ADDR_CONST(0x30c8)
#define GPIO_AE_VM_01_0_SECURE                  0x0
#define GPIO_AE_VM_01_0_DUAL                    0x0
#define GPIO_AE_VM_01_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AE_VM_01_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AE_VM_01_0_WORD_COUNT                      0x1
#define GPIO_AE_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AE_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AE_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AE_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AE_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM1_SHIFT)
#define GPIO_AE_VM_01_0_VM1_RANGE                       1:0
#define GPIO_AE_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_AE_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AE_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM2_SHIFT)
#define GPIO_AE_VM_01_0_VM2_RANGE                       3:2
#define GPIO_AE_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AE_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AE_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_AE_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AE_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM3_SHIFT)
#define GPIO_AE_VM_01_0_VM3_RANGE                       5:4
#define GPIO_AE_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AE_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AE_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_AE_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AE_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM4_SHIFT)
#define GPIO_AE_VM_01_0_VM4_RANGE                       7:6
#define GPIO_AE_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AE_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AE_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_AE_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AE_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM5_SHIFT)
#define GPIO_AE_VM_01_0_VM5_RANGE                       9:8
#define GPIO_AE_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AE_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AE_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_AE_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AE_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM6_SHIFT)
#define GPIO_AE_VM_01_0_VM6_RANGE                       11:10
#define GPIO_AE_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AE_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AE_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_AE_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AE_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM7_SHIFT)
#define GPIO_AE_VM_01_0_VM7_RANGE                       13:12
#define GPIO_AE_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AE_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AE_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_AE_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AE_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AE_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM8_SHIFT)
#define GPIO_AE_VM_01_0_VM8_RANGE                       15:14
#define GPIO_AE_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AE_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AE_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_AE_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_SCR_01_0
#define GPIO_AE_SCR_01_0                        MK_ADDR_CONST(0x30cc)
#define GPIO_AE_SCR_01_0_SECURE                         0x0
#define GPIO_AE_SCR_01_0_DUAL                   0x0
#define GPIO_AE_SCR_01_0_SCR                    0
#define GPIO_AE_SCR_01_0_SCRREG                         0
#define GPIO_AE_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_AE_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AE_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AE_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AE_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AE_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_AE_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_AE_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AE_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AE_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AE_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AE_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_AE_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_AE_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AE_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AE_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AE_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AE_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_AE_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_AE_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AE_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AE_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AE_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AE_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AE_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_AE_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AE_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AE_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AE_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AE_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AE_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AE_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR7_SHIFT)
#define GPIO_AE_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_AE_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AE_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AE_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AE_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR6_SHIFT)
#define GPIO_AE_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_AE_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AE_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AE_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AE_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR5_SHIFT)
#define GPIO_AE_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_AE_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AE_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AE_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AE_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR4_SHIFT)
#define GPIO_AE_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_AE_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AE_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AE_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AE_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR3_SHIFT)
#define GPIO_AE_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_AE_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AE_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AE_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AE_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR2_SHIFT)
#define GPIO_AE_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_AE_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AE_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AE_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AE_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR1_SHIFT)
#define GPIO_AE_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_AE_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AE_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AE_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AE_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR0_SHIFT)
#define GPIO_AE_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_AE_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AE_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AE_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AE_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G7W_SHIFT)
#define GPIO_AE_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_AE_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AE_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AE_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AE_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G6W_SHIFT)
#define GPIO_AE_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_AE_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AE_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AE_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AE_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G5W_SHIFT)
#define GPIO_AE_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_AE_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AE_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AE_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AE_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G4W_SHIFT)
#define GPIO_AE_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_AE_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AE_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AE_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AE_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G3W_SHIFT)
#define GPIO_AE_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_AE_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AE_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AE_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AE_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G2W_SHIFT)
#define GPIO_AE_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_AE_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AE_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AE_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AE_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G1W_SHIFT)
#define GPIO_AE_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_AE_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AE_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AE_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AE_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G0W_SHIFT)
#define GPIO_AE_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_AE_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AE_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AE_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AE_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G7R_SHIFT)
#define GPIO_AE_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_AE_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AE_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AE_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AE_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G6R_SHIFT)
#define GPIO_AE_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_AE_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AE_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AE_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AE_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G5R_SHIFT)
#define GPIO_AE_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_AE_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AE_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AE_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AE_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G4R_SHIFT)
#define GPIO_AE_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_AE_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AE_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AE_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AE_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G3R_SHIFT)
#define GPIO_AE_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_AE_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AE_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AE_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AE_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G2R_SHIFT)
#define GPIO_AE_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_AE_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AE_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AE_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AE_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G1R_SHIFT)
#define GPIO_AE_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_AE_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AE_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AE_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AE_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AE_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G0R_SHIFT)
#define GPIO_AE_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_AE_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AE_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AE_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_AE_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AE_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x30d0

// Reserved address 0x30d4

// Reserved address 0x30d8

// Reserved address 0x30dc

// Reserved address 0x30e0

// Reserved address 0x30e4

// Reserved address 0x30e8

// Reserved address 0x30ec

// Reserved address 0x30f0

// Reserved address 0x30f4

// Reserved address 0x30f8

// Reserved address 0x30fc

// Register GPIO_AF_VM_00_0
#define GPIO_AF_VM_00_0                 MK_ADDR_CONST(0x3100)
#define GPIO_AF_VM_00_0_SECURE                  0x0
#define GPIO_AF_VM_00_0_DUAL                    0x0
#define GPIO_AF_VM_00_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AF_VM_00_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AF_VM_00_0_WORD_COUNT                      0x1
#define GPIO_AF_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM1_SHIFT)
#define GPIO_AF_VM_00_0_VM1_RANGE                       1:0
#define GPIO_AF_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AF_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_VM_00_0_VM1_WOFFSET                     0x0
#define GPIO_AF_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AF_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM2_SHIFT)
#define GPIO_AF_VM_00_0_VM2_RANGE                       3:2
#define GPIO_AF_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AF_VM_00_0_VM2_WOFFSET                     0x0
#define GPIO_AF_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AF_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM3_SHIFT)
#define GPIO_AF_VM_00_0_VM3_RANGE                       5:4
#define GPIO_AF_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AF_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AF_VM_00_0_VM3_WOFFSET                     0x0
#define GPIO_AF_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AF_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM4_SHIFT)
#define GPIO_AF_VM_00_0_VM4_RANGE                       7:6
#define GPIO_AF_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AF_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AF_VM_00_0_VM4_WOFFSET                     0x0
#define GPIO_AF_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AF_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM5_SHIFT)
#define GPIO_AF_VM_00_0_VM5_RANGE                       9:8
#define GPIO_AF_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AF_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AF_VM_00_0_VM5_WOFFSET                     0x0
#define GPIO_AF_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AF_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM6_SHIFT)
#define GPIO_AF_VM_00_0_VM6_RANGE                       11:10
#define GPIO_AF_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AF_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AF_VM_00_0_VM6_WOFFSET                     0x0
#define GPIO_AF_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AF_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM7_SHIFT)
#define GPIO_AF_VM_00_0_VM7_RANGE                       13:12
#define GPIO_AF_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AF_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AF_VM_00_0_VM7_WOFFSET                     0x0
#define GPIO_AF_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AF_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM8_SHIFT)
#define GPIO_AF_VM_00_0_VM8_RANGE                       15:14
#define GPIO_AF_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AF_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AF_VM_00_0_VM8_WOFFSET                     0x0
#define GPIO_AF_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_SCR_00_0
#define GPIO_AF_SCR_00_0                        MK_ADDR_CONST(0x3104)
#define GPIO_AF_SCR_00_0_SECURE                         0x0
#define GPIO_AF_SCR_00_0_DUAL                   0x0
#define GPIO_AF_SCR_00_0_SCR                    0
#define GPIO_AF_SCR_00_0_SCRREG                         0
#define GPIO_AF_SCR_00_0_WORD_COUNT                     0x1
#define GPIO_AF_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_AF_SCR_00_0_SEC_LCK_RANGE                  29:29
#define GPIO_AF_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_00_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AF_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_AF_SCR_00_0_SEC_WEN_RANGE                  28:28
#define GPIO_AF_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_00_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AF_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_AF_SCR_00_0_SEC_REN_RANGE                  27:27
#define GPIO_AF_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_00_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AF_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AF_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AF_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_AF_SCR_00_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AF_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AF_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AF_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AF_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AF_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR7_SHIFT)
#define GPIO_AF_SCR_00_0_PR7_RANGE                      23:23
#define GPIO_AF_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_00_0_PR7_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR6_SHIFT)
#define GPIO_AF_SCR_00_0_PR6_RANGE                      22:22
#define GPIO_AF_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_00_0_PR6_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR5_SHIFT)
#define GPIO_AF_SCR_00_0_PR5_RANGE                      21:21
#define GPIO_AF_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_00_0_PR5_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR4_SHIFT)
#define GPIO_AF_SCR_00_0_PR4_RANGE                      20:20
#define GPIO_AF_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_00_0_PR4_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR3_SHIFT)
#define GPIO_AF_SCR_00_0_PR3_RANGE                      19:19
#define GPIO_AF_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_00_0_PR3_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR2_SHIFT)
#define GPIO_AF_SCR_00_0_PR2_RANGE                      18:18
#define GPIO_AF_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_00_0_PR2_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR1_SHIFT)
#define GPIO_AF_SCR_00_0_PR1_RANGE                      17:17
#define GPIO_AF_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_00_0_PR1_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR0_SHIFT)
#define GPIO_AF_SCR_00_0_PR0_RANGE                      16:16
#define GPIO_AF_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_00_0_PR0_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G7W_SHIFT)
#define GPIO_AF_SCR_00_0_G7W_RANGE                      15:15
#define GPIO_AF_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_00_0_G7W_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G6W_SHIFT)
#define GPIO_AF_SCR_00_0_G6W_RANGE                      14:14
#define GPIO_AF_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_00_0_G6W_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G5W_SHIFT)
#define GPIO_AF_SCR_00_0_G5W_RANGE                      13:13
#define GPIO_AF_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_00_0_G5W_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G4W_SHIFT)
#define GPIO_AF_SCR_00_0_G4W_RANGE                      12:12
#define GPIO_AF_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_00_0_G4W_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G3W_SHIFT)
#define GPIO_AF_SCR_00_0_G3W_RANGE                      11:11
#define GPIO_AF_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_00_0_G3W_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G2W_SHIFT)
#define GPIO_AF_SCR_00_0_G2W_RANGE                      10:10
#define GPIO_AF_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_00_0_G2W_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G1W_SHIFT)
#define GPIO_AF_SCR_00_0_G1W_RANGE                      9:9
#define GPIO_AF_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_00_0_G1W_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G0W_SHIFT)
#define GPIO_AF_SCR_00_0_G0W_RANGE                      8:8
#define GPIO_AF_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_00_0_G0W_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G7R_SHIFT)
#define GPIO_AF_SCR_00_0_G7R_RANGE                      7:7
#define GPIO_AF_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_00_0_G7R_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G6R_SHIFT)
#define GPIO_AF_SCR_00_0_G6R_RANGE                      6:6
#define GPIO_AF_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_00_0_G6R_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G5R_SHIFT)
#define GPIO_AF_SCR_00_0_G5R_RANGE                      5:5
#define GPIO_AF_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_00_0_G5R_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G4R_SHIFT)
#define GPIO_AF_SCR_00_0_G4R_RANGE                      4:4
#define GPIO_AF_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_00_0_G4R_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G3R_SHIFT)
#define GPIO_AF_SCR_00_0_G3R_RANGE                      3:3
#define GPIO_AF_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_00_0_G3R_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G2R_SHIFT)
#define GPIO_AF_SCR_00_0_G2R_RANGE                      2:2
#define GPIO_AF_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_00_0_G2R_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G1R_SHIFT)
#define GPIO_AF_SCR_00_0_G1R_RANGE                      1:1
#define GPIO_AF_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_00_0_G1R_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G0R_SHIFT)
#define GPIO_AF_SCR_00_0_G0R_RANGE                      0:0
#define GPIO_AF_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_00_0_G0R_WOFFSET                    0x0
#define GPIO_AF_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AF_VM_01_0
#define GPIO_AF_VM_01_0                 MK_ADDR_CONST(0x3108)
#define GPIO_AF_VM_01_0_SECURE                  0x0
#define GPIO_AF_VM_01_0_DUAL                    0x0
#define GPIO_AF_VM_01_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AF_VM_01_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AF_VM_01_0_WORD_COUNT                      0x1
#define GPIO_AF_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM1_SHIFT)
#define GPIO_AF_VM_01_0_VM1_RANGE                       1:0
#define GPIO_AF_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AF_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_VM_01_0_VM1_WOFFSET                     0x0
#define GPIO_AF_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AF_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM2_SHIFT)
#define GPIO_AF_VM_01_0_VM2_RANGE                       3:2
#define GPIO_AF_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AF_VM_01_0_VM2_WOFFSET                     0x0
#define GPIO_AF_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AF_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM3_SHIFT)
#define GPIO_AF_VM_01_0_VM3_RANGE                       5:4
#define GPIO_AF_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AF_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AF_VM_01_0_VM3_WOFFSET                     0x0
#define GPIO_AF_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AF_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM4_SHIFT)
#define GPIO_AF_VM_01_0_VM4_RANGE                       7:6
#define GPIO_AF_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AF_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AF_VM_01_0_VM4_WOFFSET                     0x0
#define GPIO_AF_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AF_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM5_SHIFT)
#define GPIO_AF_VM_01_0_VM5_RANGE                       9:8
#define GPIO_AF_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AF_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AF_VM_01_0_VM5_WOFFSET                     0x0
#define GPIO_AF_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AF_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM6_SHIFT)
#define GPIO_AF_VM_01_0_VM6_RANGE                       11:10
#define GPIO_AF_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AF_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AF_VM_01_0_VM6_WOFFSET                     0x0
#define GPIO_AF_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AF_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM7_SHIFT)
#define GPIO_AF_VM_01_0_VM7_RANGE                       13:12
#define GPIO_AF_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AF_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AF_VM_01_0_VM7_WOFFSET                     0x0
#define GPIO_AF_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AF_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM8_SHIFT)
#define GPIO_AF_VM_01_0_VM8_RANGE                       15:14
#define GPIO_AF_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AF_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AF_VM_01_0_VM8_WOFFSET                     0x0
#define GPIO_AF_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_SCR_01_0
#define GPIO_AF_SCR_01_0                        MK_ADDR_CONST(0x310c)
#define GPIO_AF_SCR_01_0_SECURE                         0x0
#define GPIO_AF_SCR_01_0_DUAL                   0x0
#define GPIO_AF_SCR_01_0_SCR                    0
#define GPIO_AF_SCR_01_0_SCRREG                         0
#define GPIO_AF_SCR_01_0_WORD_COUNT                     0x1
#define GPIO_AF_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_AF_SCR_01_0_SEC_LCK_RANGE                  29:29
#define GPIO_AF_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_01_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AF_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_AF_SCR_01_0_SEC_WEN_RANGE                  28:28
#define GPIO_AF_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_01_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AF_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_AF_SCR_01_0_SEC_REN_RANGE                  27:27
#define GPIO_AF_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_01_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AF_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AF_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AF_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_AF_SCR_01_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AF_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AF_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AF_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AF_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AF_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR7_SHIFT)
#define GPIO_AF_SCR_01_0_PR7_RANGE                      23:23
#define GPIO_AF_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_01_0_PR7_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR6_SHIFT)
#define GPIO_AF_SCR_01_0_PR6_RANGE                      22:22
#define GPIO_AF_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_01_0_PR6_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR5_SHIFT)
#define GPIO_AF_SCR_01_0_PR5_RANGE                      21:21
#define GPIO_AF_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_01_0_PR5_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR4_SHIFT)
#define GPIO_AF_SCR_01_0_PR4_RANGE                      20:20
#define GPIO_AF_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_01_0_PR4_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR3_SHIFT)
#define GPIO_AF_SCR_01_0_PR3_RANGE                      19:19
#define GPIO_AF_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_01_0_PR3_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR2_SHIFT)
#define GPIO_AF_SCR_01_0_PR2_RANGE                      18:18
#define GPIO_AF_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_01_0_PR2_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR1_SHIFT)
#define GPIO_AF_SCR_01_0_PR1_RANGE                      17:17
#define GPIO_AF_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_01_0_PR1_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR0_SHIFT)
#define GPIO_AF_SCR_01_0_PR0_RANGE                      16:16
#define GPIO_AF_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_01_0_PR0_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G7W_SHIFT)
#define GPIO_AF_SCR_01_0_G7W_RANGE                      15:15
#define GPIO_AF_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_01_0_G7W_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G6W_SHIFT)
#define GPIO_AF_SCR_01_0_G6W_RANGE                      14:14
#define GPIO_AF_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_01_0_G6W_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G5W_SHIFT)
#define GPIO_AF_SCR_01_0_G5W_RANGE                      13:13
#define GPIO_AF_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_01_0_G5W_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G4W_SHIFT)
#define GPIO_AF_SCR_01_0_G4W_RANGE                      12:12
#define GPIO_AF_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_01_0_G4W_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G3W_SHIFT)
#define GPIO_AF_SCR_01_0_G3W_RANGE                      11:11
#define GPIO_AF_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_01_0_G3W_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G2W_SHIFT)
#define GPIO_AF_SCR_01_0_G2W_RANGE                      10:10
#define GPIO_AF_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_01_0_G2W_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G1W_SHIFT)
#define GPIO_AF_SCR_01_0_G1W_RANGE                      9:9
#define GPIO_AF_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_01_0_G1W_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G0W_SHIFT)
#define GPIO_AF_SCR_01_0_G0W_RANGE                      8:8
#define GPIO_AF_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_01_0_G0W_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G7R_SHIFT)
#define GPIO_AF_SCR_01_0_G7R_RANGE                      7:7
#define GPIO_AF_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_01_0_G7R_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G6R_SHIFT)
#define GPIO_AF_SCR_01_0_G6R_RANGE                      6:6
#define GPIO_AF_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_01_0_G6R_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G5R_SHIFT)
#define GPIO_AF_SCR_01_0_G5R_RANGE                      5:5
#define GPIO_AF_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_01_0_G5R_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G4R_SHIFT)
#define GPIO_AF_SCR_01_0_G4R_RANGE                      4:4
#define GPIO_AF_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_01_0_G4R_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G3R_SHIFT)
#define GPIO_AF_SCR_01_0_G3R_RANGE                      3:3
#define GPIO_AF_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_01_0_G3R_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G2R_SHIFT)
#define GPIO_AF_SCR_01_0_G2R_RANGE                      2:2
#define GPIO_AF_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_01_0_G2R_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G1R_SHIFT)
#define GPIO_AF_SCR_01_0_G1R_RANGE                      1:1
#define GPIO_AF_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_01_0_G1R_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G0R_SHIFT)
#define GPIO_AF_SCR_01_0_G0R_RANGE                      0:0
#define GPIO_AF_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_01_0_G0R_WOFFSET                    0x0
#define GPIO_AF_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AF_VM_02_0
#define GPIO_AF_VM_02_0                 MK_ADDR_CONST(0x3110)
#define GPIO_AF_VM_02_0_SECURE                  0x0
#define GPIO_AF_VM_02_0_DUAL                    0x0
#define GPIO_AF_VM_02_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AF_VM_02_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AF_VM_02_0_WORD_COUNT                      0x1
#define GPIO_AF_VM_02_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_02_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_02_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_02_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_VM_02_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM1_SHIFT)
#define GPIO_AF_VM_02_0_VM1_RANGE                       1:0
#define GPIO_AF_VM_02_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AF_VM_02_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_VM_02_0_VM1_WOFFSET                     0x0
#define GPIO_AF_VM_02_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_02_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AF_VM_02_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM2_SHIFT)
#define GPIO_AF_VM_02_0_VM2_RANGE                       3:2
#define GPIO_AF_VM_02_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_VM_02_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AF_VM_02_0_VM2_WOFFSET                     0x0
#define GPIO_AF_VM_02_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_02_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AF_VM_02_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM3_SHIFT)
#define GPIO_AF_VM_02_0_VM3_RANGE                       5:4
#define GPIO_AF_VM_02_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AF_VM_02_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AF_VM_02_0_VM3_WOFFSET                     0x0
#define GPIO_AF_VM_02_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_02_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AF_VM_02_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM4_SHIFT)
#define GPIO_AF_VM_02_0_VM4_RANGE                       7:6
#define GPIO_AF_VM_02_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AF_VM_02_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AF_VM_02_0_VM4_WOFFSET                     0x0
#define GPIO_AF_VM_02_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_02_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AF_VM_02_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM5_SHIFT)
#define GPIO_AF_VM_02_0_VM5_RANGE                       9:8
#define GPIO_AF_VM_02_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AF_VM_02_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AF_VM_02_0_VM5_WOFFSET                     0x0
#define GPIO_AF_VM_02_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_02_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AF_VM_02_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM6_SHIFT)
#define GPIO_AF_VM_02_0_VM6_RANGE                       11:10
#define GPIO_AF_VM_02_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AF_VM_02_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AF_VM_02_0_VM6_WOFFSET                     0x0
#define GPIO_AF_VM_02_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_02_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AF_VM_02_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM7_SHIFT)
#define GPIO_AF_VM_02_0_VM7_RANGE                       13:12
#define GPIO_AF_VM_02_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AF_VM_02_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AF_VM_02_0_VM7_WOFFSET                     0x0
#define GPIO_AF_VM_02_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_02_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AF_VM_02_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM8_SHIFT)
#define GPIO_AF_VM_02_0_VM8_RANGE                       15:14
#define GPIO_AF_VM_02_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AF_VM_02_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AF_VM_02_0_VM8_WOFFSET                     0x0
#define GPIO_AF_VM_02_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_02_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_02_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_SCR_02_0
#define GPIO_AF_SCR_02_0                        MK_ADDR_CONST(0x3114)
#define GPIO_AF_SCR_02_0_SECURE                         0x0
#define GPIO_AF_SCR_02_0_DUAL                   0x0
#define GPIO_AF_SCR_02_0_SCR                    0
#define GPIO_AF_SCR_02_0_SCRREG                         0
#define GPIO_AF_SCR_02_0_WORD_COUNT                     0x1
#define GPIO_AF_SCR_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_02_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_02_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_02_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_AF_SCR_02_0_SEC_LCK_RANGE                  29:29
#define GPIO_AF_SCR_02_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_02_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_02_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AF_SCR_02_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_02_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_AF_SCR_02_0_SEC_WEN_RANGE                  28:28
#define GPIO_AF_SCR_02_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_02_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_02_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AF_SCR_02_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_02_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_AF_SCR_02_0_SEC_REN_RANGE                  27:27
#define GPIO_AF_SCR_02_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_02_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_02_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AF_SCR_02_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AF_SCR_02_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AF_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_AF_SCR_02_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AF_SCR_02_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AF_SCR_02_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AF_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AF_SCR_02_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AF_SCR_02_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_02_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR7_SHIFT)
#define GPIO_AF_SCR_02_0_PR7_RANGE                      23:23
#define GPIO_AF_SCR_02_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_02_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_02_0_PR7_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_02_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR6_SHIFT)
#define GPIO_AF_SCR_02_0_PR6_RANGE                      22:22
#define GPIO_AF_SCR_02_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_02_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_02_0_PR6_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_02_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR5_SHIFT)
#define GPIO_AF_SCR_02_0_PR5_RANGE                      21:21
#define GPIO_AF_SCR_02_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_02_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_02_0_PR5_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_02_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR4_SHIFT)
#define GPIO_AF_SCR_02_0_PR4_RANGE                      20:20
#define GPIO_AF_SCR_02_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_02_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_02_0_PR4_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_02_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR3_SHIFT)
#define GPIO_AF_SCR_02_0_PR3_RANGE                      19:19
#define GPIO_AF_SCR_02_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_02_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_02_0_PR3_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_02_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR2_SHIFT)
#define GPIO_AF_SCR_02_0_PR2_RANGE                      18:18
#define GPIO_AF_SCR_02_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_02_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_02_0_PR2_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_02_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR1_SHIFT)
#define GPIO_AF_SCR_02_0_PR1_RANGE                      17:17
#define GPIO_AF_SCR_02_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_02_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_02_0_PR1_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_02_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR0_SHIFT)
#define GPIO_AF_SCR_02_0_PR0_RANGE                      16:16
#define GPIO_AF_SCR_02_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_02_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_02_0_PR0_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_02_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G7W_SHIFT)
#define GPIO_AF_SCR_02_0_G7W_RANGE                      15:15
#define GPIO_AF_SCR_02_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_02_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_02_0_G7W_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_02_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G6W_SHIFT)
#define GPIO_AF_SCR_02_0_G6W_RANGE                      14:14
#define GPIO_AF_SCR_02_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_02_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_02_0_G6W_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_02_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G5W_SHIFT)
#define GPIO_AF_SCR_02_0_G5W_RANGE                      13:13
#define GPIO_AF_SCR_02_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_02_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_02_0_G5W_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_02_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G4W_SHIFT)
#define GPIO_AF_SCR_02_0_G4W_RANGE                      12:12
#define GPIO_AF_SCR_02_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_02_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_02_0_G4W_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_02_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G3W_SHIFT)
#define GPIO_AF_SCR_02_0_G3W_RANGE                      11:11
#define GPIO_AF_SCR_02_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_02_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_02_0_G3W_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_02_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G2W_SHIFT)
#define GPIO_AF_SCR_02_0_G2W_RANGE                      10:10
#define GPIO_AF_SCR_02_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_02_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_02_0_G2W_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_02_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G1W_SHIFT)
#define GPIO_AF_SCR_02_0_G1W_RANGE                      9:9
#define GPIO_AF_SCR_02_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_02_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_02_0_G1W_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_02_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G0W_SHIFT)
#define GPIO_AF_SCR_02_0_G0W_RANGE                      8:8
#define GPIO_AF_SCR_02_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_02_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_02_0_G0W_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_02_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G7R_SHIFT)
#define GPIO_AF_SCR_02_0_G7R_RANGE                      7:7
#define GPIO_AF_SCR_02_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_02_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_02_0_G7R_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_02_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G6R_SHIFT)
#define GPIO_AF_SCR_02_0_G6R_RANGE                      6:6
#define GPIO_AF_SCR_02_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_02_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_02_0_G6R_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_02_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G5R_SHIFT)
#define GPIO_AF_SCR_02_0_G5R_RANGE                      5:5
#define GPIO_AF_SCR_02_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_02_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_02_0_G5R_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_02_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G4R_SHIFT)
#define GPIO_AF_SCR_02_0_G4R_RANGE                      4:4
#define GPIO_AF_SCR_02_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_02_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_02_0_G4R_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_02_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G3R_SHIFT)
#define GPIO_AF_SCR_02_0_G3R_RANGE                      3:3
#define GPIO_AF_SCR_02_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_02_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_02_0_G3R_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_02_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G2R_SHIFT)
#define GPIO_AF_SCR_02_0_G2R_RANGE                      2:2
#define GPIO_AF_SCR_02_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_02_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_02_0_G2R_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_02_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G1R_SHIFT)
#define GPIO_AF_SCR_02_0_G1R_RANGE                      1:1
#define GPIO_AF_SCR_02_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_02_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_02_0_G1R_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_02_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_02_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G0R_SHIFT)
#define GPIO_AF_SCR_02_0_G0R_RANGE                      0:0
#define GPIO_AF_SCR_02_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_02_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_02_0_G0R_WOFFSET                    0x0
#define GPIO_AF_SCR_02_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_02_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_02_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Register GPIO_AF_VM_03_0
#define GPIO_AF_VM_03_0                 MK_ADDR_CONST(0x3118)
#define GPIO_AF_VM_03_0_SECURE                  0x0
#define GPIO_AF_VM_03_0_DUAL                    0x0
#define GPIO_AF_VM_03_0_SCR                     GPIO_CTL3_VM_SCR_0
#define GPIO_AF_VM_03_0_SCRREG                  GPIO_CTL3_VM_SCR_0
#define GPIO_AF_VM_03_0_WORD_COUNT                      0x1
#define GPIO_AF_VM_03_0_RESET_VAL                       MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_03_0_RESET_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_READ_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_03_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
#define GPIO_AF_VM_03_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_VM_03_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM1_SHIFT)
#define GPIO_AF_VM_03_0_VM1_RANGE                       1:0
#define GPIO_AF_VM_03_0_VM1_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AF_VM_03_0_VM1_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_VM_03_0_VM1_WOFFSET                     0x0
#define GPIO_AF_VM_03_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_03_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_AF_VM_03_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM2_SHIFT)
#define GPIO_AF_VM_03_0_VM2_RANGE                       3:2
#define GPIO_AF_VM_03_0_VM2_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_VM_03_0_VM2_LSB                 MK_SHIFT_CONST(2)
#define GPIO_AF_VM_03_0_VM2_WOFFSET                     0x0
#define GPIO_AF_VM_03_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_03_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_AF_VM_03_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM3_SHIFT)
#define GPIO_AF_VM_03_0_VM3_RANGE                       5:4
#define GPIO_AF_VM_03_0_VM3_MSB                 MK_SHIFT_CONST(5)
#define GPIO_AF_VM_03_0_VM3_LSB                 MK_SHIFT_CONST(4)
#define GPIO_AF_VM_03_0_VM3_WOFFSET                     0x0
#define GPIO_AF_VM_03_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_03_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_AF_VM_03_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM4_SHIFT)
#define GPIO_AF_VM_03_0_VM4_RANGE                       7:6
#define GPIO_AF_VM_03_0_VM4_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AF_VM_03_0_VM4_LSB                 MK_SHIFT_CONST(6)
#define GPIO_AF_VM_03_0_VM4_WOFFSET                     0x0
#define GPIO_AF_VM_03_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_03_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_AF_VM_03_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM5_SHIFT)
#define GPIO_AF_VM_03_0_VM5_RANGE                       9:8
#define GPIO_AF_VM_03_0_VM5_MSB                 MK_SHIFT_CONST(9)
#define GPIO_AF_VM_03_0_VM5_LSB                 MK_SHIFT_CONST(8)
#define GPIO_AF_VM_03_0_VM5_WOFFSET                     0x0
#define GPIO_AF_VM_03_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_03_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_AF_VM_03_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM6_SHIFT)
#define GPIO_AF_VM_03_0_VM6_RANGE                       11:10
#define GPIO_AF_VM_03_0_VM6_MSB                 MK_SHIFT_CONST(11)
#define GPIO_AF_VM_03_0_VM6_LSB                 MK_SHIFT_CONST(10)
#define GPIO_AF_VM_03_0_VM6_WOFFSET                     0x0
#define GPIO_AF_VM_03_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_03_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_AF_VM_03_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM7_SHIFT)
#define GPIO_AF_VM_03_0_VM7_RANGE                       13:12
#define GPIO_AF_VM_03_0_VM7_MSB                 MK_SHIFT_CONST(13)
#define GPIO_AF_VM_03_0_VM7_LSB                 MK_SHIFT_CONST(12)
#define GPIO_AF_VM_03_0_VM7_WOFFSET                     0x0
#define GPIO_AF_VM_03_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_AF_VM_03_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_AF_VM_03_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM8_SHIFT)
#define GPIO_AF_VM_03_0_VM8_RANGE                       15:14
#define GPIO_AF_VM_03_0_VM8_MSB                 MK_SHIFT_CONST(15)
#define GPIO_AF_VM_03_0_VM8_LSB                 MK_SHIFT_CONST(14)
#define GPIO_AF_VM_03_0_VM8_WOFFSET                     0x0
#define GPIO_AF_VM_03_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AF_VM_03_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_VM_03_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_SCR_03_0
#define GPIO_AF_SCR_03_0                        MK_ADDR_CONST(0x311c)
#define GPIO_AF_SCR_03_0_SECURE                         0x0
#define GPIO_AF_SCR_03_0_DUAL                   0x0
#define GPIO_AF_SCR_03_0_SCR                    0
#define GPIO_AF_SCR_03_0_SCRREG                         0
#define GPIO_AF_SCR_03_0_WORD_COUNT                     0x1
#define GPIO_AF_SCR_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_03_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
#define GPIO_AF_SCR_03_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_03_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_AF_SCR_03_0_SEC_LCK_RANGE                  29:29
#define GPIO_AF_SCR_03_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_03_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
#define GPIO_AF_SCR_03_0_SEC_LCK_WOFFSET                        0x0
#define GPIO_AF_SCR_03_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_03_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_AF_SCR_03_0_SEC_WEN_RANGE                  28:28
#define GPIO_AF_SCR_03_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_03_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
#define GPIO_AF_SCR_03_0_SEC_WEN_WOFFSET                        0x0
#define GPIO_AF_SCR_03_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_03_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_AF_SCR_03_0_SEC_REN_RANGE                  27:27
#define GPIO_AF_SCR_03_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_03_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
#define GPIO_AF_SCR_03_0_SEC_REN_WOFFSET                        0x0
#define GPIO_AF_SCR_03_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
#define GPIO_AF_SCR_03_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AF_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_AF_SCR_03_0_SEC_OWNER_RANGE                        26:24
#define GPIO_AF_SCR_03_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
#define GPIO_AF_SCR_03_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
#define GPIO_AF_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
#define GPIO_AF_SCR_03_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
#define GPIO_AF_SCR_03_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_03_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR7_SHIFT)
#define GPIO_AF_SCR_03_0_PR7_RANGE                      23:23
#define GPIO_AF_SCR_03_0_PR7_MSB                        MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_03_0_PR7_LSB                        MK_SHIFT_CONST(23)
#define GPIO_AF_SCR_03_0_PR7_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_03_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR6_SHIFT)
#define GPIO_AF_SCR_03_0_PR6_RANGE                      22:22
#define GPIO_AF_SCR_03_0_PR6_MSB                        MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_03_0_PR6_LSB                        MK_SHIFT_CONST(22)
#define GPIO_AF_SCR_03_0_PR6_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_03_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR5_SHIFT)
#define GPIO_AF_SCR_03_0_PR5_RANGE                      21:21
#define GPIO_AF_SCR_03_0_PR5_MSB                        MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_03_0_PR5_LSB                        MK_SHIFT_CONST(21)
#define GPIO_AF_SCR_03_0_PR5_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_03_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR4_SHIFT)
#define GPIO_AF_SCR_03_0_PR4_RANGE                      20:20
#define GPIO_AF_SCR_03_0_PR4_MSB                        MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_03_0_PR4_LSB                        MK_SHIFT_CONST(20)
#define GPIO_AF_SCR_03_0_PR4_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_03_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR3_SHIFT)
#define GPIO_AF_SCR_03_0_PR3_RANGE                      19:19
#define GPIO_AF_SCR_03_0_PR3_MSB                        MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_03_0_PR3_LSB                        MK_SHIFT_CONST(19)
#define GPIO_AF_SCR_03_0_PR3_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_03_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR2_SHIFT)
#define GPIO_AF_SCR_03_0_PR2_RANGE                      18:18
#define GPIO_AF_SCR_03_0_PR2_MSB                        MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_03_0_PR2_LSB                        MK_SHIFT_CONST(18)
#define GPIO_AF_SCR_03_0_PR2_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_03_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR1_SHIFT)
#define GPIO_AF_SCR_03_0_PR1_RANGE                      17:17
#define GPIO_AF_SCR_03_0_PR1_MSB                        MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_03_0_PR1_LSB                        MK_SHIFT_CONST(17)
#define GPIO_AF_SCR_03_0_PR1_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_03_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR0_SHIFT)
#define GPIO_AF_SCR_03_0_PR0_RANGE                      16:16
#define GPIO_AF_SCR_03_0_PR0_MSB                        MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_03_0_PR0_LSB                        MK_SHIFT_CONST(16)
#define GPIO_AF_SCR_03_0_PR0_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_03_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G7W_SHIFT)
#define GPIO_AF_SCR_03_0_G7W_RANGE                      15:15
#define GPIO_AF_SCR_03_0_G7W_MSB                        MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_03_0_G7W_LSB                        MK_SHIFT_CONST(15)
#define GPIO_AF_SCR_03_0_G7W_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_03_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G6W_SHIFT)
#define GPIO_AF_SCR_03_0_G6W_RANGE                      14:14
#define GPIO_AF_SCR_03_0_G6W_MSB                        MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_03_0_G6W_LSB                        MK_SHIFT_CONST(14)
#define GPIO_AF_SCR_03_0_G6W_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_03_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G5W_SHIFT)
#define GPIO_AF_SCR_03_0_G5W_RANGE                      13:13
#define GPIO_AF_SCR_03_0_G5W_MSB                        MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_03_0_G5W_LSB                        MK_SHIFT_CONST(13)
#define GPIO_AF_SCR_03_0_G5W_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_03_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G4W_SHIFT)
#define GPIO_AF_SCR_03_0_G4W_RANGE                      12:12
#define GPIO_AF_SCR_03_0_G4W_MSB                        MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_03_0_G4W_LSB                        MK_SHIFT_CONST(12)
#define GPIO_AF_SCR_03_0_G4W_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_03_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G3W_SHIFT)
#define GPIO_AF_SCR_03_0_G3W_RANGE                      11:11
#define GPIO_AF_SCR_03_0_G3W_MSB                        MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_03_0_G3W_LSB                        MK_SHIFT_CONST(11)
#define GPIO_AF_SCR_03_0_G3W_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_03_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G2W_SHIFT)
#define GPIO_AF_SCR_03_0_G2W_RANGE                      10:10
#define GPIO_AF_SCR_03_0_G2W_MSB                        MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_03_0_G2W_LSB                        MK_SHIFT_CONST(10)
#define GPIO_AF_SCR_03_0_G2W_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_03_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G1W_SHIFT)
#define GPIO_AF_SCR_03_0_G1W_RANGE                      9:9
#define GPIO_AF_SCR_03_0_G1W_MSB                        MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_03_0_G1W_LSB                        MK_SHIFT_CONST(9)
#define GPIO_AF_SCR_03_0_G1W_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_03_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G0W_SHIFT)
#define GPIO_AF_SCR_03_0_G0W_RANGE                      8:8
#define GPIO_AF_SCR_03_0_G0W_MSB                        MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_03_0_G0W_LSB                        MK_SHIFT_CONST(8)
#define GPIO_AF_SCR_03_0_G0W_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_03_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G7R_SHIFT)
#define GPIO_AF_SCR_03_0_G7R_RANGE                      7:7
#define GPIO_AF_SCR_03_0_G7R_MSB                        MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_03_0_G7R_LSB                        MK_SHIFT_CONST(7)
#define GPIO_AF_SCR_03_0_G7R_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_03_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G6R_SHIFT)
#define GPIO_AF_SCR_03_0_G6R_RANGE                      6:6
#define GPIO_AF_SCR_03_0_G6R_MSB                        MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_03_0_G6R_LSB                        MK_SHIFT_CONST(6)
#define GPIO_AF_SCR_03_0_G6R_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_03_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G5R_SHIFT)
#define GPIO_AF_SCR_03_0_G5R_RANGE                      5:5
#define GPIO_AF_SCR_03_0_G5R_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_03_0_G5R_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_SCR_03_0_G5R_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_03_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G4R_SHIFT)
#define GPIO_AF_SCR_03_0_G4R_RANGE                      4:4
#define GPIO_AF_SCR_03_0_G4R_MSB                        MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_03_0_G4R_LSB                        MK_SHIFT_CONST(4)
#define GPIO_AF_SCR_03_0_G4R_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_03_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G3R_SHIFT)
#define GPIO_AF_SCR_03_0_G3R_RANGE                      3:3
#define GPIO_AF_SCR_03_0_G3R_MSB                        MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_03_0_G3R_LSB                        MK_SHIFT_CONST(3)
#define GPIO_AF_SCR_03_0_G3R_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_03_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G2R_SHIFT)
#define GPIO_AF_SCR_03_0_G2R_RANGE                      2:2
#define GPIO_AF_SCR_03_0_G2R_MSB                        MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_03_0_G2R_LSB                        MK_SHIFT_CONST(2)
#define GPIO_AF_SCR_03_0_G2R_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_03_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G1R_SHIFT)
#define GPIO_AF_SCR_03_0_G1R_RANGE                      1:1
#define GPIO_AF_SCR_03_0_G1R_MSB                        MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_03_0_G1R_LSB                        MK_SHIFT_CONST(1)
#define GPIO_AF_SCR_03_0_G1R_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_AF_SCR_03_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_03_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G0R_SHIFT)
#define GPIO_AF_SCR_03_0_G0R_RANGE                      0:0
#define GPIO_AF_SCR_03_0_G0R_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_03_0_G0R_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_SCR_03_0_G0R_WOFFSET                    0x0
#define GPIO_AF_SCR_03_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_SCR_03_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_AF_SCR_03_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)


// Reserved address 0x3120

// Reserved address 0x3124

// Reserved address 0x3128

// Reserved address 0x312c

// Reserved address 0x3130

// Reserved address 0x3134

// Reserved address 0x3138

// Reserved address 0x313c

// Register GPIO_CTL3_VM_SCR_0
#define GPIO_CTL3_VM_SCR_0                      MK_ADDR_CONST(0x3800)
#define GPIO_CTL3_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL3_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL3_VM_SCR_0_SCR                  0
#define GPIO_CTL3_VM_SCR_0_SCRREG                       0
#define GPIO_CTL3_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL3_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL3_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL3_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL3_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define GPIO_CTL3_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL3_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL3_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL3_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define GPIO_CTL3_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL3_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL3_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL3_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define GPIO_CTL3_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL3_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL3_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL3_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define GPIO_CTL3_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL3_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL3_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL3_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define GPIO_CTL3_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL3_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL3_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL3_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define GPIO_CTL3_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL3_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL3_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL3_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define GPIO_CTL3_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL3_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL3_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL3_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define GPIO_CTL3_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL3_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL3_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL3_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define GPIO_CTL3_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL3_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL3_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL3_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define GPIO_CTL3_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL3_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL3_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL3_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define GPIO_CTL3_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL3_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL3_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL3_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define GPIO_CTL3_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL3_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL3_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL3_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define GPIO_CTL3_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL3_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL3_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL3_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define GPIO_CTL3_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL3_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL3_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL3_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define GPIO_CTL3_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL3_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL3_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL3_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define GPIO_CTL3_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL3_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL3_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL3_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define GPIO_CTL3_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL3_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL3_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL3_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define GPIO_CTL3_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL3_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL3_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL3_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define GPIO_CTL3_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL3_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL3_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL3_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define GPIO_CTL3_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL3_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL3_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL3_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define GPIO_CTL3_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL3_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL3_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL3_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_CTL3_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL3_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL3_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL3_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define GPIO_CTL3_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL3_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL3_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL3_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL3_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CTL3_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL3_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL3_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL3_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL3_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL3_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x3804)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL3_INTERRUPT_STATUS_VM_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x3808)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_CTL3_SCR_0
#define GPIO_CTL3_SCR_0                 MK_ADDR_CONST(0x380c)
#define GPIO_CTL3_SCR_0_SECURE                  0x0
#define GPIO_CTL3_SCR_0_DUAL                    0x0
#define GPIO_CTL3_SCR_0_SCR                     0
#define GPIO_CTL3_SCR_0_SCRREG                  0
#define GPIO_CTL3_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL3_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL3_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_CTL3_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL3_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL3_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL3_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_CTL3_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL3_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL3_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL3_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_CTL3_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL3_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL3_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL3_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL3_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_CTL3_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL3_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL3_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL3_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_CTL3_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_CTL3_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL3_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_CTL3_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_CTL3_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR7_SHIFT)
#define GPIO_CTL3_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL3_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL3_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL3_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_CTL3_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR6_SHIFT)
#define GPIO_CTL3_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL3_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL3_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL3_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_CTL3_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR5_SHIFT)
#define GPIO_CTL3_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL3_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL3_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL3_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_CTL3_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR4_SHIFT)
#define GPIO_CTL3_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL3_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL3_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL3_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_CTL3_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR3_SHIFT)
#define GPIO_CTL3_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL3_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL3_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL3_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_CTL3_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR2_SHIFT)
#define GPIO_CTL3_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL3_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL3_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL3_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_CTL3_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR1_SHIFT)
#define GPIO_CTL3_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL3_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL3_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL3_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_CTL3_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR0_SHIFT)
#define GPIO_CTL3_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL3_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL3_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL3_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_CTL3_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G7W_SHIFT)
#define GPIO_CTL3_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL3_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL3_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL3_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_CTL3_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G6W_SHIFT)
#define GPIO_CTL3_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL3_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL3_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL3_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_CTL3_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G5W_SHIFT)
#define GPIO_CTL3_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL3_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL3_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL3_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_CTL3_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G4W_SHIFT)
#define GPIO_CTL3_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL3_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL3_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL3_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_CTL3_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G3W_SHIFT)
#define GPIO_CTL3_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL3_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL3_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL3_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_CTL3_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G2W_SHIFT)
#define GPIO_CTL3_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL3_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL3_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL3_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_CTL3_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G1W_SHIFT)
#define GPIO_CTL3_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL3_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL3_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL3_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_CTL3_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G0W_SHIFT)
#define GPIO_CTL3_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL3_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL3_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL3_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_CTL3_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G7R_SHIFT)
#define GPIO_CTL3_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL3_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL3_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL3_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_CTL3_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G6R_SHIFT)
#define GPIO_CTL3_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL3_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL3_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL3_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_CTL3_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G5R_SHIFT)
#define GPIO_CTL3_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL3_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL3_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL3_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_CTL3_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G4R_SHIFT)
#define GPIO_CTL3_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL3_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL3_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL3_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_CTL3_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G3R_SHIFT)
#define GPIO_CTL3_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL3_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL3_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL3_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_CTL3_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G2R_SHIFT)
#define GPIO_CTL3_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL3_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL3_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL3_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_CTL3_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G1R_SHIFT)
#define GPIO_CTL3_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL3_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL3_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL3_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL3_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CTL3_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G0R_SHIFT)
#define GPIO_CTL3_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL3_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL3_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL3_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL3_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL3_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CTL3_ICG_EN_OVERRIDE_0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x3810)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_K_INT0_ROUTE_MAPPING_0
#define GPIO_K_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3814)
#define GPIO_K_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_K_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_K_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_K_INT1_ROUTE_MAPPING_0
#define GPIO_K_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3818)
#define GPIO_K_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_K_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_K_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_K_INT2_ROUTE_MAPPING_0
#define GPIO_K_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x381c)
#define GPIO_K_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_K_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_K_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_K_INT3_ROUTE_MAPPING_0
#define GPIO_K_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3820)
#define GPIO_K_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_K_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_K_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_K_INT4_ROUTE_MAPPING_0
#define GPIO_K_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3824)
#define GPIO_K_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_K_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_K_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_K_INT5_ROUTE_MAPPING_0
#define GPIO_K_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3828)
#define GPIO_K_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_K_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_K_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_K_INT6_ROUTE_MAPPING_0
#define GPIO_K_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x382c)
#define GPIO_K_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_K_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_K_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_K_INT7_ROUTE_MAPPING_0
#define GPIO_K_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3830)
#define GPIO_K_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_K_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_K_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_K_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_K_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_K_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_K_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_L_INT0_ROUTE_MAPPING_0
#define GPIO_L_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3834)
#define GPIO_L_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_L_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_L_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_L_INT1_ROUTE_MAPPING_0
#define GPIO_L_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3838)
#define GPIO_L_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_L_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_L_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_L_INT2_ROUTE_MAPPING_0
#define GPIO_L_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x383c)
#define GPIO_L_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_L_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_L_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_L_INT3_ROUTE_MAPPING_0
#define GPIO_L_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3840)
#define GPIO_L_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_L_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_L_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_L_INT4_ROUTE_MAPPING_0
#define GPIO_L_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3844)
#define GPIO_L_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_L_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_L_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_L_INT5_ROUTE_MAPPING_0
#define GPIO_L_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3848)
#define GPIO_L_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_L_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_L_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_L_INT6_ROUTE_MAPPING_0
#define GPIO_L_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x384c)
#define GPIO_L_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_L_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_L_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_L_INT7_ROUTE_MAPPING_0
#define GPIO_L_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3850)
#define GPIO_L_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_L_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_L_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
#define GPIO_L_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
#define GPIO_L_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_L_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_L_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_AG_INT0_ROUTE_MAPPING_0
#define GPIO_AG_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3854)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AG_INT0_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AG_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AG_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AG_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AG_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AG_INT1_ROUTE_MAPPING_0
#define GPIO_AG_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3858)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AG_INT1_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AG_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AG_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AG_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AG_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AG_INT2_ROUTE_MAPPING_0
#define GPIO_AG_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x385c)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AG_INT2_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AG_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AG_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AG_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AG_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AG_INT3_ROUTE_MAPPING_0
#define GPIO_AG_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3860)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AG_INT3_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AG_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AG_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AG_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AG_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AG_INT4_ROUTE_MAPPING_0
#define GPIO_AG_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3864)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AG_INT4_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AG_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AG_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AG_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AG_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AG_INT5_ROUTE_MAPPING_0
#define GPIO_AG_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3868)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AG_INT5_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AG_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AG_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AG_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AG_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AG_INT6_ROUTE_MAPPING_0
#define GPIO_AG_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x386c)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AG_INT6_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AG_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AG_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AG_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AG_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AG_INT7_ROUTE_MAPPING_0
#define GPIO_AG_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3870)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AG_INT7_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AG_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AG_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AG_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AG_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_RANGE                  7:0
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AE_INT0_ROUTE_MAPPING_0
#define GPIO_AE_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3874)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AE_INT0_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AE_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AE_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AE_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AE_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AE_INT1_ROUTE_MAPPING_0
#define GPIO_AE_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3878)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AE_INT1_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AE_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AE_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AE_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AE_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AE_INT2_ROUTE_MAPPING_0
#define GPIO_AE_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x387c)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AE_INT2_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AE_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AE_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AE_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AE_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AE_INT3_ROUTE_MAPPING_0
#define GPIO_AE_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3880)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AE_INT3_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AE_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AE_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AE_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AE_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AE_INT4_ROUTE_MAPPING_0
#define GPIO_AE_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3884)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AE_INT4_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AE_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AE_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AE_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AE_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AE_INT5_ROUTE_MAPPING_0
#define GPIO_AE_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3888)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AE_INT5_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AE_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AE_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AE_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AE_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AE_INT6_ROUTE_MAPPING_0
#define GPIO_AE_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x388c)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AE_INT6_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AE_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AE_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AE_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AE_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AE_INT7_ROUTE_MAPPING_0
#define GPIO_AE_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3890)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AE_INT7_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AE_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AE_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AE_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AE_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_RANGE                  1:0
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AF_INT0_ROUTE_MAPPING_0
#define GPIO_AF_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3894)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AF_INT0_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AF_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AF_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AF_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AF_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AF_INT1_ROUTE_MAPPING_0
#define GPIO_AF_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3898)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AF_INT1_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AF_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AF_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AF_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AF_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AF_INT2_ROUTE_MAPPING_0
#define GPIO_AF_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x389c)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AF_INT2_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AF_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AF_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AF_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AF_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AF_INT3_ROUTE_MAPPING_0
#define GPIO_AF_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38a0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AF_INT3_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AF_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AF_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AF_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AF_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AF_INT4_ROUTE_MAPPING_0
#define GPIO_AF_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38a4)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AF_INT4_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AF_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AF_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AF_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AF_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AF_INT5_ROUTE_MAPPING_0
#define GPIO_AF_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38a8)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AF_INT5_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AF_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AF_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AF_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AF_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AF_INT6_ROUTE_MAPPING_0
#define GPIO_AF_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38ac)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AF_INT6_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AF_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AF_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AF_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AF_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_AF_INT7_ROUTE_MAPPING_0
#define GPIO_AF_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38b0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_SECURE                     0x0
#define GPIO_AF_INT7_ROUTE_MAPPING_0_DUAL                       0x0
#define GPIO_AF_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
#define GPIO_AF_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
#define GPIO_AF_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
#define GPIO_AF_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_RANGE                  3:0
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_CTL3_SPARE_0
#define GPIO_CTL3_SPARE_0                       MK_ADDR_CONST(0x38b4)
#define GPIO_CTL3_SPARE_0_SECURE                        0x0
#define GPIO_CTL3_SPARE_0_DUAL                  0x0
#define GPIO_CTL3_SPARE_0_SCR                   0
#define GPIO_CTL3_SPARE_0_SCRREG                        0
#define GPIO_CTL3_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL3_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL3_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL3_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL3_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL3_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL3_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL3_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL3_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL3_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL3_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_G_VM_00_0
#define GPIO_G_VM_00_0                  MK_ADDR_CONST(0x4000)
#define GPIO_G_VM_00_0_SECURE                   0x0
#define GPIO_G_VM_00_0_DUAL                     0x0
#define GPIO_G_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_00_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_00_0_WORD_COUNT                       0x1
#define GPIO_G_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM1_SHIFT)
#define GPIO_G_VM_00_0_VM1_RANGE                        1:0
#define GPIO_G_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_G_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_G_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM2_SHIFT)
#define GPIO_G_VM_00_0_VM2_RANGE                        3:2
#define GPIO_G_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_G_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_G_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_G_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM3_SHIFT)
#define GPIO_G_VM_00_0_VM3_RANGE                        5:4
#define GPIO_G_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_G_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_G_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_G_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM4_SHIFT)
#define GPIO_G_VM_00_0_VM4_RANGE                        7:6
#define GPIO_G_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_G_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_G_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM5_SHIFT)
#define GPIO_G_VM_00_0_VM5_RANGE                        9:8
#define GPIO_G_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_G_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_G_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_G_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM6_SHIFT)
#define GPIO_G_VM_00_0_VM6_RANGE                        11:10
#define GPIO_G_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_G_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_G_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_G_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM7_SHIFT)
#define GPIO_G_VM_00_0_VM7_RANGE                        13:12
#define GPIO_G_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_G_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_G_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_G_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM8_SHIFT)
#define GPIO_G_VM_00_0_VM8_RANGE                        15:14
#define GPIO_G_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_G_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_G_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_00_0
#define GPIO_G_SCR_00_0                 MK_ADDR_CONST(0x4004)
#define GPIO_G_SCR_00_0_SECURE                  0x0
#define GPIO_G_SCR_00_0_DUAL                    0x0
#define GPIO_G_SCR_00_0_SCR                     0
#define GPIO_G_SCR_00_0_SCRREG                  0
#define GPIO_G_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_G_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_G_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_G_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_G_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_G_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_G_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_G_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_G_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR7_SHIFT)
#define GPIO_G_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_G_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR6_SHIFT)
#define GPIO_G_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_G_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR5_SHIFT)
#define GPIO_G_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_G_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR4_SHIFT)
#define GPIO_G_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_G_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR3_SHIFT)
#define GPIO_G_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_G_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR2_SHIFT)
#define GPIO_G_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_G_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR1_SHIFT)
#define GPIO_G_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_G_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR0_SHIFT)
#define GPIO_G_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_G_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G7W_SHIFT)
#define GPIO_G_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_G_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G6W_SHIFT)
#define GPIO_G_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_G_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G5W_SHIFT)
#define GPIO_G_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_G_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G4W_SHIFT)
#define GPIO_G_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_G_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G3W_SHIFT)
#define GPIO_G_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_G_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G2W_SHIFT)
#define GPIO_G_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_G_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G1W_SHIFT)
#define GPIO_G_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_G_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G0W_SHIFT)
#define GPIO_G_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_G_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G7R_SHIFT)
#define GPIO_G_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_G_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G6R_SHIFT)
#define GPIO_G_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G5R_SHIFT)
#define GPIO_G_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_G_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G4R_SHIFT)
#define GPIO_G_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_G_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G3R_SHIFT)
#define GPIO_G_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_G_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G2R_SHIFT)
#define GPIO_G_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_G_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G1R_SHIFT)
#define GPIO_G_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G0R_SHIFT)
#define GPIO_G_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_G_VM_01_0
#define GPIO_G_VM_01_0                  MK_ADDR_CONST(0x4008)
#define GPIO_G_VM_01_0_SECURE                   0x0
#define GPIO_G_VM_01_0_DUAL                     0x0
#define GPIO_G_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_01_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_01_0_WORD_COUNT                       0x1
#define GPIO_G_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM1_SHIFT)
#define GPIO_G_VM_01_0_VM1_RANGE                        1:0
#define GPIO_G_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_G_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_G_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM2_SHIFT)
#define GPIO_G_VM_01_0_VM2_RANGE                        3:2
#define GPIO_G_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_G_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_G_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_G_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM3_SHIFT)
#define GPIO_G_VM_01_0_VM3_RANGE                        5:4
#define GPIO_G_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_G_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_G_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_G_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM4_SHIFT)
#define GPIO_G_VM_01_0_VM4_RANGE                        7:6
#define GPIO_G_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_G_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_G_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM5_SHIFT)
#define GPIO_G_VM_01_0_VM5_RANGE                        9:8
#define GPIO_G_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_G_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_G_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_G_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM6_SHIFT)
#define GPIO_G_VM_01_0_VM6_RANGE                        11:10
#define GPIO_G_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_G_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_G_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_G_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM7_SHIFT)
#define GPIO_G_VM_01_0_VM7_RANGE                        13:12
#define GPIO_G_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_G_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_G_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_G_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM8_SHIFT)
#define GPIO_G_VM_01_0_VM8_RANGE                        15:14
#define GPIO_G_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_G_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_G_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_01_0
#define GPIO_G_SCR_01_0                 MK_ADDR_CONST(0x400c)
#define GPIO_G_SCR_01_0_SECURE                  0x0
#define GPIO_G_SCR_01_0_DUAL                    0x0
#define GPIO_G_SCR_01_0_SCR                     0
#define GPIO_G_SCR_01_0_SCRREG                  0
#define GPIO_G_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_G_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_G_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_G_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_G_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_G_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_G_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_G_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_G_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR7_SHIFT)
#define GPIO_G_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_G_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR6_SHIFT)
#define GPIO_G_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_G_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR5_SHIFT)
#define GPIO_G_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_G_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR4_SHIFT)
#define GPIO_G_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_G_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR3_SHIFT)
#define GPIO_G_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_G_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR2_SHIFT)
#define GPIO_G_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_G_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR1_SHIFT)
#define GPIO_G_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_G_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR0_SHIFT)
#define GPIO_G_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_G_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G7W_SHIFT)
#define GPIO_G_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_G_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G6W_SHIFT)
#define GPIO_G_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_G_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G5W_SHIFT)
#define GPIO_G_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_G_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G4W_SHIFT)
#define GPIO_G_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_G_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G3W_SHIFT)
#define GPIO_G_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_G_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G2W_SHIFT)
#define GPIO_G_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_G_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G1W_SHIFT)
#define GPIO_G_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_G_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G0W_SHIFT)
#define GPIO_G_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_G_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G7R_SHIFT)
#define GPIO_G_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_G_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G6R_SHIFT)
#define GPIO_G_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G5R_SHIFT)
#define GPIO_G_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_G_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G4R_SHIFT)
#define GPIO_G_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_G_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G3R_SHIFT)
#define GPIO_G_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_G_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G2R_SHIFT)
#define GPIO_G_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_G_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G1R_SHIFT)
#define GPIO_G_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G0R_SHIFT)
#define GPIO_G_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_G_VM_02_0
#define GPIO_G_VM_02_0                  MK_ADDR_CONST(0x4010)
#define GPIO_G_VM_02_0_SECURE                   0x0
#define GPIO_G_VM_02_0_DUAL                     0x0
#define GPIO_G_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_02_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_02_0_WORD_COUNT                       0x1
#define GPIO_G_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM1_SHIFT)
#define GPIO_G_VM_02_0_VM1_RANGE                        1:0
#define GPIO_G_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_G_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_G_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM2_SHIFT)
#define GPIO_G_VM_02_0_VM2_RANGE                        3:2
#define GPIO_G_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_G_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_G_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_G_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM3_SHIFT)
#define GPIO_G_VM_02_0_VM3_RANGE                        5:4
#define GPIO_G_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_G_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_G_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_G_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM4_SHIFT)
#define GPIO_G_VM_02_0_VM4_RANGE                        7:6
#define GPIO_G_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_G_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_G_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM5_SHIFT)
#define GPIO_G_VM_02_0_VM5_RANGE                        9:8
#define GPIO_G_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_G_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_G_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_G_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM6_SHIFT)
#define GPIO_G_VM_02_0_VM6_RANGE                        11:10
#define GPIO_G_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_G_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_G_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_G_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM7_SHIFT)
#define GPIO_G_VM_02_0_VM7_RANGE                        13:12
#define GPIO_G_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_G_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_G_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_G_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM8_SHIFT)
#define GPIO_G_VM_02_0_VM8_RANGE                        15:14
#define GPIO_G_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_G_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_G_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_02_0
#define GPIO_G_SCR_02_0                 MK_ADDR_CONST(0x4014)
#define GPIO_G_SCR_02_0_SECURE                  0x0
#define GPIO_G_SCR_02_0_DUAL                    0x0
#define GPIO_G_SCR_02_0_SCR                     0
#define GPIO_G_SCR_02_0_SCRREG                  0
#define GPIO_G_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_G_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_G_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_G_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_G_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_G_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_G_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_G_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_G_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR7_SHIFT)
#define GPIO_G_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_G_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR6_SHIFT)
#define GPIO_G_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_G_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR5_SHIFT)
#define GPIO_G_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_G_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR4_SHIFT)
#define GPIO_G_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_G_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR3_SHIFT)
#define GPIO_G_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_G_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR2_SHIFT)
#define GPIO_G_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_G_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR1_SHIFT)
#define GPIO_G_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_G_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR0_SHIFT)
#define GPIO_G_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_G_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G7W_SHIFT)
#define GPIO_G_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_G_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G6W_SHIFT)
#define GPIO_G_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_G_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G5W_SHIFT)
#define GPIO_G_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_G_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G4W_SHIFT)
#define GPIO_G_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_G_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G3W_SHIFT)
#define GPIO_G_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_G_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G2W_SHIFT)
#define GPIO_G_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_G_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G1W_SHIFT)
#define GPIO_G_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_G_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G0W_SHIFT)
#define GPIO_G_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_G_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G7R_SHIFT)
#define GPIO_G_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_G_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G6R_SHIFT)
#define GPIO_G_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G5R_SHIFT)
#define GPIO_G_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_G_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G4R_SHIFT)
#define GPIO_G_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_G_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G3R_SHIFT)
#define GPIO_G_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_G_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G2R_SHIFT)
#define GPIO_G_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_G_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G1R_SHIFT)
#define GPIO_G_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G0R_SHIFT)
#define GPIO_G_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_G_VM_03_0
#define GPIO_G_VM_03_0                  MK_ADDR_CONST(0x4018)
#define GPIO_G_VM_03_0_SECURE                   0x0
#define GPIO_G_VM_03_0_DUAL                     0x0
#define GPIO_G_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_03_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_03_0_WORD_COUNT                       0x1
#define GPIO_G_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM1_SHIFT)
#define GPIO_G_VM_03_0_VM1_RANGE                        1:0
#define GPIO_G_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_G_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_G_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM2_SHIFT)
#define GPIO_G_VM_03_0_VM2_RANGE                        3:2
#define GPIO_G_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_G_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_G_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_G_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM3_SHIFT)
#define GPIO_G_VM_03_0_VM3_RANGE                        5:4
#define GPIO_G_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_G_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_G_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_G_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM4_SHIFT)
#define GPIO_G_VM_03_0_VM4_RANGE                        7:6
#define GPIO_G_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_G_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_G_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM5_SHIFT)
#define GPIO_G_VM_03_0_VM5_RANGE                        9:8
#define GPIO_G_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_G_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_G_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_G_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM6_SHIFT)
#define GPIO_G_VM_03_0_VM6_RANGE                        11:10
#define GPIO_G_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_G_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_G_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_G_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM7_SHIFT)
#define GPIO_G_VM_03_0_VM7_RANGE                        13:12
#define GPIO_G_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_G_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_G_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_G_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM8_SHIFT)
#define GPIO_G_VM_03_0_VM8_RANGE                        15:14
#define GPIO_G_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_G_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_G_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_03_0
#define GPIO_G_SCR_03_0                 MK_ADDR_CONST(0x401c)
#define GPIO_G_SCR_03_0_SECURE                  0x0
#define GPIO_G_SCR_03_0_DUAL                    0x0
#define GPIO_G_SCR_03_0_SCR                     0
#define GPIO_G_SCR_03_0_SCRREG                  0
#define GPIO_G_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_G_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_G_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_G_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_G_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_G_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_G_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_G_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_G_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR7_SHIFT)
#define GPIO_G_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_G_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR6_SHIFT)
#define GPIO_G_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_G_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR5_SHIFT)
#define GPIO_G_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_G_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR4_SHIFT)
#define GPIO_G_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_G_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR3_SHIFT)
#define GPIO_G_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_G_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR2_SHIFT)
#define GPIO_G_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_G_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR1_SHIFT)
#define GPIO_G_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_G_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR0_SHIFT)
#define GPIO_G_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_G_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G7W_SHIFT)
#define GPIO_G_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_G_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G6W_SHIFT)
#define GPIO_G_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_G_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G5W_SHIFT)
#define GPIO_G_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_G_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G4W_SHIFT)
#define GPIO_G_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_G_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G3W_SHIFT)
#define GPIO_G_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_G_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G2W_SHIFT)
#define GPIO_G_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_G_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G1W_SHIFT)
#define GPIO_G_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_G_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G0W_SHIFT)
#define GPIO_G_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_G_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G7R_SHIFT)
#define GPIO_G_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_G_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G6R_SHIFT)
#define GPIO_G_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G5R_SHIFT)
#define GPIO_G_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_G_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G4R_SHIFT)
#define GPIO_G_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_G_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G3R_SHIFT)
#define GPIO_G_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_G_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G2R_SHIFT)
#define GPIO_G_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_G_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G1R_SHIFT)
#define GPIO_G_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G0R_SHIFT)
#define GPIO_G_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_G_VM_04_0
#define GPIO_G_VM_04_0                  MK_ADDR_CONST(0x4020)
#define GPIO_G_VM_04_0_SECURE                   0x0
#define GPIO_G_VM_04_0_DUAL                     0x0
#define GPIO_G_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_04_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_04_0_WORD_COUNT                       0x1
#define GPIO_G_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM1_SHIFT)
#define GPIO_G_VM_04_0_VM1_RANGE                        1:0
#define GPIO_G_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_G_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_G_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM2_SHIFT)
#define GPIO_G_VM_04_0_VM2_RANGE                        3:2
#define GPIO_G_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_G_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_G_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_G_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM3_SHIFT)
#define GPIO_G_VM_04_0_VM3_RANGE                        5:4
#define GPIO_G_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_G_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_G_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_G_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM4_SHIFT)
#define GPIO_G_VM_04_0_VM4_RANGE                        7:6
#define GPIO_G_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_G_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_G_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM5_SHIFT)
#define GPIO_G_VM_04_0_VM5_RANGE                        9:8
#define GPIO_G_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_G_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_G_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_G_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM6_SHIFT)
#define GPIO_G_VM_04_0_VM6_RANGE                        11:10
#define GPIO_G_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_G_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_G_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_G_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM7_SHIFT)
#define GPIO_G_VM_04_0_VM7_RANGE                        13:12
#define GPIO_G_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_G_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_G_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_G_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM8_SHIFT)
#define GPIO_G_VM_04_0_VM8_RANGE                        15:14
#define GPIO_G_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_G_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_G_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_04_0
#define GPIO_G_SCR_04_0                 MK_ADDR_CONST(0x4024)
#define GPIO_G_SCR_04_0_SECURE                  0x0
#define GPIO_G_SCR_04_0_DUAL                    0x0
#define GPIO_G_SCR_04_0_SCR                     0
#define GPIO_G_SCR_04_0_SCRREG                  0
#define GPIO_G_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_G_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_G_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_G_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_G_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_G_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_G_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_G_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_G_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR7_SHIFT)
#define GPIO_G_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_G_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR6_SHIFT)
#define GPIO_G_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_G_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR5_SHIFT)
#define GPIO_G_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_G_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR4_SHIFT)
#define GPIO_G_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_G_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR3_SHIFT)
#define GPIO_G_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_G_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR2_SHIFT)
#define GPIO_G_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_G_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR1_SHIFT)
#define GPIO_G_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_G_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR0_SHIFT)
#define GPIO_G_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_G_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G7W_SHIFT)
#define GPIO_G_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_G_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G6W_SHIFT)
#define GPIO_G_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_G_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G5W_SHIFT)
#define GPIO_G_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_G_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G4W_SHIFT)
#define GPIO_G_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_G_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G3W_SHIFT)
#define GPIO_G_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_G_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G2W_SHIFT)
#define GPIO_G_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_G_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G1W_SHIFT)
#define GPIO_G_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_G_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G0W_SHIFT)
#define GPIO_G_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_G_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G7R_SHIFT)
#define GPIO_G_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_G_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G6R_SHIFT)
#define GPIO_G_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G5R_SHIFT)
#define GPIO_G_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_G_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G4R_SHIFT)
#define GPIO_G_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_G_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G3R_SHIFT)
#define GPIO_G_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_G_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G2R_SHIFT)
#define GPIO_G_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_G_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G1R_SHIFT)
#define GPIO_G_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G0R_SHIFT)
#define GPIO_G_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_G_VM_05_0
#define GPIO_G_VM_05_0                  MK_ADDR_CONST(0x4028)
#define GPIO_G_VM_05_0_SECURE                   0x0
#define GPIO_G_VM_05_0_DUAL                     0x0
#define GPIO_G_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_05_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_05_0_WORD_COUNT                       0x1
#define GPIO_G_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM1_SHIFT)
#define GPIO_G_VM_05_0_VM1_RANGE                        1:0
#define GPIO_G_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_G_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_G_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM2_SHIFT)
#define GPIO_G_VM_05_0_VM2_RANGE                        3:2
#define GPIO_G_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_G_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_G_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_G_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM3_SHIFT)
#define GPIO_G_VM_05_0_VM3_RANGE                        5:4
#define GPIO_G_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_G_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_G_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_G_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM4_SHIFT)
#define GPIO_G_VM_05_0_VM4_RANGE                        7:6
#define GPIO_G_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_G_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_G_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM5_SHIFT)
#define GPIO_G_VM_05_0_VM5_RANGE                        9:8
#define GPIO_G_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_G_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_G_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_G_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM6_SHIFT)
#define GPIO_G_VM_05_0_VM6_RANGE                        11:10
#define GPIO_G_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_G_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_G_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_G_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM7_SHIFT)
#define GPIO_G_VM_05_0_VM7_RANGE                        13:12
#define GPIO_G_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_G_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_G_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_G_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM8_SHIFT)
#define GPIO_G_VM_05_0_VM8_RANGE                        15:14
#define GPIO_G_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_G_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_G_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_05_0
#define GPIO_G_SCR_05_0                 MK_ADDR_CONST(0x402c)
#define GPIO_G_SCR_05_0_SECURE                  0x0
#define GPIO_G_SCR_05_0_DUAL                    0x0
#define GPIO_G_SCR_05_0_SCR                     0
#define GPIO_G_SCR_05_0_SCRREG                  0
#define GPIO_G_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_G_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_G_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_G_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_G_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_G_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_G_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_G_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_G_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR7_SHIFT)
#define GPIO_G_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_G_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR6_SHIFT)
#define GPIO_G_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_G_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR5_SHIFT)
#define GPIO_G_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_G_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR4_SHIFT)
#define GPIO_G_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_G_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR3_SHIFT)
#define GPIO_G_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_G_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR2_SHIFT)
#define GPIO_G_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_G_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR1_SHIFT)
#define GPIO_G_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_G_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR0_SHIFT)
#define GPIO_G_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_G_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G7W_SHIFT)
#define GPIO_G_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_G_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G6W_SHIFT)
#define GPIO_G_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_G_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G5W_SHIFT)
#define GPIO_G_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_G_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G4W_SHIFT)
#define GPIO_G_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_G_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G3W_SHIFT)
#define GPIO_G_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_G_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G2W_SHIFT)
#define GPIO_G_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_G_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G1W_SHIFT)
#define GPIO_G_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_G_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G0W_SHIFT)
#define GPIO_G_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_G_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G7R_SHIFT)
#define GPIO_G_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_G_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G6R_SHIFT)
#define GPIO_G_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G5R_SHIFT)
#define GPIO_G_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_G_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G4R_SHIFT)
#define GPIO_G_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_G_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G3R_SHIFT)
#define GPIO_G_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_G_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G2R_SHIFT)
#define GPIO_G_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_G_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G1R_SHIFT)
#define GPIO_G_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G0R_SHIFT)
#define GPIO_G_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_G_VM_06_0
#define GPIO_G_VM_06_0                  MK_ADDR_CONST(0x4030)
#define GPIO_G_VM_06_0_SECURE                   0x0
#define GPIO_G_VM_06_0_DUAL                     0x0
#define GPIO_G_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_06_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_06_0_WORD_COUNT                       0x1
#define GPIO_G_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM1_SHIFT)
#define GPIO_G_VM_06_0_VM1_RANGE                        1:0
#define GPIO_G_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_G_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_G_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM2_SHIFT)
#define GPIO_G_VM_06_0_VM2_RANGE                        3:2
#define GPIO_G_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_G_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_G_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_G_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM3_SHIFT)
#define GPIO_G_VM_06_0_VM3_RANGE                        5:4
#define GPIO_G_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_G_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_G_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_G_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM4_SHIFT)
#define GPIO_G_VM_06_0_VM4_RANGE                        7:6
#define GPIO_G_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_G_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_G_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM5_SHIFT)
#define GPIO_G_VM_06_0_VM5_RANGE                        9:8
#define GPIO_G_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_G_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_G_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_G_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM6_SHIFT)
#define GPIO_G_VM_06_0_VM6_RANGE                        11:10
#define GPIO_G_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_G_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_G_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_G_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM7_SHIFT)
#define GPIO_G_VM_06_0_VM7_RANGE                        13:12
#define GPIO_G_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_G_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_G_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_G_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM8_SHIFT)
#define GPIO_G_VM_06_0_VM8_RANGE                        15:14
#define GPIO_G_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_G_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_G_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_06_0
#define GPIO_G_SCR_06_0                 MK_ADDR_CONST(0x4034)
#define GPIO_G_SCR_06_0_SECURE                  0x0
#define GPIO_G_SCR_06_0_DUAL                    0x0
#define GPIO_G_SCR_06_0_SCR                     0
#define GPIO_G_SCR_06_0_SCRREG                  0
#define GPIO_G_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_G_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_G_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_G_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_G_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_G_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_G_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_G_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_G_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR7_SHIFT)
#define GPIO_G_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_G_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR6_SHIFT)
#define GPIO_G_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_G_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR5_SHIFT)
#define GPIO_G_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_G_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR4_SHIFT)
#define GPIO_G_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_G_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR3_SHIFT)
#define GPIO_G_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_G_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR2_SHIFT)
#define GPIO_G_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_G_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR1_SHIFT)
#define GPIO_G_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_G_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR0_SHIFT)
#define GPIO_G_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_G_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G7W_SHIFT)
#define GPIO_G_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_G_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G6W_SHIFT)
#define GPIO_G_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_G_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G5W_SHIFT)
#define GPIO_G_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_G_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G4W_SHIFT)
#define GPIO_G_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_G_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G3W_SHIFT)
#define GPIO_G_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_G_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G2W_SHIFT)
#define GPIO_G_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_G_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G1W_SHIFT)
#define GPIO_G_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_G_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G0W_SHIFT)
#define GPIO_G_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_G_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G7R_SHIFT)
#define GPIO_G_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_G_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G6R_SHIFT)
#define GPIO_G_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G5R_SHIFT)
#define GPIO_G_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_G_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G4R_SHIFT)
#define GPIO_G_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_G_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G3R_SHIFT)
#define GPIO_G_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_G_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G2R_SHIFT)
#define GPIO_G_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_G_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G1R_SHIFT)
#define GPIO_G_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G0R_SHIFT)
#define GPIO_G_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_G_VM_07_0
#define GPIO_G_VM_07_0                  MK_ADDR_CONST(0x4038)
#define GPIO_G_VM_07_0_SECURE                   0x0
#define GPIO_G_VM_07_0_DUAL                     0x0
#define GPIO_G_VM_07_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_07_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_G_VM_07_0_WORD_COUNT                       0x1
#define GPIO_G_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_G_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_G_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM1_SHIFT)
#define GPIO_G_VM_07_0_VM1_RANGE                        1:0
#define GPIO_G_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_G_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_G_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM2_SHIFT)
#define GPIO_G_VM_07_0_VM2_RANGE                        3:2
#define GPIO_G_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_G_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_G_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_G_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM3_SHIFT)
#define GPIO_G_VM_07_0_VM3_RANGE                        5:4
#define GPIO_G_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_G_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_G_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_G_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM4_SHIFT)
#define GPIO_G_VM_07_0_VM4_RANGE                        7:6
#define GPIO_G_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_G_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_G_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM5_SHIFT)
#define GPIO_G_VM_07_0_VM5_RANGE                        9:8
#define GPIO_G_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_G_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_G_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_G_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM6_SHIFT)
#define GPIO_G_VM_07_0_VM6_RANGE                        11:10
#define GPIO_G_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_G_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_G_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_G_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM7_SHIFT)
#define GPIO_G_VM_07_0_VM7_RANGE                        13:12
#define GPIO_G_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_G_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_G_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_G_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_G_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM8_SHIFT)
#define GPIO_G_VM_07_0_VM8_RANGE                        15:14
#define GPIO_G_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_G_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_G_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_G_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_G_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_SCR_07_0
#define GPIO_G_SCR_07_0                 MK_ADDR_CONST(0x403c)
#define GPIO_G_SCR_07_0_SECURE                  0x0
#define GPIO_G_SCR_07_0_DUAL                    0x0
#define GPIO_G_SCR_07_0_SCR                     0
#define GPIO_G_SCR_07_0_SCRREG                  0
#define GPIO_G_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_G_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_G_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_G_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_G_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_G_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_G_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_G_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_G_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_G_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_G_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_G_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_G_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_G_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_G_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_G_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_G_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_G_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_G_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_G_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_G_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_G_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_G_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_G_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_G_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_G_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR7_SHIFT)
#define GPIO_G_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_G_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_G_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_G_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR6_SHIFT)
#define GPIO_G_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_G_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_G_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_G_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR5_SHIFT)
#define GPIO_G_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_G_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_G_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_G_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR4_SHIFT)
#define GPIO_G_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_G_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_G_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_G_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR3_SHIFT)
#define GPIO_G_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_G_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_G_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_G_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR2_SHIFT)
#define GPIO_G_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_G_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_G_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_G_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR1_SHIFT)
#define GPIO_G_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_G_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_G_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_G_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR0_SHIFT)
#define GPIO_G_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_G_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_G_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_G_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G7W_SHIFT)
#define GPIO_G_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_G_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_G_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_G_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G6W_SHIFT)
#define GPIO_G_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_G_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_G_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_G_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G5W_SHIFT)
#define GPIO_G_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_G_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_G_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_G_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G4W_SHIFT)
#define GPIO_G_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_G_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_G_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_G_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G3W_SHIFT)
#define GPIO_G_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_G_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_G_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_G_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G2W_SHIFT)
#define GPIO_G_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_G_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_G_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_G_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G1W_SHIFT)
#define GPIO_G_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_G_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_G_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_G_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G0W_SHIFT)
#define GPIO_G_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_G_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_G_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_G_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G7R_SHIFT)
#define GPIO_G_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_G_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_G_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_G_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G6R_SHIFT)
#define GPIO_G_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_G_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_G_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G5R_SHIFT)
#define GPIO_G_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_G_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_G_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G4R_SHIFT)
#define GPIO_G_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_G_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_G_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_G_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G3R_SHIFT)
#define GPIO_G_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_G_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_G_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_G_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G2R_SHIFT)
#define GPIO_G_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_G_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_G_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_G_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G1R_SHIFT)
#define GPIO_G_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_G_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_G_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_G_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G0R_SHIFT)
#define GPIO_G_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_G_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_G_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_G_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_H_VM_00_0
#define GPIO_H_VM_00_0                  MK_ADDR_CONST(0x4040)
#define GPIO_H_VM_00_0_SECURE                   0x0
#define GPIO_H_VM_00_0_DUAL                     0x0
#define GPIO_H_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_00_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_00_0_WORD_COUNT                       0x1
#define GPIO_H_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM1_SHIFT)
#define GPIO_H_VM_00_0_VM1_RANGE                        1:0
#define GPIO_H_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_H_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_H_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM2_SHIFT)
#define GPIO_H_VM_00_0_VM2_RANGE                        3:2
#define GPIO_H_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_H_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_H_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_H_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM3_SHIFT)
#define GPIO_H_VM_00_0_VM3_RANGE                        5:4
#define GPIO_H_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_H_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_H_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_H_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM4_SHIFT)
#define GPIO_H_VM_00_0_VM4_RANGE                        7:6
#define GPIO_H_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_H_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_H_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM5_SHIFT)
#define GPIO_H_VM_00_0_VM5_RANGE                        9:8
#define GPIO_H_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_H_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_H_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_H_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM6_SHIFT)
#define GPIO_H_VM_00_0_VM6_RANGE                        11:10
#define GPIO_H_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_H_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_H_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_H_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM7_SHIFT)
#define GPIO_H_VM_00_0_VM7_RANGE                        13:12
#define GPIO_H_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_H_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_H_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_H_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM8_SHIFT)
#define GPIO_H_VM_00_0_VM8_RANGE                        15:14
#define GPIO_H_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_H_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_H_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_00_0
#define GPIO_H_SCR_00_0                 MK_ADDR_CONST(0x4044)
#define GPIO_H_SCR_00_0_SECURE                  0x0
#define GPIO_H_SCR_00_0_DUAL                    0x0
#define GPIO_H_SCR_00_0_SCR                     0
#define GPIO_H_SCR_00_0_SCRREG                  0
#define GPIO_H_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_H_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_H_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_H_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_H_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_H_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_H_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_H_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_H_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR7_SHIFT)
#define GPIO_H_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_H_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR6_SHIFT)
#define GPIO_H_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_H_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR5_SHIFT)
#define GPIO_H_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_H_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR4_SHIFT)
#define GPIO_H_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_H_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR3_SHIFT)
#define GPIO_H_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_H_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR2_SHIFT)
#define GPIO_H_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_H_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR1_SHIFT)
#define GPIO_H_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_H_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR0_SHIFT)
#define GPIO_H_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_H_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G7W_SHIFT)
#define GPIO_H_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_H_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G6W_SHIFT)
#define GPIO_H_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_H_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G5W_SHIFT)
#define GPIO_H_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_H_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G4W_SHIFT)
#define GPIO_H_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_H_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G3W_SHIFT)
#define GPIO_H_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_H_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G2W_SHIFT)
#define GPIO_H_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_H_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G1W_SHIFT)
#define GPIO_H_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_H_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G0W_SHIFT)
#define GPIO_H_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_H_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G7R_SHIFT)
#define GPIO_H_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_H_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G6R_SHIFT)
#define GPIO_H_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G5R_SHIFT)
#define GPIO_H_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_H_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G4R_SHIFT)
#define GPIO_H_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_H_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G3R_SHIFT)
#define GPIO_H_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_H_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G2R_SHIFT)
#define GPIO_H_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_H_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G1R_SHIFT)
#define GPIO_H_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G0R_SHIFT)
#define GPIO_H_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_H_VM_01_0
#define GPIO_H_VM_01_0                  MK_ADDR_CONST(0x4048)
#define GPIO_H_VM_01_0_SECURE                   0x0
#define GPIO_H_VM_01_0_DUAL                     0x0
#define GPIO_H_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_01_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_01_0_WORD_COUNT                       0x1
#define GPIO_H_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM1_SHIFT)
#define GPIO_H_VM_01_0_VM1_RANGE                        1:0
#define GPIO_H_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_H_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_H_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM2_SHIFT)
#define GPIO_H_VM_01_0_VM2_RANGE                        3:2
#define GPIO_H_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_H_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_H_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_H_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM3_SHIFT)
#define GPIO_H_VM_01_0_VM3_RANGE                        5:4
#define GPIO_H_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_H_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_H_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_H_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM4_SHIFT)
#define GPIO_H_VM_01_0_VM4_RANGE                        7:6
#define GPIO_H_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_H_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_H_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM5_SHIFT)
#define GPIO_H_VM_01_0_VM5_RANGE                        9:8
#define GPIO_H_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_H_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_H_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_H_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM6_SHIFT)
#define GPIO_H_VM_01_0_VM6_RANGE                        11:10
#define GPIO_H_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_H_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_H_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_H_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM7_SHIFT)
#define GPIO_H_VM_01_0_VM7_RANGE                        13:12
#define GPIO_H_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_H_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_H_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_H_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM8_SHIFT)
#define GPIO_H_VM_01_0_VM8_RANGE                        15:14
#define GPIO_H_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_H_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_H_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_01_0
#define GPIO_H_SCR_01_0                 MK_ADDR_CONST(0x404c)
#define GPIO_H_SCR_01_0_SECURE                  0x0
#define GPIO_H_SCR_01_0_DUAL                    0x0
#define GPIO_H_SCR_01_0_SCR                     0
#define GPIO_H_SCR_01_0_SCRREG                  0
#define GPIO_H_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_H_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_H_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_H_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_H_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_H_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_H_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_H_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_H_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR7_SHIFT)
#define GPIO_H_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_H_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR6_SHIFT)
#define GPIO_H_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_H_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR5_SHIFT)
#define GPIO_H_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_H_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR4_SHIFT)
#define GPIO_H_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_H_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR3_SHIFT)
#define GPIO_H_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_H_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR2_SHIFT)
#define GPIO_H_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_H_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR1_SHIFT)
#define GPIO_H_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_H_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR0_SHIFT)
#define GPIO_H_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_H_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G7W_SHIFT)
#define GPIO_H_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_H_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G6W_SHIFT)
#define GPIO_H_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_H_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G5W_SHIFT)
#define GPIO_H_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_H_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G4W_SHIFT)
#define GPIO_H_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_H_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G3W_SHIFT)
#define GPIO_H_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_H_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G2W_SHIFT)
#define GPIO_H_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_H_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G1W_SHIFT)
#define GPIO_H_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_H_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G0W_SHIFT)
#define GPIO_H_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_H_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G7R_SHIFT)
#define GPIO_H_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_H_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G6R_SHIFT)
#define GPIO_H_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G5R_SHIFT)
#define GPIO_H_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_H_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G4R_SHIFT)
#define GPIO_H_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_H_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G3R_SHIFT)
#define GPIO_H_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_H_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G2R_SHIFT)
#define GPIO_H_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_H_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G1R_SHIFT)
#define GPIO_H_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G0R_SHIFT)
#define GPIO_H_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_H_VM_02_0
#define GPIO_H_VM_02_0                  MK_ADDR_CONST(0x4050)
#define GPIO_H_VM_02_0_SECURE                   0x0
#define GPIO_H_VM_02_0_DUAL                     0x0
#define GPIO_H_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_02_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_02_0_WORD_COUNT                       0x1
#define GPIO_H_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM1_SHIFT)
#define GPIO_H_VM_02_0_VM1_RANGE                        1:0
#define GPIO_H_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_H_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_H_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM2_SHIFT)
#define GPIO_H_VM_02_0_VM2_RANGE                        3:2
#define GPIO_H_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_H_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_H_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_H_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM3_SHIFT)
#define GPIO_H_VM_02_0_VM3_RANGE                        5:4
#define GPIO_H_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_H_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_H_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_H_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM4_SHIFT)
#define GPIO_H_VM_02_0_VM4_RANGE                        7:6
#define GPIO_H_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_H_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_H_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM5_SHIFT)
#define GPIO_H_VM_02_0_VM5_RANGE                        9:8
#define GPIO_H_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_H_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_H_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_H_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM6_SHIFT)
#define GPIO_H_VM_02_0_VM6_RANGE                        11:10
#define GPIO_H_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_H_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_H_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_H_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM7_SHIFT)
#define GPIO_H_VM_02_0_VM7_RANGE                        13:12
#define GPIO_H_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_H_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_H_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_H_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM8_SHIFT)
#define GPIO_H_VM_02_0_VM8_RANGE                        15:14
#define GPIO_H_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_H_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_H_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_02_0
#define GPIO_H_SCR_02_0                 MK_ADDR_CONST(0x4054)
#define GPIO_H_SCR_02_0_SECURE                  0x0
#define GPIO_H_SCR_02_0_DUAL                    0x0
#define GPIO_H_SCR_02_0_SCR                     0
#define GPIO_H_SCR_02_0_SCRREG                  0
#define GPIO_H_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_H_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_H_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_H_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_H_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_H_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_H_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_H_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_H_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR7_SHIFT)
#define GPIO_H_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_H_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR6_SHIFT)
#define GPIO_H_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_H_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR5_SHIFT)
#define GPIO_H_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_H_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR4_SHIFT)
#define GPIO_H_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_H_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR3_SHIFT)
#define GPIO_H_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_H_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR2_SHIFT)
#define GPIO_H_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_H_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR1_SHIFT)
#define GPIO_H_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_H_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR0_SHIFT)
#define GPIO_H_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_H_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G7W_SHIFT)
#define GPIO_H_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_H_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G6W_SHIFT)
#define GPIO_H_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_H_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G5W_SHIFT)
#define GPIO_H_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_H_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G4W_SHIFT)
#define GPIO_H_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_H_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G3W_SHIFT)
#define GPIO_H_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_H_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G2W_SHIFT)
#define GPIO_H_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_H_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G1W_SHIFT)
#define GPIO_H_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_H_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G0W_SHIFT)
#define GPIO_H_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_H_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G7R_SHIFT)
#define GPIO_H_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_H_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G6R_SHIFT)
#define GPIO_H_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G5R_SHIFT)
#define GPIO_H_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_H_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G4R_SHIFT)
#define GPIO_H_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_H_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G3R_SHIFT)
#define GPIO_H_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_H_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G2R_SHIFT)
#define GPIO_H_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_H_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G1R_SHIFT)
#define GPIO_H_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G0R_SHIFT)
#define GPIO_H_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_H_VM_03_0
#define GPIO_H_VM_03_0                  MK_ADDR_CONST(0x4058)
#define GPIO_H_VM_03_0_SECURE                   0x0
#define GPIO_H_VM_03_0_DUAL                     0x0
#define GPIO_H_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_03_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_03_0_WORD_COUNT                       0x1
#define GPIO_H_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM1_SHIFT)
#define GPIO_H_VM_03_0_VM1_RANGE                        1:0
#define GPIO_H_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_H_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_H_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM2_SHIFT)
#define GPIO_H_VM_03_0_VM2_RANGE                        3:2
#define GPIO_H_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_H_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_H_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_H_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM3_SHIFT)
#define GPIO_H_VM_03_0_VM3_RANGE                        5:4
#define GPIO_H_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_H_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_H_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_H_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM4_SHIFT)
#define GPIO_H_VM_03_0_VM4_RANGE                        7:6
#define GPIO_H_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_H_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_H_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM5_SHIFT)
#define GPIO_H_VM_03_0_VM5_RANGE                        9:8
#define GPIO_H_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_H_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_H_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_H_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM6_SHIFT)
#define GPIO_H_VM_03_0_VM6_RANGE                        11:10
#define GPIO_H_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_H_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_H_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_H_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM7_SHIFT)
#define GPIO_H_VM_03_0_VM7_RANGE                        13:12
#define GPIO_H_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_H_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_H_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_H_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM8_SHIFT)
#define GPIO_H_VM_03_0_VM8_RANGE                        15:14
#define GPIO_H_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_H_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_H_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_03_0
#define GPIO_H_SCR_03_0                 MK_ADDR_CONST(0x405c)
#define GPIO_H_SCR_03_0_SECURE                  0x0
#define GPIO_H_SCR_03_0_DUAL                    0x0
#define GPIO_H_SCR_03_0_SCR                     0
#define GPIO_H_SCR_03_0_SCRREG                  0
#define GPIO_H_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_H_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_H_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_H_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_H_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_H_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_H_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_H_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_H_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR7_SHIFT)
#define GPIO_H_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_H_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR6_SHIFT)
#define GPIO_H_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_H_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR5_SHIFT)
#define GPIO_H_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_H_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR4_SHIFT)
#define GPIO_H_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_H_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR3_SHIFT)
#define GPIO_H_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_H_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR2_SHIFT)
#define GPIO_H_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_H_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR1_SHIFT)
#define GPIO_H_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_H_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR0_SHIFT)
#define GPIO_H_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_H_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G7W_SHIFT)
#define GPIO_H_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_H_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G6W_SHIFT)
#define GPIO_H_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_H_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G5W_SHIFT)
#define GPIO_H_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_H_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G4W_SHIFT)
#define GPIO_H_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_H_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G3W_SHIFT)
#define GPIO_H_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_H_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G2W_SHIFT)
#define GPIO_H_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_H_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G1W_SHIFT)
#define GPIO_H_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_H_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G0W_SHIFT)
#define GPIO_H_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_H_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G7R_SHIFT)
#define GPIO_H_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_H_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G6R_SHIFT)
#define GPIO_H_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G5R_SHIFT)
#define GPIO_H_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_H_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G4R_SHIFT)
#define GPIO_H_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_H_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G3R_SHIFT)
#define GPIO_H_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_H_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G2R_SHIFT)
#define GPIO_H_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_H_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G1R_SHIFT)
#define GPIO_H_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G0R_SHIFT)
#define GPIO_H_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_H_VM_04_0
#define GPIO_H_VM_04_0                  MK_ADDR_CONST(0x4060)
#define GPIO_H_VM_04_0_SECURE                   0x0
#define GPIO_H_VM_04_0_DUAL                     0x0
#define GPIO_H_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_04_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_04_0_WORD_COUNT                       0x1
#define GPIO_H_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM1_SHIFT)
#define GPIO_H_VM_04_0_VM1_RANGE                        1:0
#define GPIO_H_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_H_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_H_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM2_SHIFT)
#define GPIO_H_VM_04_0_VM2_RANGE                        3:2
#define GPIO_H_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_H_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_H_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_H_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM3_SHIFT)
#define GPIO_H_VM_04_0_VM3_RANGE                        5:4
#define GPIO_H_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_H_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_H_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_H_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM4_SHIFT)
#define GPIO_H_VM_04_0_VM4_RANGE                        7:6
#define GPIO_H_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_H_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_H_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM5_SHIFT)
#define GPIO_H_VM_04_0_VM5_RANGE                        9:8
#define GPIO_H_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_H_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_H_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_H_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM6_SHIFT)
#define GPIO_H_VM_04_0_VM6_RANGE                        11:10
#define GPIO_H_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_H_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_H_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_H_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM7_SHIFT)
#define GPIO_H_VM_04_0_VM7_RANGE                        13:12
#define GPIO_H_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_H_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_H_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_H_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM8_SHIFT)
#define GPIO_H_VM_04_0_VM8_RANGE                        15:14
#define GPIO_H_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_H_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_H_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_04_0
#define GPIO_H_SCR_04_0                 MK_ADDR_CONST(0x4064)
#define GPIO_H_SCR_04_0_SECURE                  0x0
#define GPIO_H_SCR_04_0_DUAL                    0x0
#define GPIO_H_SCR_04_0_SCR                     0
#define GPIO_H_SCR_04_0_SCRREG                  0
#define GPIO_H_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_H_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_H_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_H_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_H_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_H_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_H_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_H_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_H_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR7_SHIFT)
#define GPIO_H_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_H_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR6_SHIFT)
#define GPIO_H_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_H_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR5_SHIFT)
#define GPIO_H_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_H_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR4_SHIFT)
#define GPIO_H_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_H_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR3_SHIFT)
#define GPIO_H_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_H_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR2_SHIFT)
#define GPIO_H_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_H_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR1_SHIFT)
#define GPIO_H_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_H_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR0_SHIFT)
#define GPIO_H_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_H_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G7W_SHIFT)
#define GPIO_H_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_H_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G6W_SHIFT)
#define GPIO_H_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_H_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G5W_SHIFT)
#define GPIO_H_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_H_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G4W_SHIFT)
#define GPIO_H_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_H_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G3W_SHIFT)
#define GPIO_H_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_H_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G2W_SHIFT)
#define GPIO_H_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_H_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G1W_SHIFT)
#define GPIO_H_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_H_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G0W_SHIFT)
#define GPIO_H_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_H_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G7R_SHIFT)
#define GPIO_H_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_H_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G6R_SHIFT)
#define GPIO_H_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G5R_SHIFT)
#define GPIO_H_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_H_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G4R_SHIFT)
#define GPIO_H_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_H_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G3R_SHIFT)
#define GPIO_H_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_H_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G2R_SHIFT)
#define GPIO_H_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_H_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G1R_SHIFT)
#define GPIO_H_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G0R_SHIFT)
#define GPIO_H_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_H_VM_05_0
#define GPIO_H_VM_05_0                  MK_ADDR_CONST(0x4068)
#define GPIO_H_VM_05_0_SECURE                   0x0
#define GPIO_H_VM_05_0_DUAL                     0x0
#define GPIO_H_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_05_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_05_0_WORD_COUNT                       0x1
#define GPIO_H_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM1_SHIFT)
#define GPIO_H_VM_05_0_VM1_RANGE                        1:0
#define GPIO_H_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_H_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_H_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM2_SHIFT)
#define GPIO_H_VM_05_0_VM2_RANGE                        3:2
#define GPIO_H_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_H_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_H_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_H_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM3_SHIFT)
#define GPIO_H_VM_05_0_VM3_RANGE                        5:4
#define GPIO_H_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_H_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_H_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_H_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM4_SHIFT)
#define GPIO_H_VM_05_0_VM4_RANGE                        7:6
#define GPIO_H_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_H_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_H_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM5_SHIFT)
#define GPIO_H_VM_05_0_VM5_RANGE                        9:8
#define GPIO_H_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_H_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_H_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_H_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM6_SHIFT)
#define GPIO_H_VM_05_0_VM6_RANGE                        11:10
#define GPIO_H_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_H_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_H_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_H_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM7_SHIFT)
#define GPIO_H_VM_05_0_VM7_RANGE                        13:12
#define GPIO_H_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_H_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_H_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_H_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM8_SHIFT)
#define GPIO_H_VM_05_0_VM8_RANGE                        15:14
#define GPIO_H_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_H_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_H_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_05_0
#define GPIO_H_SCR_05_0                 MK_ADDR_CONST(0x406c)
#define GPIO_H_SCR_05_0_SECURE                  0x0
#define GPIO_H_SCR_05_0_DUAL                    0x0
#define GPIO_H_SCR_05_0_SCR                     0
#define GPIO_H_SCR_05_0_SCRREG                  0
#define GPIO_H_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_H_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_H_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_H_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_H_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_H_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_H_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_H_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_H_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR7_SHIFT)
#define GPIO_H_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_H_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR6_SHIFT)
#define GPIO_H_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_H_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR5_SHIFT)
#define GPIO_H_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_H_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR4_SHIFT)
#define GPIO_H_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_H_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR3_SHIFT)
#define GPIO_H_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_H_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR2_SHIFT)
#define GPIO_H_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_H_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR1_SHIFT)
#define GPIO_H_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_H_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR0_SHIFT)
#define GPIO_H_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_H_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G7W_SHIFT)
#define GPIO_H_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_H_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G6W_SHIFT)
#define GPIO_H_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_H_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G5W_SHIFT)
#define GPIO_H_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_H_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G4W_SHIFT)
#define GPIO_H_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_H_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G3W_SHIFT)
#define GPIO_H_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_H_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G2W_SHIFT)
#define GPIO_H_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_H_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G1W_SHIFT)
#define GPIO_H_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_H_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G0W_SHIFT)
#define GPIO_H_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_H_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G7R_SHIFT)
#define GPIO_H_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_H_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G6R_SHIFT)
#define GPIO_H_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G5R_SHIFT)
#define GPIO_H_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_H_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G4R_SHIFT)
#define GPIO_H_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_H_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G3R_SHIFT)
#define GPIO_H_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_H_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G2R_SHIFT)
#define GPIO_H_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_H_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G1R_SHIFT)
#define GPIO_H_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G0R_SHIFT)
#define GPIO_H_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_H_VM_06_0
#define GPIO_H_VM_06_0                  MK_ADDR_CONST(0x4070)
#define GPIO_H_VM_06_0_SECURE                   0x0
#define GPIO_H_VM_06_0_DUAL                     0x0
#define GPIO_H_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_06_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_06_0_WORD_COUNT                       0x1
#define GPIO_H_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM1_SHIFT)
#define GPIO_H_VM_06_0_VM1_RANGE                        1:0
#define GPIO_H_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_H_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_H_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM2_SHIFT)
#define GPIO_H_VM_06_0_VM2_RANGE                        3:2
#define GPIO_H_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_H_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_H_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_H_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM3_SHIFT)
#define GPIO_H_VM_06_0_VM3_RANGE                        5:4
#define GPIO_H_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_H_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_H_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_H_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM4_SHIFT)
#define GPIO_H_VM_06_0_VM4_RANGE                        7:6
#define GPIO_H_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_H_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_H_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM5_SHIFT)
#define GPIO_H_VM_06_0_VM5_RANGE                        9:8
#define GPIO_H_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_H_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_H_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_H_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM6_SHIFT)
#define GPIO_H_VM_06_0_VM6_RANGE                        11:10
#define GPIO_H_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_H_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_H_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_H_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM7_SHIFT)
#define GPIO_H_VM_06_0_VM7_RANGE                        13:12
#define GPIO_H_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_H_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_H_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_H_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM8_SHIFT)
#define GPIO_H_VM_06_0_VM8_RANGE                        15:14
#define GPIO_H_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_H_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_H_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_06_0
#define GPIO_H_SCR_06_0                 MK_ADDR_CONST(0x4074)
#define GPIO_H_SCR_06_0_SECURE                  0x0
#define GPIO_H_SCR_06_0_DUAL                    0x0
#define GPIO_H_SCR_06_0_SCR                     0
#define GPIO_H_SCR_06_0_SCRREG                  0
#define GPIO_H_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_H_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_H_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_H_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_H_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_H_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_H_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_H_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_H_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR7_SHIFT)
#define GPIO_H_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_H_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR6_SHIFT)
#define GPIO_H_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_H_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR5_SHIFT)
#define GPIO_H_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_H_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR4_SHIFT)
#define GPIO_H_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_H_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR3_SHIFT)
#define GPIO_H_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_H_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR2_SHIFT)
#define GPIO_H_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_H_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR1_SHIFT)
#define GPIO_H_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_H_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR0_SHIFT)
#define GPIO_H_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_H_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G7W_SHIFT)
#define GPIO_H_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_H_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G6W_SHIFT)
#define GPIO_H_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_H_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G5W_SHIFT)
#define GPIO_H_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_H_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G4W_SHIFT)
#define GPIO_H_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_H_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G3W_SHIFT)
#define GPIO_H_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_H_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G2W_SHIFT)
#define GPIO_H_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_H_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G1W_SHIFT)
#define GPIO_H_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_H_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G0W_SHIFT)
#define GPIO_H_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_H_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G7R_SHIFT)
#define GPIO_H_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_H_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G6R_SHIFT)
#define GPIO_H_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G5R_SHIFT)
#define GPIO_H_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_H_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G4R_SHIFT)
#define GPIO_H_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_H_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G3R_SHIFT)
#define GPIO_H_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_H_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G2R_SHIFT)
#define GPIO_H_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_H_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G1R_SHIFT)
#define GPIO_H_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G0R_SHIFT)
#define GPIO_H_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_H_VM_07_0
#define GPIO_H_VM_07_0                  MK_ADDR_CONST(0x4078)
#define GPIO_H_VM_07_0_SECURE                   0x0
#define GPIO_H_VM_07_0_DUAL                     0x0
#define GPIO_H_VM_07_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_07_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_H_VM_07_0_WORD_COUNT                       0x1
#define GPIO_H_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_H_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_H_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM1_SHIFT)
#define GPIO_H_VM_07_0_VM1_RANGE                        1:0
#define GPIO_H_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_H_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_H_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM2_SHIFT)
#define GPIO_H_VM_07_0_VM2_RANGE                        3:2
#define GPIO_H_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_H_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_H_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_H_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM3_SHIFT)
#define GPIO_H_VM_07_0_VM3_RANGE                        5:4
#define GPIO_H_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_H_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_H_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_H_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM4_SHIFT)
#define GPIO_H_VM_07_0_VM4_RANGE                        7:6
#define GPIO_H_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_H_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_H_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM5_SHIFT)
#define GPIO_H_VM_07_0_VM5_RANGE                        9:8
#define GPIO_H_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_H_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_H_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_H_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM6_SHIFT)
#define GPIO_H_VM_07_0_VM6_RANGE                        11:10
#define GPIO_H_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_H_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_H_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_H_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM7_SHIFT)
#define GPIO_H_VM_07_0_VM7_RANGE                        13:12
#define GPIO_H_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_H_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_H_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_H_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_H_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM8_SHIFT)
#define GPIO_H_VM_07_0_VM8_RANGE                        15:14
#define GPIO_H_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_H_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_H_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_H_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_H_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_SCR_07_0
#define GPIO_H_SCR_07_0                 MK_ADDR_CONST(0x407c)
#define GPIO_H_SCR_07_0_SECURE                  0x0
#define GPIO_H_SCR_07_0_DUAL                    0x0
#define GPIO_H_SCR_07_0_SCR                     0
#define GPIO_H_SCR_07_0_SCRREG                  0
#define GPIO_H_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_H_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_H_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_H_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_H_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_H_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_H_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_H_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_H_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_H_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_H_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_H_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_H_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_H_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_H_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_H_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_H_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_H_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_H_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_H_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_H_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_H_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_H_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_H_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_H_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_H_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR7_SHIFT)
#define GPIO_H_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_H_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_H_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_H_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR6_SHIFT)
#define GPIO_H_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_H_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_H_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_H_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR5_SHIFT)
#define GPIO_H_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_H_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_H_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_H_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR4_SHIFT)
#define GPIO_H_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_H_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_H_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_H_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR3_SHIFT)
#define GPIO_H_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_H_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_H_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_H_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR2_SHIFT)
#define GPIO_H_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_H_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_H_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_H_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR1_SHIFT)
#define GPIO_H_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_H_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_H_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_H_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR0_SHIFT)
#define GPIO_H_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_H_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_H_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_H_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G7W_SHIFT)
#define GPIO_H_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_H_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_H_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_H_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G6W_SHIFT)
#define GPIO_H_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_H_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_H_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_H_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G5W_SHIFT)
#define GPIO_H_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_H_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_H_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_H_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G4W_SHIFT)
#define GPIO_H_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_H_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_H_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_H_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G3W_SHIFT)
#define GPIO_H_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_H_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_H_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_H_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G2W_SHIFT)
#define GPIO_H_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_H_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_H_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_H_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G1W_SHIFT)
#define GPIO_H_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_H_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_H_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_H_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G0W_SHIFT)
#define GPIO_H_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_H_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_H_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_H_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G7R_SHIFT)
#define GPIO_H_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_H_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_H_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_H_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G6R_SHIFT)
#define GPIO_H_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_H_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_H_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G5R_SHIFT)
#define GPIO_H_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_H_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_H_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G4R_SHIFT)
#define GPIO_H_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_H_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_H_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_H_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G3R_SHIFT)
#define GPIO_H_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_H_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_H_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_H_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G2R_SHIFT)
#define GPIO_H_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_H_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_H_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_H_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G1R_SHIFT)
#define GPIO_H_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_H_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_H_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_H_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G0R_SHIFT)
#define GPIO_H_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_H_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_H_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_H_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_I_VM_00_0
#define GPIO_I_VM_00_0                  MK_ADDR_CONST(0x4080)
#define GPIO_I_VM_00_0_SECURE                   0x0
#define GPIO_I_VM_00_0_DUAL                     0x0
#define GPIO_I_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_00_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_00_0_WORD_COUNT                       0x1
#define GPIO_I_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM1_SHIFT)
#define GPIO_I_VM_00_0_VM1_RANGE                        1:0
#define GPIO_I_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_I_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_I_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM2_SHIFT)
#define GPIO_I_VM_00_0_VM2_RANGE                        3:2
#define GPIO_I_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_I_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_I_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_I_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM3_SHIFT)
#define GPIO_I_VM_00_0_VM3_RANGE                        5:4
#define GPIO_I_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_I_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_I_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_I_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM4_SHIFT)
#define GPIO_I_VM_00_0_VM4_RANGE                        7:6
#define GPIO_I_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_I_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_I_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_I_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM5_SHIFT)
#define GPIO_I_VM_00_0_VM5_RANGE                        9:8
#define GPIO_I_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_I_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_I_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_I_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM6_SHIFT)
#define GPIO_I_VM_00_0_VM6_RANGE                        11:10
#define GPIO_I_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_I_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_I_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_I_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM7_SHIFT)
#define GPIO_I_VM_00_0_VM7_RANGE                        13:12
#define GPIO_I_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_I_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_I_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_I_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM8_SHIFT)
#define GPIO_I_VM_00_0_VM8_RANGE                        15:14
#define GPIO_I_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_I_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_I_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_00_0
#define GPIO_I_SCR_00_0                 MK_ADDR_CONST(0x4084)
#define GPIO_I_SCR_00_0_SECURE                  0x0
#define GPIO_I_SCR_00_0_DUAL                    0x0
#define GPIO_I_SCR_00_0_SCR                     0
#define GPIO_I_SCR_00_0_SCRREG                  0
#define GPIO_I_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_I_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_I_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_I_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_I_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_I_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_I_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_I_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_I_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR7_SHIFT)
#define GPIO_I_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_I_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR6_SHIFT)
#define GPIO_I_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_I_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR5_SHIFT)
#define GPIO_I_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_I_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR4_SHIFT)
#define GPIO_I_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_I_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR3_SHIFT)
#define GPIO_I_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_I_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR2_SHIFT)
#define GPIO_I_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_I_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR1_SHIFT)
#define GPIO_I_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_I_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR0_SHIFT)
#define GPIO_I_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_I_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G7W_SHIFT)
#define GPIO_I_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_I_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G6W_SHIFT)
#define GPIO_I_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_I_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G5W_SHIFT)
#define GPIO_I_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_I_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G4W_SHIFT)
#define GPIO_I_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_I_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G3W_SHIFT)
#define GPIO_I_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_I_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G2W_SHIFT)
#define GPIO_I_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_I_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G1W_SHIFT)
#define GPIO_I_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_I_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G0W_SHIFT)
#define GPIO_I_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_I_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G7R_SHIFT)
#define GPIO_I_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_I_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G6R_SHIFT)
#define GPIO_I_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G5R_SHIFT)
#define GPIO_I_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_I_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G4R_SHIFT)
#define GPIO_I_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_I_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G3R_SHIFT)
#define GPIO_I_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_I_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G2R_SHIFT)
#define GPIO_I_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_I_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G1R_SHIFT)
#define GPIO_I_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G0R_SHIFT)
#define GPIO_I_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_I_VM_01_0
#define GPIO_I_VM_01_0                  MK_ADDR_CONST(0x4088)
#define GPIO_I_VM_01_0_SECURE                   0x0
#define GPIO_I_VM_01_0_DUAL                     0x0
#define GPIO_I_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_01_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_01_0_WORD_COUNT                       0x1
#define GPIO_I_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM1_SHIFT)
#define GPIO_I_VM_01_0_VM1_RANGE                        1:0
#define GPIO_I_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_I_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_I_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM2_SHIFT)
#define GPIO_I_VM_01_0_VM2_RANGE                        3:2
#define GPIO_I_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_I_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_I_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_I_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM3_SHIFT)
#define GPIO_I_VM_01_0_VM3_RANGE                        5:4
#define GPIO_I_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_I_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_I_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_I_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM4_SHIFT)
#define GPIO_I_VM_01_0_VM4_RANGE                        7:6
#define GPIO_I_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_I_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_I_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_I_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM5_SHIFT)
#define GPIO_I_VM_01_0_VM5_RANGE                        9:8
#define GPIO_I_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_I_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_I_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_I_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM6_SHIFT)
#define GPIO_I_VM_01_0_VM6_RANGE                        11:10
#define GPIO_I_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_I_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_I_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_I_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM7_SHIFT)
#define GPIO_I_VM_01_0_VM7_RANGE                        13:12
#define GPIO_I_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_I_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_I_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_I_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM8_SHIFT)
#define GPIO_I_VM_01_0_VM8_RANGE                        15:14
#define GPIO_I_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_I_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_I_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_01_0
#define GPIO_I_SCR_01_0                 MK_ADDR_CONST(0x408c)
#define GPIO_I_SCR_01_0_SECURE                  0x0
#define GPIO_I_SCR_01_0_DUAL                    0x0
#define GPIO_I_SCR_01_0_SCR                     0
#define GPIO_I_SCR_01_0_SCRREG                  0
#define GPIO_I_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_I_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_I_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_I_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_I_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_I_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_I_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_I_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_I_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR7_SHIFT)
#define GPIO_I_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_I_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR6_SHIFT)
#define GPIO_I_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_I_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR5_SHIFT)
#define GPIO_I_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_I_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR4_SHIFT)
#define GPIO_I_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_I_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR3_SHIFT)
#define GPIO_I_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_I_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR2_SHIFT)
#define GPIO_I_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_I_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR1_SHIFT)
#define GPIO_I_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_I_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR0_SHIFT)
#define GPIO_I_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_I_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G7W_SHIFT)
#define GPIO_I_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_I_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G6W_SHIFT)
#define GPIO_I_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_I_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G5W_SHIFT)
#define GPIO_I_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_I_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G4W_SHIFT)
#define GPIO_I_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_I_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G3W_SHIFT)
#define GPIO_I_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_I_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G2W_SHIFT)
#define GPIO_I_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_I_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G1W_SHIFT)
#define GPIO_I_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_I_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G0W_SHIFT)
#define GPIO_I_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_I_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G7R_SHIFT)
#define GPIO_I_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_I_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G6R_SHIFT)
#define GPIO_I_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G5R_SHIFT)
#define GPIO_I_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_I_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G4R_SHIFT)
#define GPIO_I_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_I_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G3R_SHIFT)
#define GPIO_I_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_I_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G2R_SHIFT)
#define GPIO_I_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_I_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G1R_SHIFT)
#define GPIO_I_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G0R_SHIFT)
#define GPIO_I_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_I_VM_02_0
#define GPIO_I_VM_02_0                  MK_ADDR_CONST(0x4090)
#define GPIO_I_VM_02_0_SECURE                   0x0
#define GPIO_I_VM_02_0_DUAL                     0x0
#define GPIO_I_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_02_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_02_0_WORD_COUNT                       0x1
#define GPIO_I_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM1_SHIFT)
#define GPIO_I_VM_02_0_VM1_RANGE                        1:0
#define GPIO_I_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_I_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_I_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM2_SHIFT)
#define GPIO_I_VM_02_0_VM2_RANGE                        3:2
#define GPIO_I_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_I_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_I_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_I_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM3_SHIFT)
#define GPIO_I_VM_02_0_VM3_RANGE                        5:4
#define GPIO_I_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_I_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_I_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_I_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM4_SHIFT)
#define GPIO_I_VM_02_0_VM4_RANGE                        7:6
#define GPIO_I_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_I_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_I_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_I_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM5_SHIFT)
#define GPIO_I_VM_02_0_VM5_RANGE                        9:8
#define GPIO_I_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_I_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_I_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_I_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM6_SHIFT)
#define GPIO_I_VM_02_0_VM6_RANGE                        11:10
#define GPIO_I_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_I_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_I_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_I_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM7_SHIFT)
#define GPIO_I_VM_02_0_VM7_RANGE                        13:12
#define GPIO_I_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_I_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_I_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_I_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM8_SHIFT)
#define GPIO_I_VM_02_0_VM8_RANGE                        15:14
#define GPIO_I_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_I_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_I_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_02_0
#define GPIO_I_SCR_02_0                 MK_ADDR_CONST(0x4094)
#define GPIO_I_SCR_02_0_SECURE                  0x0
#define GPIO_I_SCR_02_0_DUAL                    0x0
#define GPIO_I_SCR_02_0_SCR                     0
#define GPIO_I_SCR_02_0_SCRREG                  0
#define GPIO_I_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_I_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_I_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_I_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_I_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_I_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_I_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_I_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_I_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR7_SHIFT)
#define GPIO_I_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_I_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR6_SHIFT)
#define GPIO_I_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_I_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR5_SHIFT)
#define GPIO_I_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_I_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR4_SHIFT)
#define GPIO_I_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_I_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR3_SHIFT)
#define GPIO_I_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_I_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR2_SHIFT)
#define GPIO_I_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_I_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR1_SHIFT)
#define GPIO_I_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_I_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR0_SHIFT)
#define GPIO_I_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_I_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G7W_SHIFT)
#define GPIO_I_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_I_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G6W_SHIFT)
#define GPIO_I_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_I_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G5W_SHIFT)
#define GPIO_I_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_I_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G4W_SHIFT)
#define GPIO_I_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_I_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G3W_SHIFT)
#define GPIO_I_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_I_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G2W_SHIFT)
#define GPIO_I_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_I_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G1W_SHIFT)
#define GPIO_I_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_I_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G0W_SHIFT)
#define GPIO_I_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_I_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G7R_SHIFT)
#define GPIO_I_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_I_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G6R_SHIFT)
#define GPIO_I_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G5R_SHIFT)
#define GPIO_I_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_I_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G4R_SHIFT)
#define GPIO_I_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_I_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G3R_SHIFT)
#define GPIO_I_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_I_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G2R_SHIFT)
#define GPIO_I_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_I_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G1R_SHIFT)
#define GPIO_I_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G0R_SHIFT)
#define GPIO_I_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_I_VM_03_0
#define GPIO_I_VM_03_0                  MK_ADDR_CONST(0x4098)
#define GPIO_I_VM_03_0_SECURE                   0x0
#define GPIO_I_VM_03_0_DUAL                     0x0
#define GPIO_I_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_03_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_03_0_WORD_COUNT                       0x1
#define GPIO_I_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM1_SHIFT)
#define GPIO_I_VM_03_0_VM1_RANGE                        1:0
#define GPIO_I_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_I_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_I_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM2_SHIFT)
#define GPIO_I_VM_03_0_VM2_RANGE                        3:2
#define GPIO_I_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_I_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_I_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_I_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM3_SHIFT)
#define GPIO_I_VM_03_0_VM3_RANGE                        5:4
#define GPIO_I_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_I_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_I_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_I_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM4_SHIFT)
#define GPIO_I_VM_03_0_VM4_RANGE                        7:6
#define GPIO_I_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_I_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_I_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_I_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM5_SHIFT)
#define GPIO_I_VM_03_0_VM5_RANGE                        9:8
#define GPIO_I_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_I_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_I_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_I_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM6_SHIFT)
#define GPIO_I_VM_03_0_VM6_RANGE                        11:10
#define GPIO_I_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_I_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_I_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_I_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM7_SHIFT)
#define GPIO_I_VM_03_0_VM7_RANGE                        13:12
#define GPIO_I_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_I_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_I_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_I_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM8_SHIFT)
#define GPIO_I_VM_03_0_VM8_RANGE                        15:14
#define GPIO_I_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_I_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_I_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_03_0
#define GPIO_I_SCR_03_0                 MK_ADDR_CONST(0x409c)
#define GPIO_I_SCR_03_0_SECURE                  0x0
#define GPIO_I_SCR_03_0_DUAL                    0x0
#define GPIO_I_SCR_03_0_SCR                     0
#define GPIO_I_SCR_03_0_SCRREG                  0
#define GPIO_I_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_I_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_I_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_I_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_I_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_I_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_I_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_I_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_I_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR7_SHIFT)
#define GPIO_I_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_I_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR6_SHIFT)
#define GPIO_I_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_I_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR5_SHIFT)
#define GPIO_I_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_I_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR4_SHIFT)
#define GPIO_I_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_I_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR3_SHIFT)
#define GPIO_I_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_I_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR2_SHIFT)
#define GPIO_I_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_I_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR1_SHIFT)
#define GPIO_I_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_I_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR0_SHIFT)
#define GPIO_I_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_I_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G7W_SHIFT)
#define GPIO_I_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_I_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G6W_SHIFT)
#define GPIO_I_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_I_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G5W_SHIFT)
#define GPIO_I_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_I_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G4W_SHIFT)
#define GPIO_I_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_I_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G3W_SHIFT)
#define GPIO_I_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_I_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G2W_SHIFT)
#define GPIO_I_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_I_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G1W_SHIFT)
#define GPIO_I_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_I_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G0W_SHIFT)
#define GPIO_I_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_I_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G7R_SHIFT)
#define GPIO_I_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_I_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G6R_SHIFT)
#define GPIO_I_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G5R_SHIFT)
#define GPIO_I_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_I_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G4R_SHIFT)
#define GPIO_I_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_I_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G3R_SHIFT)
#define GPIO_I_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_I_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G2R_SHIFT)
#define GPIO_I_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_I_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G1R_SHIFT)
#define GPIO_I_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G0R_SHIFT)
#define GPIO_I_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_I_VM_04_0
#define GPIO_I_VM_04_0                  MK_ADDR_CONST(0x40a0)
#define GPIO_I_VM_04_0_SECURE                   0x0
#define GPIO_I_VM_04_0_DUAL                     0x0
#define GPIO_I_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_04_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_04_0_WORD_COUNT                       0x1
#define GPIO_I_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM1_SHIFT)
#define GPIO_I_VM_04_0_VM1_RANGE                        1:0
#define GPIO_I_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_I_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_I_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM2_SHIFT)
#define GPIO_I_VM_04_0_VM2_RANGE                        3:2
#define GPIO_I_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_I_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_I_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_I_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM3_SHIFT)
#define GPIO_I_VM_04_0_VM3_RANGE                        5:4
#define GPIO_I_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_I_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_I_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_I_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM4_SHIFT)
#define GPIO_I_VM_04_0_VM4_RANGE                        7:6
#define GPIO_I_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_I_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_I_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_I_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM5_SHIFT)
#define GPIO_I_VM_04_0_VM5_RANGE                        9:8
#define GPIO_I_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_I_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_I_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_I_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM6_SHIFT)
#define GPIO_I_VM_04_0_VM6_RANGE                        11:10
#define GPIO_I_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_I_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_I_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_I_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM7_SHIFT)
#define GPIO_I_VM_04_0_VM7_RANGE                        13:12
#define GPIO_I_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_I_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_I_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_I_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM8_SHIFT)
#define GPIO_I_VM_04_0_VM8_RANGE                        15:14
#define GPIO_I_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_I_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_I_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_04_0
#define GPIO_I_SCR_04_0                 MK_ADDR_CONST(0x40a4)
#define GPIO_I_SCR_04_0_SECURE                  0x0
#define GPIO_I_SCR_04_0_DUAL                    0x0
#define GPIO_I_SCR_04_0_SCR                     0
#define GPIO_I_SCR_04_0_SCRREG                  0
#define GPIO_I_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_I_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_I_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_I_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_I_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_I_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_I_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_I_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_I_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR7_SHIFT)
#define GPIO_I_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_I_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR6_SHIFT)
#define GPIO_I_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_I_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR5_SHIFT)
#define GPIO_I_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_I_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR4_SHIFT)
#define GPIO_I_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_I_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR3_SHIFT)
#define GPIO_I_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_I_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR2_SHIFT)
#define GPIO_I_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_I_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR1_SHIFT)
#define GPIO_I_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_I_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR0_SHIFT)
#define GPIO_I_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_I_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G7W_SHIFT)
#define GPIO_I_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_I_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G6W_SHIFT)
#define GPIO_I_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_I_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G5W_SHIFT)
#define GPIO_I_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_I_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G4W_SHIFT)
#define GPIO_I_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_I_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G3W_SHIFT)
#define GPIO_I_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_I_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G2W_SHIFT)
#define GPIO_I_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_I_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G1W_SHIFT)
#define GPIO_I_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_I_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G0W_SHIFT)
#define GPIO_I_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_I_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G7R_SHIFT)
#define GPIO_I_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_I_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G6R_SHIFT)
#define GPIO_I_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G5R_SHIFT)
#define GPIO_I_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_I_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G4R_SHIFT)
#define GPIO_I_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_I_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G3R_SHIFT)
#define GPIO_I_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_I_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G2R_SHIFT)
#define GPIO_I_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_I_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G1R_SHIFT)
#define GPIO_I_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G0R_SHIFT)
#define GPIO_I_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_I_VM_05_0
#define GPIO_I_VM_05_0                  MK_ADDR_CONST(0x40a8)
#define GPIO_I_VM_05_0_SECURE                   0x0
#define GPIO_I_VM_05_0_DUAL                     0x0
#define GPIO_I_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_05_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_05_0_WORD_COUNT                       0x1
#define GPIO_I_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM1_SHIFT)
#define GPIO_I_VM_05_0_VM1_RANGE                        1:0
#define GPIO_I_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_I_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_I_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM2_SHIFT)
#define GPIO_I_VM_05_0_VM2_RANGE                        3:2
#define GPIO_I_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_I_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_I_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_I_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM3_SHIFT)
#define GPIO_I_VM_05_0_VM3_RANGE                        5:4
#define GPIO_I_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_I_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_I_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_I_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM4_SHIFT)
#define GPIO_I_VM_05_0_VM4_RANGE                        7:6
#define GPIO_I_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_I_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_I_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_I_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM5_SHIFT)
#define GPIO_I_VM_05_0_VM5_RANGE                        9:8
#define GPIO_I_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_I_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_I_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_I_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM6_SHIFT)
#define GPIO_I_VM_05_0_VM6_RANGE                        11:10
#define GPIO_I_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_I_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_I_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_I_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM7_SHIFT)
#define GPIO_I_VM_05_0_VM7_RANGE                        13:12
#define GPIO_I_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_I_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_I_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_I_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM8_SHIFT)
#define GPIO_I_VM_05_0_VM8_RANGE                        15:14
#define GPIO_I_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_I_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_I_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_05_0
#define GPIO_I_SCR_05_0                 MK_ADDR_CONST(0x40ac)
#define GPIO_I_SCR_05_0_SECURE                  0x0
#define GPIO_I_SCR_05_0_DUAL                    0x0
#define GPIO_I_SCR_05_0_SCR                     0
#define GPIO_I_SCR_05_0_SCRREG                  0
#define GPIO_I_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_I_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_I_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_I_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_I_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_I_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_I_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_I_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_I_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR7_SHIFT)
#define GPIO_I_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_I_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR6_SHIFT)
#define GPIO_I_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_I_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR5_SHIFT)
#define GPIO_I_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_I_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR4_SHIFT)
#define GPIO_I_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_I_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR3_SHIFT)
#define GPIO_I_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_I_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR2_SHIFT)
#define GPIO_I_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_I_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR1_SHIFT)
#define GPIO_I_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_I_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR0_SHIFT)
#define GPIO_I_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_I_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G7W_SHIFT)
#define GPIO_I_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_I_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G6W_SHIFT)
#define GPIO_I_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_I_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G5W_SHIFT)
#define GPIO_I_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_I_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G4W_SHIFT)
#define GPIO_I_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_I_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G3W_SHIFT)
#define GPIO_I_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_I_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G2W_SHIFT)
#define GPIO_I_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_I_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G1W_SHIFT)
#define GPIO_I_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_I_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G0W_SHIFT)
#define GPIO_I_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_I_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G7R_SHIFT)
#define GPIO_I_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_I_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G6R_SHIFT)
#define GPIO_I_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G5R_SHIFT)
#define GPIO_I_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_I_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G4R_SHIFT)
#define GPIO_I_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_I_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G3R_SHIFT)
#define GPIO_I_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_I_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G2R_SHIFT)
#define GPIO_I_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_I_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G1R_SHIFT)
#define GPIO_I_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G0R_SHIFT)
#define GPIO_I_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_I_VM_06_0
#define GPIO_I_VM_06_0                  MK_ADDR_CONST(0x40b0)
#define GPIO_I_VM_06_0_SECURE                   0x0
#define GPIO_I_VM_06_0_DUAL                     0x0
#define GPIO_I_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_06_0_SCRREG                   GPIO_CTL4_VM_SCR_0
#define GPIO_I_VM_06_0_WORD_COUNT                       0x1
#define GPIO_I_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_I_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_I_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM1_SHIFT)
#define GPIO_I_VM_06_0_VM1_RANGE                        1:0
#define GPIO_I_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_I_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_I_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM2_SHIFT)
#define GPIO_I_VM_06_0_VM2_RANGE                        3:2
#define GPIO_I_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_I_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_I_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_I_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM3_SHIFT)
#define GPIO_I_VM_06_0_VM3_RANGE                        5:4
#define GPIO_I_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_I_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_I_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_I_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM4_SHIFT)
#define GPIO_I_VM_06_0_VM4_RANGE                        7:6
#define GPIO_I_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_I_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_I_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_I_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM5_SHIFT)
#define GPIO_I_VM_06_0_VM5_RANGE                        9:8
#define GPIO_I_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_I_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_I_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_I_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM6_SHIFT)
#define GPIO_I_VM_06_0_VM6_RANGE                        11:10
#define GPIO_I_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_I_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_I_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_I_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM7_SHIFT)
#define GPIO_I_VM_06_0_VM7_RANGE                        13:12
#define GPIO_I_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_I_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_I_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_I_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_I_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM8_SHIFT)
#define GPIO_I_VM_06_0_VM8_RANGE                        15:14
#define GPIO_I_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_I_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_I_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_I_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_I_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_SCR_06_0
#define GPIO_I_SCR_06_0                 MK_ADDR_CONST(0x40b4)
#define GPIO_I_SCR_06_0_SECURE                  0x0
#define GPIO_I_SCR_06_0_DUAL                    0x0
#define GPIO_I_SCR_06_0_SCR                     0
#define GPIO_I_SCR_06_0_SCRREG                  0
#define GPIO_I_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_I_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_I_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_I_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_I_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_I_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_I_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_I_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_I_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_I_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_I_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_I_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_I_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_I_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_I_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_I_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_I_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_I_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_I_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_I_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_I_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_I_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_I_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_I_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_I_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_I_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR7_SHIFT)
#define GPIO_I_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_I_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_I_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_I_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR6_SHIFT)
#define GPIO_I_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_I_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_I_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_I_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR5_SHIFT)
#define GPIO_I_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_I_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_I_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_I_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR4_SHIFT)
#define GPIO_I_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_I_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_I_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_I_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR3_SHIFT)
#define GPIO_I_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_I_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_I_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_I_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR2_SHIFT)
#define GPIO_I_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_I_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_I_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_I_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR1_SHIFT)
#define GPIO_I_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_I_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_I_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_I_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR0_SHIFT)
#define GPIO_I_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_I_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_I_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_I_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G7W_SHIFT)
#define GPIO_I_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_I_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_I_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_I_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G6W_SHIFT)
#define GPIO_I_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_I_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_I_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_I_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G5W_SHIFT)
#define GPIO_I_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_I_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_I_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_I_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G4W_SHIFT)
#define GPIO_I_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_I_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_I_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_I_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G3W_SHIFT)
#define GPIO_I_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_I_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_I_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_I_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G2W_SHIFT)
#define GPIO_I_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_I_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_I_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_I_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G1W_SHIFT)
#define GPIO_I_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_I_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_I_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_I_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G0W_SHIFT)
#define GPIO_I_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_I_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_I_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_I_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G7R_SHIFT)
#define GPIO_I_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_I_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_I_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_I_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G6R_SHIFT)
#define GPIO_I_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_I_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_I_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G5R_SHIFT)
#define GPIO_I_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_I_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_I_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G4R_SHIFT)
#define GPIO_I_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_I_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_I_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_I_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G3R_SHIFT)
#define GPIO_I_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_I_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_I_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_I_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G2R_SHIFT)
#define GPIO_I_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_I_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_I_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_I_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G1R_SHIFT)
#define GPIO_I_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_I_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_I_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_I_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G0R_SHIFT)
#define GPIO_I_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_I_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_I_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_I_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x40b8

// Reserved address 0x40bc

// Register GPIO_CTL4_VM_SCR_0
#define GPIO_CTL4_VM_SCR_0                      MK_ADDR_CONST(0x4800)
#define GPIO_CTL4_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL4_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL4_VM_SCR_0_SCR                  0
#define GPIO_CTL4_VM_SCR_0_SCRREG                       0
#define GPIO_CTL4_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL4_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL4_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL4_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL4_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define GPIO_CTL4_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL4_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL4_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL4_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define GPIO_CTL4_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL4_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL4_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL4_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define GPIO_CTL4_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL4_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL4_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL4_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define GPIO_CTL4_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL4_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL4_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL4_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define GPIO_CTL4_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL4_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL4_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL4_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define GPIO_CTL4_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL4_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL4_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL4_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define GPIO_CTL4_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL4_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL4_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL4_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define GPIO_CTL4_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL4_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL4_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL4_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define GPIO_CTL4_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL4_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL4_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL4_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define GPIO_CTL4_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL4_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL4_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL4_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define GPIO_CTL4_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL4_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL4_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL4_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define GPIO_CTL4_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL4_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL4_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL4_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define GPIO_CTL4_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL4_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL4_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL4_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define GPIO_CTL4_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL4_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL4_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL4_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define GPIO_CTL4_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL4_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL4_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL4_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define GPIO_CTL4_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL4_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL4_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL4_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define GPIO_CTL4_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL4_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL4_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL4_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define GPIO_CTL4_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL4_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL4_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL4_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define GPIO_CTL4_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL4_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL4_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL4_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define GPIO_CTL4_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL4_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL4_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL4_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define GPIO_CTL4_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL4_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL4_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL4_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_CTL4_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL4_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL4_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL4_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define GPIO_CTL4_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL4_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL4_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL4_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL4_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CTL4_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL4_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL4_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL4_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL4_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL4_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x4804)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL4_INTERRUPT_STATUS_VM_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x4808)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_CTL4_SCR_0
#define GPIO_CTL4_SCR_0                 MK_ADDR_CONST(0x480c)
#define GPIO_CTL4_SCR_0_SECURE                  0x0
#define GPIO_CTL4_SCR_0_DUAL                    0x0
#define GPIO_CTL4_SCR_0_SCR                     0
#define GPIO_CTL4_SCR_0_SCRREG                  0
#define GPIO_CTL4_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL4_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL4_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_CTL4_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL4_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL4_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL4_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_CTL4_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL4_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL4_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL4_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_CTL4_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL4_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL4_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL4_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL4_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_CTL4_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL4_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL4_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL4_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_CTL4_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_CTL4_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL4_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_CTL4_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_CTL4_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR7_SHIFT)
#define GPIO_CTL4_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL4_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL4_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL4_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_CTL4_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR6_SHIFT)
#define GPIO_CTL4_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL4_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL4_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL4_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_CTL4_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR5_SHIFT)
#define GPIO_CTL4_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL4_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL4_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL4_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_CTL4_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR4_SHIFT)
#define GPIO_CTL4_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL4_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL4_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL4_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_CTL4_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR3_SHIFT)
#define GPIO_CTL4_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL4_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL4_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL4_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_CTL4_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR2_SHIFT)
#define GPIO_CTL4_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL4_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL4_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL4_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_CTL4_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR1_SHIFT)
#define GPIO_CTL4_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL4_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL4_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL4_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_CTL4_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR0_SHIFT)
#define GPIO_CTL4_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL4_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL4_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL4_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_CTL4_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G7W_SHIFT)
#define GPIO_CTL4_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL4_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL4_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL4_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_CTL4_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G6W_SHIFT)
#define GPIO_CTL4_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL4_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL4_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL4_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_CTL4_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G5W_SHIFT)
#define GPIO_CTL4_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL4_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL4_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL4_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_CTL4_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G4W_SHIFT)
#define GPIO_CTL4_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL4_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL4_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL4_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_CTL4_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G3W_SHIFT)
#define GPIO_CTL4_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL4_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL4_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL4_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_CTL4_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G2W_SHIFT)
#define GPIO_CTL4_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL4_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL4_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL4_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_CTL4_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G1W_SHIFT)
#define GPIO_CTL4_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL4_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL4_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL4_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_CTL4_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G0W_SHIFT)
#define GPIO_CTL4_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL4_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL4_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL4_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_CTL4_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G7R_SHIFT)
#define GPIO_CTL4_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL4_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL4_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL4_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_CTL4_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G6R_SHIFT)
#define GPIO_CTL4_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL4_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL4_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL4_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_CTL4_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G5R_SHIFT)
#define GPIO_CTL4_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL4_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL4_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL4_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_CTL4_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G4R_SHIFT)
#define GPIO_CTL4_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL4_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL4_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL4_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_CTL4_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G3R_SHIFT)
#define GPIO_CTL4_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL4_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL4_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL4_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_CTL4_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G2R_SHIFT)
#define GPIO_CTL4_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL4_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL4_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL4_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_CTL4_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G1R_SHIFT)
#define GPIO_CTL4_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL4_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL4_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL4_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL4_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CTL4_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G0R_SHIFT)
#define GPIO_CTL4_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL4_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL4_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL4_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL4_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL4_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CTL4_ICG_EN_OVERRIDE_0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x4810)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_G_INT0_ROUTE_MAPPING_0
#define GPIO_G_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4814)
#define GPIO_G_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_G_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_G_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_G_INT1_ROUTE_MAPPING_0
#define GPIO_G_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4818)
#define GPIO_G_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_G_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_G_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_G_INT2_ROUTE_MAPPING_0
#define GPIO_G_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x481c)
#define GPIO_G_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_G_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_G_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_G_INT3_ROUTE_MAPPING_0
#define GPIO_G_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4820)
#define GPIO_G_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_G_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_G_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_G_INT4_ROUTE_MAPPING_0
#define GPIO_G_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4824)
#define GPIO_G_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_G_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_G_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_G_INT5_ROUTE_MAPPING_0
#define GPIO_G_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4828)
#define GPIO_G_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_G_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_G_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_G_INT6_ROUTE_MAPPING_0
#define GPIO_G_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x482c)
#define GPIO_G_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_G_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_G_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_G_INT7_ROUTE_MAPPING_0
#define GPIO_G_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4830)
#define GPIO_G_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_G_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_G_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_G_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_G_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_G_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_G_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_H_INT0_ROUTE_MAPPING_0
#define GPIO_H_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4834)
#define GPIO_H_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_H_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_H_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_H_INT1_ROUTE_MAPPING_0
#define GPIO_H_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4838)
#define GPIO_H_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_H_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_H_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_H_INT2_ROUTE_MAPPING_0
#define GPIO_H_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x483c)
#define GPIO_H_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_H_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_H_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_H_INT3_ROUTE_MAPPING_0
#define GPIO_H_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4840)
#define GPIO_H_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_H_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_H_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_H_INT4_ROUTE_MAPPING_0
#define GPIO_H_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4844)
#define GPIO_H_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_H_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_H_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_H_INT5_ROUTE_MAPPING_0
#define GPIO_H_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4848)
#define GPIO_H_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_H_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_H_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_H_INT6_ROUTE_MAPPING_0
#define GPIO_H_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x484c)
#define GPIO_H_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_H_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_H_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_H_INT7_ROUTE_MAPPING_0
#define GPIO_H_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4850)
#define GPIO_H_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_H_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_H_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_H_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_H_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_H_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_H_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_I_INT0_ROUTE_MAPPING_0
#define GPIO_I_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4854)
#define GPIO_I_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_I_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define GPIO_I_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_RANGE                   6:0
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_I_INT1_ROUTE_MAPPING_0
#define GPIO_I_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4858)
#define GPIO_I_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_I_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define GPIO_I_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_RANGE                   6:0
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_I_INT2_ROUTE_MAPPING_0
#define GPIO_I_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x485c)
#define GPIO_I_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_I_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define GPIO_I_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_RANGE                   6:0
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_I_INT3_ROUTE_MAPPING_0
#define GPIO_I_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4860)
#define GPIO_I_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_I_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define GPIO_I_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_RANGE                   6:0
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_I_INT4_ROUTE_MAPPING_0
#define GPIO_I_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4864)
#define GPIO_I_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_I_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define GPIO_I_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_RANGE                   6:0
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_I_INT5_ROUTE_MAPPING_0
#define GPIO_I_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4868)
#define GPIO_I_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_I_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define GPIO_I_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_RANGE                   6:0
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_I_INT6_ROUTE_MAPPING_0
#define GPIO_I_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x486c)
#define GPIO_I_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_I_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define GPIO_I_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_RANGE                   6:0
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_I_INT7_ROUTE_MAPPING_0
#define GPIO_I_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4870)
#define GPIO_I_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_I_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_I_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
#define GPIO_I_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
#define GPIO_I_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_I_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
#define GPIO_I_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_RANGE                   6:0
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL4_SPARE_0
#define GPIO_CTL4_SPARE_0                       MK_ADDR_CONST(0x4874)
#define GPIO_CTL4_SPARE_0_SECURE                        0x0
#define GPIO_CTL4_SPARE_0_DUAL                  0x0
#define GPIO_CTL4_SPARE_0_SCR                   0
#define GPIO_CTL4_SPARE_0_SCRREG                        0
#define GPIO_CTL4_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL4_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL4_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL4_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL4_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL4_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL4_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL4_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL4_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL4_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL4_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_J_VM_00_0
#define GPIO_J_VM_00_0                  MK_ADDR_CONST(0x5000)
#define GPIO_J_VM_00_0_SECURE                   0x0
#define GPIO_J_VM_00_0_DUAL                     0x0
#define GPIO_J_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_00_0_WORD_COUNT                       0x1
#define GPIO_J_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM1_SHIFT)
#define GPIO_J_VM_00_0_VM1_RANGE                        1:0
#define GPIO_J_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_J_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_J_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM2_SHIFT)
#define GPIO_J_VM_00_0_VM2_RANGE                        3:2
#define GPIO_J_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_J_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_J_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_J_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM3_SHIFT)
#define GPIO_J_VM_00_0_VM3_RANGE                        5:4
#define GPIO_J_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_J_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_J_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM4_SHIFT)
#define GPIO_J_VM_00_0_VM4_RANGE                        7:6
#define GPIO_J_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_J_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_J_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_J_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM5_SHIFT)
#define GPIO_J_VM_00_0_VM5_RANGE                        9:8
#define GPIO_J_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_J_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_J_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_J_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM6_SHIFT)
#define GPIO_J_VM_00_0_VM6_RANGE                        11:10
#define GPIO_J_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_J_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_J_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_J_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM7_SHIFT)
#define GPIO_J_VM_00_0_VM7_RANGE                        13:12
#define GPIO_J_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_J_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_J_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_J_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM8_SHIFT)
#define GPIO_J_VM_00_0_VM8_RANGE                        15:14
#define GPIO_J_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_J_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_J_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_00_0
#define GPIO_J_SCR_00_0                 MK_ADDR_CONST(0x5004)
#define GPIO_J_SCR_00_0_SECURE                  0x0
#define GPIO_J_SCR_00_0_DUAL                    0x0
#define GPIO_J_SCR_00_0_SCR                     0
#define GPIO_J_SCR_00_0_SCRREG                  0
#define GPIO_J_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_J_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_J_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_J_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_J_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_J_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_J_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_J_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_J_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR7_SHIFT)
#define GPIO_J_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_J_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR6_SHIFT)
#define GPIO_J_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_J_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR5_SHIFT)
#define GPIO_J_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_J_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR4_SHIFT)
#define GPIO_J_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_J_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR3_SHIFT)
#define GPIO_J_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_J_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR2_SHIFT)
#define GPIO_J_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_J_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR1_SHIFT)
#define GPIO_J_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_J_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR0_SHIFT)
#define GPIO_J_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_J_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G7W_SHIFT)
#define GPIO_J_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_J_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G6W_SHIFT)
#define GPIO_J_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_J_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G5W_SHIFT)
#define GPIO_J_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_J_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G4W_SHIFT)
#define GPIO_J_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_J_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G3W_SHIFT)
#define GPIO_J_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_J_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G2W_SHIFT)
#define GPIO_J_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_J_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G1W_SHIFT)
#define GPIO_J_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_J_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G0W_SHIFT)
#define GPIO_J_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_J_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G7R_SHIFT)
#define GPIO_J_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_J_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G6R_SHIFT)
#define GPIO_J_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G5R_SHIFT)
#define GPIO_J_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_J_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G4R_SHIFT)
#define GPIO_J_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_J_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G3R_SHIFT)
#define GPIO_J_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_J_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G2R_SHIFT)
#define GPIO_J_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_J_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G1R_SHIFT)
#define GPIO_J_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G0R_SHIFT)
#define GPIO_J_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_J_VM_01_0
#define GPIO_J_VM_01_0                  MK_ADDR_CONST(0x5008)
#define GPIO_J_VM_01_0_SECURE                   0x0
#define GPIO_J_VM_01_0_DUAL                     0x0
#define GPIO_J_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_01_0_WORD_COUNT                       0x1
#define GPIO_J_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM1_SHIFT)
#define GPIO_J_VM_01_0_VM1_RANGE                        1:0
#define GPIO_J_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_J_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_J_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM2_SHIFT)
#define GPIO_J_VM_01_0_VM2_RANGE                        3:2
#define GPIO_J_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_J_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_J_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_J_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM3_SHIFT)
#define GPIO_J_VM_01_0_VM3_RANGE                        5:4
#define GPIO_J_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_J_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_J_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM4_SHIFT)
#define GPIO_J_VM_01_0_VM4_RANGE                        7:6
#define GPIO_J_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_J_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_J_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_J_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM5_SHIFT)
#define GPIO_J_VM_01_0_VM5_RANGE                        9:8
#define GPIO_J_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_J_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_J_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_J_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM6_SHIFT)
#define GPIO_J_VM_01_0_VM6_RANGE                        11:10
#define GPIO_J_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_J_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_J_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_J_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM7_SHIFT)
#define GPIO_J_VM_01_0_VM7_RANGE                        13:12
#define GPIO_J_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_J_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_J_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_J_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM8_SHIFT)
#define GPIO_J_VM_01_0_VM8_RANGE                        15:14
#define GPIO_J_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_J_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_J_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_01_0
#define GPIO_J_SCR_01_0                 MK_ADDR_CONST(0x500c)
#define GPIO_J_SCR_01_0_SECURE                  0x0
#define GPIO_J_SCR_01_0_DUAL                    0x0
#define GPIO_J_SCR_01_0_SCR                     0
#define GPIO_J_SCR_01_0_SCRREG                  0
#define GPIO_J_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_J_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_J_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_J_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_J_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_J_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_J_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_J_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_J_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR7_SHIFT)
#define GPIO_J_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_J_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR6_SHIFT)
#define GPIO_J_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_J_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR5_SHIFT)
#define GPIO_J_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_J_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR4_SHIFT)
#define GPIO_J_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_J_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR3_SHIFT)
#define GPIO_J_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_J_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR2_SHIFT)
#define GPIO_J_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_J_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR1_SHIFT)
#define GPIO_J_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_J_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR0_SHIFT)
#define GPIO_J_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_J_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G7W_SHIFT)
#define GPIO_J_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_J_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G6W_SHIFT)
#define GPIO_J_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_J_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G5W_SHIFT)
#define GPIO_J_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_J_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G4W_SHIFT)
#define GPIO_J_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_J_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G3W_SHIFT)
#define GPIO_J_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_J_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G2W_SHIFT)
#define GPIO_J_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_J_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G1W_SHIFT)
#define GPIO_J_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_J_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G0W_SHIFT)
#define GPIO_J_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_J_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G7R_SHIFT)
#define GPIO_J_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_J_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G6R_SHIFT)
#define GPIO_J_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G5R_SHIFT)
#define GPIO_J_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_J_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G4R_SHIFT)
#define GPIO_J_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_J_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G3R_SHIFT)
#define GPIO_J_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_J_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G2R_SHIFT)
#define GPIO_J_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_J_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G1R_SHIFT)
#define GPIO_J_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G0R_SHIFT)
#define GPIO_J_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_J_VM_02_0
#define GPIO_J_VM_02_0                  MK_ADDR_CONST(0x5010)
#define GPIO_J_VM_02_0_SECURE                   0x0
#define GPIO_J_VM_02_0_DUAL                     0x0
#define GPIO_J_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_02_0_WORD_COUNT                       0x1
#define GPIO_J_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM1_SHIFT)
#define GPIO_J_VM_02_0_VM1_RANGE                        1:0
#define GPIO_J_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_J_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_J_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM2_SHIFT)
#define GPIO_J_VM_02_0_VM2_RANGE                        3:2
#define GPIO_J_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_J_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_J_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_J_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM3_SHIFT)
#define GPIO_J_VM_02_0_VM3_RANGE                        5:4
#define GPIO_J_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_J_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_J_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM4_SHIFT)
#define GPIO_J_VM_02_0_VM4_RANGE                        7:6
#define GPIO_J_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_J_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_J_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_J_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM5_SHIFT)
#define GPIO_J_VM_02_0_VM5_RANGE                        9:8
#define GPIO_J_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_J_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_J_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_J_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM6_SHIFT)
#define GPIO_J_VM_02_0_VM6_RANGE                        11:10
#define GPIO_J_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_J_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_J_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_J_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM7_SHIFT)
#define GPIO_J_VM_02_0_VM7_RANGE                        13:12
#define GPIO_J_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_J_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_J_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_J_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM8_SHIFT)
#define GPIO_J_VM_02_0_VM8_RANGE                        15:14
#define GPIO_J_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_J_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_J_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_02_0
#define GPIO_J_SCR_02_0                 MK_ADDR_CONST(0x5014)
#define GPIO_J_SCR_02_0_SECURE                  0x0
#define GPIO_J_SCR_02_0_DUAL                    0x0
#define GPIO_J_SCR_02_0_SCR                     0
#define GPIO_J_SCR_02_0_SCRREG                  0
#define GPIO_J_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_J_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_J_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_J_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_J_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_J_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_J_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_J_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_J_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR7_SHIFT)
#define GPIO_J_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_J_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR6_SHIFT)
#define GPIO_J_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_J_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR5_SHIFT)
#define GPIO_J_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_J_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR4_SHIFT)
#define GPIO_J_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_J_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR3_SHIFT)
#define GPIO_J_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_J_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR2_SHIFT)
#define GPIO_J_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_J_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR1_SHIFT)
#define GPIO_J_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_J_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR0_SHIFT)
#define GPIO_J_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_J_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G7W_SHIFT)
#define GPIO_J_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_J_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G6W_SHIFT)
#define GPIO_J_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_J_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G5W_SHIFT)
#define GPIO_J_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_J_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G4W_SHIFT)
#define GPIO_J_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_J_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G3W_SHIFT)
#define GPIO_J_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_J_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G2W_SHIFT)
#define GPIO_J_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_J_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G1W_SHIFT)
#define GPIO_J_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_J_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G0W_SHIFT)
#define GPIO_J_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_J_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G7R_SHIFT)
#define GPIO_J_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_J_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G6R_SHIFT)
#define GPIO_J_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G5R_SHIFT)
#define GPIO_J_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_J_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G4R_SHIFT)
#define GPIO_J_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_J_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G3R_SHIFT)
#define GPIO_J_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_J_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G2R_SHIFT)
#define GPIO_J_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_J_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G1R_SHIFT)
#define GPIO_J_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G0R_SHIFT)
#define GPIO_J_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_J_VM_03_0
#define GPIO_J_VM_03_0                  MK_ADDR_CONST(0x5018)
#define GPIO_J_VM_03_0_SECURE                   0x0
#define GPIO_J_VM_03_0_DUAL                     0x0
#define GPIO_J_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_03_0_WORD_COUNT                       0x1
#define GPIO_J_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM1_SHIFT)
#define GPIO_J_VM_03_0_VM1_RANGE                        1:0
#define GPIO_J_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_J_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_J_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM2_SHIFT)
#define GPIO_J_VM_03_0_VM2_RANGE                        3:2
#define GPIO_J_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_J_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_J_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_J_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM3_SHIFT)
#define GPIO_J_VM_03_0_VM3_RANGE                        5:4
#define GPIO_J_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_J_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_J_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM4_SHIFT)
#define GPIO_J_VM_03_0_VM4_RANGE                        7:6
#define GPIO_J_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_J_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_J_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_J_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM5_SHIFT)
#define GPIO_J_VM_03_0_VM5_RANGE                        9:8
#define GPIO_J_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_J_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_J_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_J_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM6_SHIFT)
#define GPIO_J_VM_03_0_VM6_RANGE                        11:10
#define GPIO_J_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_J_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_J_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_J_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM7_SHIFT)
#define GPIO_J_VM_03_0_VM7_RANGE                        13:12
#define GPIO_J_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_J_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_J_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_J_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM8_SHIFT)
#define GPIO_J_VM_03_0_VM8_RANGE                        15:14
#define GPIO_J_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_J_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_J_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_03_0
#define GPIO_J_SCR_03_0                 MK_ADDR_CONST(0x501c)
#define GPIO_J_SCR_03_0_SECURE                  0x0
#define GPIO_J_SCR_03_0_DUAL                    0x0
#define GPIO_J_SCR_03_0_SCR                     0
#define GPIO_J_SCR_03_0_SCRREG                  0
#define GPIO_J_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_J_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_J_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_J_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_J_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_J_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_J_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_J_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_J_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR7_SHIFT)
#define GPIO_J_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_J_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR6_SHIFT)
#define GPIO_J_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_J_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR5_SHIFT)
#define GPIO_J_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_J_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR4_SHIFT)
#define GPIO_J_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_J_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR3_SHIFT)
#define GPIO_J_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_J_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR2_SHIFT)
#define GPIO_J_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_J_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR1_SHIFT)
#define GPIO_J_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_J_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR0_SHIFT)
#define GPIO_J_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_J_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G7W_SHIFT)
#define GPIO_J_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_J_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G6W_SHIFT)
#define GPIO_J_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_J_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G5W_SHIFT)
#define GPIO_J_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_J_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G4W_SHIFT)
#define GPIO_J_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_J_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G3W_SHIFT)
#define GPIO_J_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_J_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G2W_SHIFT)
#define GPIO_J_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_J_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G1W_SHIFT)
#define GPIO_J_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_J_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G0W_SHIFT)
#define GPIO_J_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_J_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G7R_SHIFT)
#define GPIO_J_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_J_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G6R_SHIFT)
#define GPIO_J_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G5R_SHIFT)
#define GPIO_J_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_J_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G4R_SHIFT)
#define GPIO_J_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_J_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G3R_SHIFT)
#define GPIO_J_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_J_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G2R_SHIFT)
#define GPIO_J_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_J_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G1R_SHIFT)
#define GPIO_J_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G0R_SHIFT)
#define GPIO_J_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_J_VM_04_0
#define GPIO_J_VM_04_0                  MK_ADDR_CONST(0x5020)
#define GPIO_J_VM_04_0_SECURE                   0x0
#define GPIO_J_VM_04_0_DUAL                     0x0
#define GPIO_J_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_04_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_04_0_WORD_COUNT                       0x1
#define GPIO_J_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM1_SHIFT)
#define GPIO_J_VM_04_0_VM1_RANGE                        1:0
#define GPIO_J_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_J_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_J_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM2_SHIFT)
#define GPIO_J_VM_04_0_VM2_RANGE                        3:2
#define GPIO_J_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_J_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_J_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_J_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM3_SHIFT)
#define GPIO_J_VM_04_0_VM3_RANGE                        5:4
#define GPIO_J_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_J_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_J_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM4_SHIFT)
#define GPIO_J_VM_04_0_VM4_RANGE                        7:6
#define GPIO_J_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_J_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_J_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_J_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM5_SHIFT)
#define GPIO_J_VM_04_0_VM5_RANGE                        9:8
#define GPIO_J_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_J_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_J_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_J_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM6_SHIFT)
#define GPIO_J_VM_04_0_VM6_RANGE                        11:10
#define GPIO_J_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_J_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_J_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_J_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM7_SHIFT)
#define GPIO_J_VM_04_0_VM7_RANGE                        13:12
#define GPIO_J_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_J_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_J_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_J_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM8_SHIFT)
#define GPIO_J_VM_04_0_VM8_RANGE                        15:14
#define GPIO_J_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_J_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_J_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_04_0
#define GPIO_J_SCR_04_0                 MK_ADDR_CONST(0x5024)
#define GPIO_J_SCR_04_0_SECURE                  0x0
#define GPIO_J_SCR_04_0_DUAL                    0x0
#define GPIO_J_SCR_04_0_SCR                     0
#define GPIO_J_SCR_04_0_SCRREG                  0
#define GPIO_J_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_J_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_J_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_J_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_J_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_J_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_J_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_J_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_J_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR7_SHIFT)
#define GPIO_J_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_J_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR6_SHIFT)
#define GPIO_J_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_J_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR5_SHIFT)
#define GPIO_J_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_J_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR4_SHIFT)
#define GPIO_J_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_J_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR3_SHIFT)
#define GPIO_J_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_J_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR2_SHIFT)
#define GPIO_J_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_J_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR1_SHIFT)
#define GPIO_J_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_J_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR0_SHIFT)
#define GPIO_J_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_J_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G7W_SHIFT)
#define GPIO_J_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_J_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G6W_SHIFT)
#define GPIO_J_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_J_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G5W_SHIFT)
#define GPIO_J_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_J_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G4W_SHIFT)
#define GPIO_J_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_J_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G3W_SHIFT)
#define GPIO_J_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_J_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G2W_SHIFT)
#define GPIO_J_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_J_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G1W_SHIFT)
#define GPIO_J_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_J_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G0W_SHIFT)
#define GPIO_J_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_J_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G7R_SHIFT)
#define GPIO_J_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_J_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G6R_SHIFT)
#define GPIO_J_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G5R_SHIFT)
#define GPIO_J_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_J_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G4R_SHIFT)
#define GPIO_J_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_J_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G3R_SHIFT)
#define GPIO_J_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_J_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G2R_SHIFT)
#define GPIO_J_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_J_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G1R_SHIFT)
#define GPIO_J_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G0R_SHIFT)
#define GPIO_J_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_J_VM_05_0
#define GPIO_J_VM_05_0                  MK_ADDR_CONST(0x5028)
#define GPIO_J_VM_05_0_SECURE                   0x0
#define GPIO_J_VM_05_0_DUAL                     0x0
#define GPIO_J_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_05_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_J_VM_05_0_WORD_COUNT                       0x1
#define GPIO_J_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_J_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM1_SHIFT)
#define GPIO_J_VM_05_0_VM1_RANGE                        1:0
#define GPIO_J_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_J_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_J_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM2_SHIFT)
#define GPIO_J_VM_05_0_VM2_RANGE                        3:2
#define GPIO_J_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_J_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_J_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_J_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM3_SHIFT)
#define GPIO_J_VM_05_0_VM3_RANGE                        5:4
#define GPIO_J_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_J_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_J_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM4_SHIFT)
#define GPIO_J_VM_05_0_VM4_RANGE                        7:6
#define GPIO_J_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_J_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_J_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_J_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM5_SHIFT)
#define GPIO_J_VM_05_0_VM5_RANGE                        9:8
#define GPIO_J_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_J_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_J_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_J_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM6_SHIFT)
#define GPIO_J_VM_05_0_VM6_RANGE                        11:10
#define GPIO_J_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_J_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_J_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_J_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM7_SHIFT)
#define GPIO_J_VM_05_0_VM7_RANGE                        13:12
#define GPIO_J_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_J_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_J_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_J_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_J_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM8_SHIFT)
#define GPIO_J_VM_05_0_VM8_RANGE                        15:14
#define GPIO_J_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_J_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_J_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_J_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_J_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_SCR_05_0
#define GPIO_J_SCR_05_0                 MK_ADDR_CONST(0x502c)
#define GPIO_J_SCR_05_0_SECURE                  0x0
#define GPIO_J_SCR_05_0_DUAL                    0x0
#define GPIO_J_SCR_05_0_SCR                     0
#define GPIO_J_SCR_05_0_SCRREG                  0
#define GPIO_J_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_J_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_J_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_J_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_J_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_J_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_J_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_J_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_J_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_J_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_J_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_J_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_J_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_J_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_J_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_J_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_J_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_J_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_J_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_J_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_J_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_J_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_J_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_J_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR7_SHIFT)
#define GPIO_J_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_J_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_J_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_J_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR6_SHIFT)
#define GPIO_J_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_J_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_J_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_J_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR5_SHIFT)
#define GPIO_J_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_J_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_J_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_J_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR4_SHIFT)
#define GPIO_J_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_J_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_J_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_J_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR3_SHIFT)
#define GPIO_J_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_J_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_J_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_J_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR2_SHIFT)
#define GPIO_J_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_J_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_J_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_J_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR1_SHIFT)
#define GPIO_J_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_J_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_J_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_J_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR0_SHIFT)
#define GPIO_J_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_J_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_J_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_J_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G7W_SHIFT)
#define GPIO_J_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_J_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_J_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_J_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G6W_SHIFT)
#define GPIO_J_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_J_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_J_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_J_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G5W_SHIFT)
#define GPIO_J_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_J_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_J_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_J_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G4W_SHIFT)
#define GPIO_J_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_J_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_J_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_J_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G3W_SHIFT)
#define GPIO_J_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_J_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_J_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_J_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G2W_SHIFT)
#define GPIO_J_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_J_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_J_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_J_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G1W_SHIFT)
#define GPIO_J_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_J_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_J_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_J_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G0W_SHIFT)
#define GPIO_J_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_J_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_J_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_J_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G7R_SHIFT)
#define GPIO_J_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_J_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_J_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_J_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G6R_SHIFT)
#define GPIO_J_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_J_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_J_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G5R_SHIFT)
#define GPIO_J_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_J_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_J_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G4R_SHIFT)
#define GPIO_J_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_J_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_J_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_J_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G3R_SHIFT)
#define GPIO_J_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_J_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_J_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_J_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G2R_SHIFT)
#define GPIO_J_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_J_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_J_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_J_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G1R_SHIFT)
#define GPIO_J_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_J_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_J_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_J_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G0R_SHIFT)
#define GPIO_J_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_J_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_J_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_J_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x5030

// Reserved address 0x5034

// Reserved address 0x5038

// Reserved address 0x503c

// Register GPIO_C_VM_00_0
#define GPIO_C_VM_00_0                  MK_ADDR_CONST(0x5040)
#define GPIO_C_VM_00_0_SECURE                   0x0
#define GPIO_C_VM_00_0_DUAL                     0x0
#define GPIO_C_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_00_0_WORD_COUNT                       0x1
#define GPIO_C_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM1_SHIFT)
#define GPIO_C_VM_00_0_VM1_RANGE                        1:0
#define GPIO_C_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_C_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_C_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM2_SHIFT)
#define GPIO_C_VM_00_0_VM2_RANGE                        3:2
#define GPIO_C_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_C_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_C_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_C_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM3_SHIFT)
#define GPIO_C_VM_00_0_VM3_RANGE                        5:4
#define GPIO_C_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_C_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_C_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_C_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM4_SHIFT)
#define GPIO_C_VM_00_0_VM4_RANGE                        7:6
#define GPIO_C_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_C_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_C_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM5_SHIFT)
#define GPIO_C_VM_00_0_VM5_RANGE                        9:8
#define GPIO_C_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_C_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_C_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_C_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM6_SHIFT)
#define GPIO_C_VM_00_0_VM6_RANGE                        11:10
#define GPIO_C_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_C_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_C_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_C_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM7_SHIFT)
#define GPIO_C_VM_00_0_VM7_RANGE                        13:12
#define GPIO_C_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_C_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_C_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_C_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM8_SHIFT)
#define GPIO_C_VM_00_0_VM8_RANGE                        15:14
#define GPIO_C_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_C_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_C_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_00_0
#define GPIO_C_SCR_00_0                 MK_ADDR_CONST(0x5044)
#define GPIO_C_SCR_00_0_SECURE                  0x0
#define GPIO_C_SCR_00_0_DUAL                    0x0
#define GPIO_C_SCR_00_0_SCR                     0
#define GPIO_C_SCR_00_0_SCRREG                  0
#define GPIO_C_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_C_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_C_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_C_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_C_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_C_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_C_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_C_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_C_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR7_SHIFT)
#define GPIO_C_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_C_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR6_SHIFT)
#define GPIO_C_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_C_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR5_SHIFT)
#define GPIO_C_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_C_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR4_SHIFT)
#define GPIO_C_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_C_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR3_SHIFT)
#define GPIO_C_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_C_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR2_SHIFT)
#define GPIO_C_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_C_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR1_SHIFT)
#define GPIO_C_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_C_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR0_SHIFT)
#define GPIO_C_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_C_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G7W_SHIFT)
#define GPIO_C_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_C_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G6W_SHIFT)
#define GPIO_C_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_C_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G5W_SHIFT)
#define GPIO_C_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_C_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G4W_SHIFT)
#define GPIO_C_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_C_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G3W_SHIFT)
#define GPIO_C_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_C_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G2W_SHIFT)
#define GPIO_C_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_C_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G1W_SHIFT)
#define GPIO_C_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_C_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G0W_SHIFT)
#define GPIO_C_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_C_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G7R_SHIFT)
#define GPIO_C_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_C_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G6R_SHIFT)
#define GPIO_C_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G5R_SHIFT)
#define GPIO_C_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_C_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G4R_SHIFT)
#define GPIO_C_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_C_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G3R_SHIFT)
#define GPIO_C_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_C_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G2R_SHIFT)
#define GPIO_C_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_C_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G1R_SHIFT)
#define GPIO_C_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G0R_SHIFT)
#define GPIO_C_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_C_VM_01_0
#define GPIO_C_VM_01_0                  MK_ADDR_CONST(0x5048)
#define GPIO_C_VM_01_0_SECURE                   0x0
#define GPIO_C_VM_01_0_DUAL                     0x0
#define GPIO_C_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_01_0_WORD_COUNT                       0x1
#define GPIO_C_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM1_SHIFT)
#define GPIO_C_VM_01_0_VM1_RANGE                        1:0
#define GPIO_C_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_C_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_C_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM2_SHIFT)
#define GPIO_C_VM_01_0_VM2_RANGE                        3:2
#define GPIO_C_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_C_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_C_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_C_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM3_SHIFT)
#define GPIO_C_VM_01_0_VM3_RANGE                        5:4
#define GPIO_C_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_C_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_C_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_C_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM4_SHIFT)
#define GPIO_C_VM_01_0_VM4_RANGE                        7:6
#define GPIO_C_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_C_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_C_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM5_SHIFT)
#define GPIO_C_VM_01_0_VM5_RANGE                        9:8
#define GPIO_C_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_C_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_C_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_C_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM6_SHIFT)
#define GPIO_C_VM_01_0_VM6_RANGE                        11:10
#define GPIO_C_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_C_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_C_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_C_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM7_SHIFT)
#define GPIO_C_VM_01_0_VM7_RANGE                        13:12
#define GPIO_C_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_C_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_C_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_C_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM8_SHIFT)
#define GPIO_C_VM_01_0_VM8_RANGE                        15:14
#define GPIO_C_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_C_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_C_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_01_0
#define GPIO_C_SCR_01_0                 MK_ADDR_CONST(0x504c)
#define GPIO_C_SCR_01_0_SECURE                  0x0
#define GPIO_C_SCR_01_0_DUAL                    0x0
#define GPIO_C_SCR_01_0_SCR                     0
#define GPIO_C_SCR_01_0_SCRREG                  0
#define GPIO_C_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_C_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_C_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_C_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_C_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_C_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_C_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_C_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_C_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR7_SHIFT)
#define GPIO_C_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_C_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR6_SHIFT)
#define GPIO_C_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_C_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR5_SHIFT)
#define GPIO_C_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_C_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR4_SHIFT)
#define GPIO_C_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_C_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR3_SHIFT)
#define GPIO_C_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_C_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR2_SHIFT)
#define GPIO_C_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_C_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR1_SHIFT)
#define GPIO_C_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_C_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR0_SHIFT)
#define GPIO_C_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_C_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G7W_SHIFT)
#define GPIO_C_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_C_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G6W_SHIFT)
#define GPIO_C_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_C_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G5W_SHIFT)
#define GPIO_C_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_C_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G4W_SHIFT)
#define GPIO_C_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_C_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G3W_SHIFT)
#define GPIO_C_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_C_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G2W_SHIFT)
#define GPIO_C_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_C_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G1W_SHIFT)
#define GPIO_C_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_C_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G0W_SHIFT)
#define GPIO_C_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_C_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G7R_SHIFT)
#define GPIO_C_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_C_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G6R_SHIFT)
#define GPIO_C_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G5R_SHIFT)
#define GPIO_C_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_C_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G4R_SHIFT)
#define GPIO_C_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_C_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G3R_SHIFT)
#define GPIO_C_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_C_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G2R_SHIFT)
#define GPIO_C_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_C_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G1R_SHIFT)
#define GPIO_C_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G0R_SHIFT)
#define GPIO_C_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_C_VM_02_0
#define GPIO_C_VM_02_0                  MK_ADDR_CONST(0x5050)
#define GPIO_C_VM_02_0_SECURE                   0x0
#define GPIO_C_VM_02_0_DUAL                     0x0
#define GPIO_C_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_02_0_WORD_COUNT                       0x1
#define GPIO_C_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM1_SHIFT)
#define GPIO_C_VM_02_0_VM1_RANGE                        1:0
#define GPIO_C_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_C_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_C_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM2_SHIFT)
#define GPIO_C_VM_02_0_VM2_RANGE                        3:2
#define GPIO_C_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_C_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_C_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_C_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM3_SHIFT)
#define GPIO_C_VM_02_0_VM3_RANGE                        5:4
#define GPIO_C_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_C_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_C_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_C_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM4_SHIFT)
#define GPIO_C_VM_02_0_VM4_RANGE                        7:6
#define GPIO_C_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_C_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_C_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM5_SHIFT)
#define GPIO_C_VM_02_0_VM5_RANGE                        9:8
#define GPIO_C_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_C_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_C_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_C_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM6_SHIFT)
#define GPIO_C_VM_02_0_VM6_RANGE                        11:10
#define GPIO_C_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_C_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_C_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_C_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM7_SHIFT)
#define GPIO_C_VM_02_0_VM7_RANGE                        13:12
#define GPIO_C_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_C_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_C_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_C_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM8_SHIFT)
#define GPIO_C_VM_02_0_VM8_RANGE                        15:14
#define GPIO_C_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_C_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_C_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_02_0
#define GPIO_C_SCR_02_0                 MK_ADDR_CONST(0x5054)
#define GPIO_C_SCR_02_0_SECURE                  0x0
#define GPIO_C_SCR_02_0_DUAL                    0x0
#define GPIO_C_SCR_02_0_SCR                     0
#define GPIO_C_SCR_02_0_SCRREG                  0
#define GPIO_C_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_C_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_C_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_C_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_C_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_C_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_C_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_C_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_C_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR7_SHIFT)
#define GPIO_C_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_C_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR6_SHIFT)
#define GPIO_C_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_C_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR5_SHIFT)
#define GPIO_C_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_C_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR4_SHIFT)
#define GPIO_C_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_C_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR3_SHIFT)
#define GPIO_C_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_C_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR2_SHIFT)
#define GPIO_C_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_C_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR1_SHIFT)
#define GPIO_C_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_C_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR0_SHIFT)
#define GPIO_C_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_C_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G7W_SHIFT)
#define GPIO_C_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_C_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G6W_SHIFT)
#define GPIO_C_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_C_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G5W_SHIFT)
#define GPIO_C_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_C_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G4W_SHIFT)
#define GPIO_C_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_C_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G3W_SHIFT)
#define GPIO_C_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_C_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G2W_SHIFT)
#define GPIO_C_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_C_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G1W_SHIFT)
#define GPIO_C_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_C_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G0W_SHIFT)
#define GPIO_C_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_C_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G7R_SHIFT)
#define GPIO_C_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_C_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G6R_SHIFT)
#define GPIO_C_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G5R_SHIFT)
#define GPIO_C_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_C_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G4R_SHIFT)
#define GPIO_C_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_C_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G3R_SHIFT)
#define GPIO_C_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_C_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G2R_SHIFT)
#define GPIO_C_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_C_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G1R_SHIFT)
#define GPIO_C_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G0R_SHIFT)
#define GPIO_C_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_C_VM_03_0
#define GPIO_C_VM_03_0                  MK_ADDR_CONST(0x5058)
#define GPIO_C_VM_03_0_SECURE                   0x0
#define GPIO_C_VM_03_0_DUAL                     0x0
#define GPIO_C_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_03_0_WORD_COUNT                       0x1
#define GPIO_C_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM1_SHIFT)
#define GPIO_C_VM_03_0_VM1_RANGE                        1:0
#define GPIO_C_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_C_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_C_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM2_SHIFT)
#define GPIO_C_VM_03_0_VM2_RANGE                        3:2
#define GPIO_C_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_C_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_C_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_C_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM3_SHIFT)
#define GPIO_C_VM_03_0_VM3_RANGE                        5:4
#define GPIO_C_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_C_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_C_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_C_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM4_SHIFT)
#define GPIO_C_VM_03_0_VM4_RANGE                        7:6
#define GPIO_C_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_C_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_C_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM5_SHIFT)
#define GPIO_C_VM_03_0_VM5_RANGE                        9:8
#define GPIO_C_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_C_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_C_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_C_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM6_SHIFT)
#define GPIO_C_VM_03_0_VM6_RANGE                        11:10
#define GPIO_C_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_C_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_C_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_C_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM7_SHIFT)
#define GPIO_C_VM_03_0_VM7_RANGE                        13:12
#define GPIO_C_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_C_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_C_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_C_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM8_SHIFT)
#define GPIO_C_VM_03_0_VM8_RANGE                        15:14
#define GPIO_C_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_C_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_C_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_03_0
#define GPIO_C_SCR_03_0                 MK_ADDR_CONST(0x505c)
#define GPIO_C_SCR_03_0_SECURE                  0x0
#define GPIO_C_SCR_03_0_DUAL                    0x0
#define GPIO_C_SCR_03_0_SCR                     0
#define GPIO_C_SCR_03_0_SCRREG                  0
#define GPIO_C_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_C_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_C_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_C_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_C_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_C_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_C_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_C_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_C_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR7_SHIFT)
#define GPIO_C_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_C_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR6_SHIFT)
#define GPIO_C_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_C_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR5_SHIFT)
#define GPIO_C_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_C_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR4_SHIFT)
#define GPIO_C_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_C_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR3_SHIFT)
#define GPIO_C_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_C_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR2_SHIFT)
#define GPIO_C_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_C_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR1_SHIFT)
#define GPIO_C_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_C_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR0_SHIFT)
#define GPIO_C_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_C_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G7W_SHIFT)
#define GPIO_C_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_C_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G6W_SHIFT)
#define GPIO_C_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_C_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G5W_SHIFT)
#define GPIO_C_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_C_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G4W_SHIFT)
#define GPIO_C_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_C_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G3W_SHIFT)
#define GPIO_C_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_C_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G2W_SHIFT)
#define GPIO_C_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_C_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G1W_SHIFT)
#define GPIO_C_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_C_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G0W_SHIFT)
#define GPIO_C_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_C_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G7R_SHIFT)
#define GPIO_C_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_C_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G6R_SHIFT)
#define GPIO_C_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G5R_SHIFT)
#define GPIO_C_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_C_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G4R_SHIFT)
#define GPIO_C_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_C_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G3R_SHIFT)
#define GPIO_C_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_C_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G2R_SHIFT)
#define GPIO_C_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_C_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G1R_SHIFT)
#define GPIO_C_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G0R_SHIFT)
#define GPIO_C_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_C_VM_04_0
#define GPIO_C_VM_04_0                  MK_ADDR_CONST(0x5060)
#define GPIO_C_VM_04_0_SECURE                   0x0
#define GPIO_C_VM_04_0_DUAL                     0x0
#define GPIO_C_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_04_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_04_0_WORD_COUNT                       0x1
#define GPIO_C_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM1_SHIFT)
#define GPIO_C_VM_04_0_VM1_RANGE                        1:0
#define GPIO_C_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_C_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_C_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM2_SHIFT)
#define GPIO_C_VM_04_0_VM2_RANGE                        3:2
#define GPIO_C_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_C_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_C_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_C_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM3_SHIFT)
#define GPIO_C_VM_04_0_VM3_RANGE                        5:4
#define GPIO_C_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_C_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_C_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_C_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM4_SHIFT)
#define GPIO_C_VM_04_0_VM4_RANGE                        7:6
#define GPIO_C_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_C_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_C_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM5_SHIFT)
#define GPIO_C_VM_04_0_VM5_RANGE                        9:8
#define GPIO_C_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_C_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_C_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_C_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM6_SHIFT)
#define GPIO_C_VM_04_0_VM6_RANGE                        11:10
#define GPIO_C_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_C_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_C_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_C_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM7_SHIFT)
#define GPIO_C_VM_04_0_VM7_RANGE                        13:12
#define GPIO_C_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_C_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_C_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_C_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM8_SHIFT)
#define GPIO_C_VM_04_0_VM8_RANGE                        15:14
#define GPIO_C_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_C_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_C_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_04_0
#define GPIO_C_SCR_04_0                 MK_ADDR_CONST(0x5064)
#define GPIO_C_SCR_04_0_SECURE                  0x0
#define GPIO_C_SCR_04_0_DUAL                    0x0
#define GPIO_C_SCR_04_0_SCR                     0
#define GPIO_C_SCR_04_0_SCRREG                  0
#define GPIO_C_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_C_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_C_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_C_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_C_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_C_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_C_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_C_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_C_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR7_SHIFT)
#define GPIO_C_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_C_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR6_SHIFT)
#define GPIO_C_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_C_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR5_SHIFT)
#define GPIO_C_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_C_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR4_SHIFT)
#define GPIO_C_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_C_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR3_SHIFT)
#define GPIO_C_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_C_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR2_SHIFT)
#define GPIO_C_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_C_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR1_SHIFT)
#define GPIO_C_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_C_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR0_SHIFT)
#define GPIO_C_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_C_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G7W_SHIFT)
#define GPIO_C_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_C_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G6W_SHIFT)
#define GPIO_C_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_C_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G5W_SHIFT)
#define GPIO_C_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_C_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G4W_SHIFT)
#define GPIO_C_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_C_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G3W_SHIFT)
#define GPIO_C_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_C_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G2W_SHIFT)
#define GPIO_C_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_C_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G1W_SHIFT)
#define GPIO_C_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_C_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G0W_SHIFT)
#define GPIO_C_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_C_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G7R_SHIFT)
#define GPIO_C_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_C_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G6R_SHIFT)
#define GPIO_C_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G5R_SHIFT)
#define GPIO_C_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_C_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G4R_SHIFT)
#define GPIO_C_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_C_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G3R_SHIFT)
#define GPIO_C_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_C_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G2R_SHIFT)
#define GPIO_C_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_C_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G1R_SHIFT)
#define GPIO_C_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G0R_SHIFT)
#define GPIO_C_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_C_VM_05_0
#define GPIO_C_VM_05_0                  MK_ADDR_CONST(0x5068)
#define GPIO_C_VM_05_0_SECURE                   0x0
#define GPIO_C_VM_05_0_DUAL                     0x0
#define GPIO_C_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_05_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_05_0_WORD_COUNT                       0x1
#define GPIO_C_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM1_SHIFT)
#define GPIO_C_VM_05_0_VM1_RANGE                        1:0
#define GPIO_C_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_C_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_C_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM2_SHIFT)
#define GPIO_C_VM_05_0_VM2_RANGE                        3:2
#define GPIO_C_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_C_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_C_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_C_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM3_SHIFT)
#define GPIO_C_VM_05_0_VM3_RANGE                        5:4
#define GPIO_C_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_C_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_C_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_C_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM4_SHIFT)
#define GPIO_C_VM_05_0_VM4_RANGE                        7:6
#define GPIO_C_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_C_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_C_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM5_SHIFT)
#define GPIO_C_VM_05_0_VM5_RANGE                        9:8
#define GPIO_C_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_C_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_C_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_C_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM6_SHIFT)
#define GPIO_C_VM_05_0_VM6_RANGE                        11:10
#define GPIO_C_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_C_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_C_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_C_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM7_SHIFT)
#define GPIO_C_VM_05_0_VM7_RANGE                        13:12
#define GPIO_C_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_C_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_C_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_C_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM8_SHIFT)
#define GPIO_C_VM_05_0_VM8_RANGE                        15:14
#define GPIO_C_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_C_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_C_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_05_0
#define GPIO_C_SCR_05_0                 MK_ADDR_CONST(0x506c)
#define GPIO_C_SCR_05_0_SECURE                  0x0
#define GPIO_C_SCR_05_0_DUAL                    0x0
#define GPIO_C_SCR_05_0_SCR                     0
#define GPIO_C_SCR_05_0_SCRREG                  0
#define GPIO_C_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_C_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_C_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_C_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_C_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_C_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_C_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_C_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_C_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR7_SHIFT)
#define GPIO_C_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_C_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR6_SHIFT)
#define GPIO_C_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_C_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR5_SHIFT)
#define GPIO_C_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_C_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR4_SHIFT)
#define GPIO_C_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_C_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR3_SHIFT)
#define GPIO_C_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_C_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR2_SHIFT)
#define GPIO_C_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_C_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR1_SHIFT)
#define GPIO_C_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_C_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR0_SHIFT)
#define GPIO_C_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_C_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G7W_SHIFT)
#define GPIO_C_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_C_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G6W_SHIFT)
#define GPIO_C_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_C_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G5W_SHIFT)
#define GPIO_C_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_C_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G4W_SHIFT)
#define GPIO_C_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_C_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G3W_SHIFT)
#define GPIO_C_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_C_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G2W_SHIFT)
#define GPIO_C_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_C_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G1W_SHIFT)
#define GPIO_C_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_C_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G0W_SHIFT)
#define GPIO_C_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_C_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G7R_SHIFT)
#define GPIO_C_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_C_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G6R_SHIFT)
#define GPIO_C_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G5R_SHIFT)
#define GPIO_C_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_C_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G4R_SHIFT)
#define GPIO_C_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_C_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G3R_SHIFT)
#define GPIO_C_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_C_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G2R_SHIFT)
#define GPIO_C_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_C_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G1R_SHIFT)
#define GPIO_C_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G0R_SHIFT)
#define GPIO_C_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_C_VM_06_0
#define GPIO_C_VM_06_0                  MK_ADDR_CONST(0x5070)
#define GPIO_C_VM_06_0_SECURE                   0x0
#define GPIO_C_VM_06_0_DUAL                     0x0
#define GPIO_C_VM_06_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_06_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_06_0_WORD_COUNT                       0x1
#define GPIO_C_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM1_SHIFT)
#define GPIO_C_VM_06_0_VM1_RANGE                        1:0
#define GPIO_C_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_C_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_C_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM2_SHIFT)
#define GPIO_C_VM_06_0_VM2_RANGE                        3:2
#define GPIO_C_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_C_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_C_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_C_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM3_SHIFT)
#define GPIO_C_VM_06_0_VM3_RANGE                        5:4
#define GPIO_C_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_C_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_C_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_C_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM4_SHIFT)
#define GPIO_C_VM_06_0_VM4_RANGE                        7:6
#define GPIO_C_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_C_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_C_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM5_SHIFT)
#define GPIO_C_VM_06_0_VM5_RANGE                        9:8
#define GPIO_C_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_C_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_C_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_C_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM6_SHIFT)
#define GPIO_C_VM_06_0_VM6_RANGE                        11:10
#define GPIO_C_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_C_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_C_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_C_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM7_SHIFT)
#define GPIO_C_VM_06_0_VM7_RANGE                        13:12
#define GPIO_C_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_C_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_C_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_C_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM8_SHIFT)
#define GPIO_C_VM_06_0_VM8_RANGE                        15:14
#define GPIO_C_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_C_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_C_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_06_0
#define GPIO_C_SCR_06_0                 MK_ADDR_CONST(0x5074)
#define GPIO_C_SCR_06_0_SECURE                  0x0
#define GPIO_C_SCR_06_0_DUAL                    0x0
#define GPIO_C_SCR_06_0_SCR                     0
#define GPIO_C_SCR_06_0_SCRREG                  0
#define GPIO_C_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_C_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_C_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_C_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_C_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_C_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_C_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_C_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_C_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR7_SHIFT)
#define GPIO_C_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_C_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR6_SHIFT)
#define GPIO_C_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_C_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR5_SHIFT)
#define GPIO_C_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_C_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR4_SHIFT)
#define GPIO_C_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_C_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR3_SHIFT)
#define GPIO_C_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_C_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR2_SHIFT)
#define GPIO_C_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_C_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR1_SHIFT)
#define GPIO_C_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_C_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR0_SHIFT)
#define GPIO_C_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_C_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G7W_SHIFT)
#define GPIO_C_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_C_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G6W_SHIFT)
#define GPIO_C_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_C_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G5W_SHIFT)
#define GPIO_C_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_C_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G4W_SHIFT)
#define GPIO_C_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_C_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G3W_SHIFT)
#define GPIO_C_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_C_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G2W_SHIFT)
#define GPIO_C_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_C_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G1W_SHIFT)
#define GPIO_C_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_C_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G0W_SHIFT)
#define GPIO_C_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_C_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G7R_SHIFT)
#define GPIO_C_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_C_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G6R_SHIFT)
#define GPIO_C_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G5R_SHIFT)
#define GPIO_C_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_C_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G4R_SHIFT)
#define GPIO_C_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_C_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G3R_SHIFT)
#define GPIO_C_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_C_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G2R_SHIFT)
#define GPIO_C_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_C_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G1R_SHIFT)
#define GPIO_C_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G0R_SHIFT)
#define GPIO_C_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_C_VM_07_0
#define GPIO_C_VM_07_0                  MK_ADDR_CONST(0x5078)
#define GPIO_C_VM_07_0_SECURE                   0x0
#define GPIO_C_VM_07_0_DUAL                     0x0
#define GPIO_C_VM_07_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_07_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_C_VM_07_0_WORD_COUNT                       0x1
#define GPIO_C_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_C_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_C_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM1_SHIFT)
#define GPIO_C_VM_07_0_VM1_RANGE                        1:0
#define GPIO_C_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_C_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_C_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM2_SHIFT)
#define GPIO_C_VM_07_0_VM2_RANGE                        3:2
#define GPIO_C_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_C_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_C_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_C_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM3_SHIFT)
#define GPIO_C_VM_07_0_VM3_RANGE                        5:4
#define GPIO_C_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_C_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_C_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_C_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM4_SHIFT)
#define GPIO_C_VM_07_0_VM4_RANGE                        7:6
#define GPIO_C_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_C_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_C_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM5_SHIFT)
#define GPIO_C_VM_07_0_VM5_RANGE                        9:8
#define GPIO_C_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_C_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_C_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_C_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM6_SHIFT)
#define GPIO_C_VM_07_0_VM6_RANGE                        11:10
#define GPIO_C_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_C_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_C_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_C_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM7_SHIFT)
#define GPIO_C_VM_07_0_VM7_RANGE                        13:12
#define GPIO_C_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_C_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_C_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_C_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_C_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM8_SHIFT)
#define GPIO_C_VM_07_0_VM8_RANGE                        15:14
#define GPIO_C_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_C_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_C_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_C_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_C_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_SCR_07_0
#define GPIO_C_SCR_07_0                 MK_ADDR_CONST(0x507c)
#define GPIO_C_SCR_07_0_SECURE                  0x0
#define GPIO_C_SCR_07_0_DUAL                    0x0
#define GPIO_C_SCR_07_0_SCR                     0
#define GPIO_C_SCR_07_0_SCRREG                  0
#define GPIO_C_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_C_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_C_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_C_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_C_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_C_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_C_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_C_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_C_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_C_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_C_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_C_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_C_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_C_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_C_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_C_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_C_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_C_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_C_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_C_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_C_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_C_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_C_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_C_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_C_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_C_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR7_SHIFT)
#define GPIO_C_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_C_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_C_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_C_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR6_SHIFT)
#define GPIO_C_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_C_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_C_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_C_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR5_SHIFT)
#define GPIO_C_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_C_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_C_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_C_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR4_SHIFT)
#define GPIO_C_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_C_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_C_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_C_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR3_SHIFT)
#define GPIO_C_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_C_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_C_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_C_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR2_SHIFT)
#define GPIO_C_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_C_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_C_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_C_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR1_SHIFT)
#define GPIO_C_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_C_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_C_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_C_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR0_SHIFT)
#define GPIO_C_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_C_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_C_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_C_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G7W_SHIFT)
#define GPIO_C_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_C_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_C_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_C_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G6W_SHIFT)
#define GPIO_C_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_C_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_C_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_C_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G5W_SHIFT)
#define GPIO_C_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_C_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_C_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_C_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G4W_SHIFT)
#define GPIO_C_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_C_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_C_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_C_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G3W_SHIFT)
#define GPIO_C_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_C_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_C_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_C_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G2W_SHIFT)
#define GPIO_C_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_C_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_C_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_C_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G1W_SHIFT)
#define GPIO_C_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_C_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_C_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_C_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G0W_SHIFT)
#define GPIO_C_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_C_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_C_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_C_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G7R_SHIFT)
#define GPIO_C_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_C_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_C_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_C_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G6R_SHIFT)
#define GPIO_C_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_C_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_C_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G5R_SHIFT)
#define GPIO_C_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_C_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_C_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G4R_SHIFT)
#define GPIO_C_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_C_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_C_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_C_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G3R_SHIFT)
#define GPIO_C_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_C_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_C_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_C_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G2R_SHIFT)
#define GPIO_C_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_C_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_C_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_C_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G1R_SHIFT)
#define GPIO_C_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_C_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_C_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_C_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G0R_SHIFT)
#define GPIO_C_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_C_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_C_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_C_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_D_VM_00_0
#define GPIO_D_VM_00_0                  MK_ADDR_CONST(0x5080)
#define GPIO_D_VM_00_0_SECURE                   0x0
#define GPIO_D_VM_00_0_DUAL                     0x0
#define GPIO_D_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_D_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_D_VM_00_0_WORD_COUNT                       0x1
#define GPIO_D_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_D_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM1_SHIFT)
#define GPIO_D_VM_00_0_VM1_RANGE                        1:0
#define GPIO_D_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_D_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_D_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM2_SHIFT)
#define GPIO_D_VM_00_0_VM2_RANGE                        3:2
#define GPIO_D_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_D_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_D_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM3_SHIFT)
#define GPIO_D_VM_00_0_VM3_RANGE                        5:4
#define GPIO_D_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_D_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_D_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_D_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM4_SHIFT)
#define GPIO_D_VM_00_0_VM4_RANGE                        7:6
#define GPIO_D_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_D_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_D_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_D_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM5_SHIFT)
#define GPIO_D_VM_00_0_VM5_RANGE                        9:8
#define GPIO_D_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_D_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_D_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_D_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM6_SHIFT)
#define GPIO_D_VM_00_0_VM6_RANGE                        11:10
#define GPIO_D_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_D_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_D_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_D_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM7_SHIFT)
#define GPIO_D_VM_00_0_VM7_RANGE                        13:12
#define GPIO_D_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_D_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_D_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_D_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM8_SHIFT)
#define GPIO_D_VM_00_0_VM8_RANGE                        15:14
#define GPIO_D_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_D_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_D_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_SCR_00_0
#define GPIO_D_SCR_00_0                 MK_ADDR_CONST(0x5084)
#define GPIO_D_SCR_00_0_SECURE                  0x0
#define GPIO_D_SCR_00_0_DUAL                    0x0
#define GPIO_D_SCR_00_0_SCR                     0
#define GPIO_D_SCR_00_0_SCRREG                  0
#define GPIO_D_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_D_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_D_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_D_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_D_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_D_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_D_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_D_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_D_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_D_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_D_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_D_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_D_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_D_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_D_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_D_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR7_SHIFT)
#define GPIO_D_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_D_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_D_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_D_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR6_SHIFT)
#define GPIO_D_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_D_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_D_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_D_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR5_SHIFT)
#define GPIO_D_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_D_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_D_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_D_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR4_SHIFT)
#define GPIO_D_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_D_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_D_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_D_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR3_SHIFT)
#define GPIO_D_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_D_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_D_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_D_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR2_SHIFT)
#define GPIO_D_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_D_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_D_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_D_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR1_SHIFT)
#define GPIO_D_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_D_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_D_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_D_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR0_SHIFT)
#define GPIO_D_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_D_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_D_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_D_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G7W_SHIFT)
#define GPIO_D_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_D_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_D_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_D_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G6W_SHIFT)
#define GPIO_D_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_D_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_D_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_D_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G5W_SHIFT)
#define GPIO_D_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_D_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_D_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_D_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G4W_SHIFT)
#define GPIO_D_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_D_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_D_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_D_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G3W_SHIFT)
#define GPIO_D_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_D_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_D_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_D_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G2W_SHIFT)
#define GPIO_D_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_D_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_D_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_D_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G1W_SHIFT)
#define GPIO_D_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_D_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_D_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_D_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G0W_SHIFT)
#define GPIO_D_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_D_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_D_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_D_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G7R_SHIFT)
#define GPIO_D_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_D_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_D_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_D_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G6R_SHIFT)
#define GPIO_D_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_D_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_D_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_D_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G5R_SHIFT)
#define GPIO_D_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_D_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_D_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_D_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G4R_SHIFT)
#define GPIO_D_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_D_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_D_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_D_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G3R_SHIFT)
#define GPIO_D_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_D_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_D_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_D_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G2R_SHIFT)
#define GPIO_D_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_D_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_D_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_D_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G1R_SHIFT)
#define GPIO_D_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_D_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_D_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_D_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G0R_SHIFT)
#define GPIO_D_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_D_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_D_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_D_VM_01_0
#define GPIO_D_VM_01_0                  MK_ADDR_CONST(0x5088)
#define GPIO_D_VM_01_0_SECURE                   0x0
#define GPIO_D_VM_01_0_DUAL                     0x0
#define GPIO_D_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_D_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_D_VM_01_0_WORD_COUNT                       0x1
#define GPIO_D_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_D_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM1_SHIFT)
#define GPIO_D_VM_01_0_VM1_RANGE                        1:0
#define GPIO_D_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_D_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_D_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM2_SHIFT)
#define GPIO_D_VM_01_0_VM2_RANGE                        3:2
#define GPIO_D_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_D_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_D_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM3_SHIFT)
#define GPIO_D_VM_01_0_VM3_RANGE                        5:4
#define GPIO_D_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_D_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_D_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_D_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM4_SHIFT)
#define GPIO_D_VM_01_0_VM4_RANGE                        7:6
#define GPIO_D_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_D_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_D_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_D_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM5_SHIFT)
#define GPIO_D_VM_01_0_VM5_RANGE                        9:8
#define GPIO_D_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_D_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_D_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_D_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM6_SHIFT)
#define GPIO_D_VM_01_0_VM6_RANGE                        11:10
#define GPIO_D_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_D_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_D_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_D_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM7_SHIFT)
#define GPIO_D_VM_01_0_VM7_RANGE                        13:12
#define GPIO_D_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_D_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_D_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_D_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM8_SHIFT)
#define GPIO_D_VM_01_0_VM8_RANGE                        15:14
#define GPIO_D_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_D_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_D_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_SCR_01_0
#define GPIO_D_SCR_01_0                 MK_ADDR_CONST(0x508c)
#define GPIO_D_SCR_01_0_SECURE                  0x0
#define GPIO_D_SCR_01_0_DUAL                    0x0
#define GPIO_D_SCR_01_0_SCR                     0
#define GPIO_D_SCR_01_0_SCRREG                  0
#define GPIO_D_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_D_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_D_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_D_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_D_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_D_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_D_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_D_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_D_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_D_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_D_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_D_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_D_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_D_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_D_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_D_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR7_SHIFT)
#define GPIO_D_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_D_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_D_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_D_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR6_SHIFT)
#define GPIO_D_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_D_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_D_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_D_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR5_SHIFT)
#define GPIO_D_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_D_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_D_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_D_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR4_SHIFT)
#define GPIO_D_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_D_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_D_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_D_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR3_SHIFT)
#define GPIO_D_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_D_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_D_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_D_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR2_SHIFT)
#define GPIO_D_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_D_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_D_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_D_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR1_SHIFT)
#define GPIO_D_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_D_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_D_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_D_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR0_SHIFT)
#define GPIO_D_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_D_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_D_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_D_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G7W_SHIFT)
#define GPIO_D_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_D_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_D_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_D_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G6W_SHIFT)
#define GPIO_D_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_D_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_D_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_D_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G5W_SHIFT)
#define GPIO_D_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_D_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_D_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_D_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G4W_SHIFT)
#define GPIO_D_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_D_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_D_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_D_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G3W_SHIFT)
#define GPIO_D_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_D_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_D_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_D_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G2W_SHIFT)
#define GPIO_D_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_D_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_D_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_D_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G1W_SHIFT)
#define GPIO_D_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_D_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_D_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_D_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G0W_SHIFT)
#define GPIO_D_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_D_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_D_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_D_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G7R_SHIFT)
#define GPIO_D_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_D_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_D_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_D_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G6R_SHIFT)
#define GPIO_D_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_D_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_D_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_D_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G5R_SHIFT)
#define GPIO_D_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_D_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_D_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_D_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G4R_SHIFT)
#define GPIO_D_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_D_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_D_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_D_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G3R_SHIFT)
#define GPIO_D_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_D_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_D_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_D_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G2R_SHIFT)
#define GPIO_D_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_D_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_D_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_D_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G1R_SHIFT)
#define GPIO_D_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_D_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_D_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_D_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G0R_SHIFT)
#define GPIO_D_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_D_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_D_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_D_VM_02_0
#define GPIO_D_VM_02_0                  MK_ADDR_CONST(0x5090)
#define GPIO_D_VM_02_0_SECURE                   0x0
#define GPIO_D_VM_02_0_DUAL                     0x0
#define GPIO_D_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_D_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_D_VM_02_0_WORD_COUNT                       0x1
#define GPIO_D_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_D_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM1_SHIFT)
#define GPIO_D_VM_02_0_VM1_RANGE                        1:0
#define GPIO_D_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_D_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_D_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM2_SHIFT)
#define GPIO_D_VM_02_0_VM2_RANGE                        3:2
#define GPIO_D_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_D_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_D_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM3_SHIFT)
#define GPIO_D_VM_02_0_VM3_RANGE                        5:4
#define GPIO_D_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_D_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_D_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_D_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM4_SHIFT)
#define GPIO_D_VM_02_0_VM4_RANGE                        7:6
#define GPIO_D_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_D_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_D_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_D_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM5_SHIFT)
#define GPIO_D_VM_02_0_VM5_RANGE                        9:8
#define GPIO_D_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_D_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_D_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_D_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM6_SHIFT)
#define GPIO_D_VM_02_0_VM6_RANGE                        11:10
#define GPIO_D_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_D_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_D_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_D_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM7_SHIFT)
#define GPIO_D_VM_02_0_VM7_RANGE                        13:12
#define GPIO_D_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_D_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_D_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_D_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM8_SHIFT)
#define GPIO_D_VM_02_0_VM8_RANGE                        15:14
#define GPIO_D_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_D_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_D_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_SCR_02_0
#define GPIO_D_SCR_02_0                 MK_ADDR_CONST(0x5094)
#define GPIO_D_SCR_02_0_SECURE                  0x0
#define GPIO_D_SCR_02_0_DUAL                    0x0
#define GPIO_D_SCR_02_0_SCR                     0
#define GPIO_D_SCR_02_0_SCRREG                  0
#define GPIO_D_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_D_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_D_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_D_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_D_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_D_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_D_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_D_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_D_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_D_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_D_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_D_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_D_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_D_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_D_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_D_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR7_SHIFT)
#define GPIO_D_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_D_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_D_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_D_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR6_SHIFT)
#define GPIO_D_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_D_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_D_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_D_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR5_SHIFT)
#define GPIO_D_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_D_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_D_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_D_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR4_SHIFT)
#define GPIO_D_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_D_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_D_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_D_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR3_SHIFT)
#define GPIO_D_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_D_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_D_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_D_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR2_SHIFT)
#define GPIO_D_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_D_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_D_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_D_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR1_SHIFT)
#define GPIO_D_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_D_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_D_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_D_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR0_SHIFT)
#define GPIO_D_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_D_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_D_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_D_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G7W_SHIFT)
#define GPIO_D_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_D_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_D_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_D_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G6W_SHIFT)
#define GPIO_D_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_D_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_D_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_D_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G5W_SHIFT)
#define GPIO_D_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_D_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_D_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_D_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G4W_SHIFT)
#define GPIO_D_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_D_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_D_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_D_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G3W_SHIFT)
#define GPIO_D_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_D_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_D_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_D_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G2W_SHIFT)
#define GPIO_D_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_D_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_D_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_D_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G1W_SHIFT)
#define GPIO_D_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_D_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_D_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_D_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G0W_SHIFT)
#define GPIO_D_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_D_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_D_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_D_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G7R_SHIFT)
#define GPIO_D_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_D_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_D_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_D_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G6R_SHIFT)
#define GPIO_D_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_D_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_D_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_D_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G5R_SHIFT)
#define GPIO_D_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_D_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_D_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_D_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G4R_SHIFT)
#define GPIO_D_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_D_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_D_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_D_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G3R_SHIFT)
#define GPIO_D_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_D_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_D_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_D_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G2R_SHIFT)
#define GPIO_D_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_D_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_D_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_D_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G1R_SHIFT)
#define GPIO_D_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_D_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_D_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_D_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G0R_SHIFT)
#define GPIO_D_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_D_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_D_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_D_VM_03_0
#define GPIO_D_VM_03_0                  MK_ADDR_CONST(0x5098)
#define GPIO_D_VM_03_0_SECURE                   0x0
#define GPIO_D_VM_03_0_DUAL                     0x0
#define GPIO_D_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_D_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_D_VM_03_0_WORD_COUNT                       0x1
#define GPIO_D_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_D_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM1_SHIFT)
#define GPIO_D_VM_03_0_VM1_RANGE                        1:0
#define GPIO_D_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_D_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_D_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM2_SHIFT)
#define GPIO_D_VM_03_0_VM2_RANGE                        3:2
#define GPIO_D_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_D_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_D_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM3_SHIFT)
#define GPIO_D_VM_03_0_VM3_RANGE                        5:4
#define GPIO_D_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_D_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_D_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_D_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM4_SHIFT)
#define GPIO_D_VM_03_0_VM4_RANGE                        7:6
#define GPIO_D_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_D_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_D_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_D_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM5_SHIFT)
#define GPIO_D_VM_03_0_VM5_RANGE                        9:8
#define GPIO_D_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_D_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_D_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_D_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM6_SHIFT)
#define GPIO_D_VM_03_0_VM6_RANGE                        11:10
#define GPIO_D_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_D_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_D_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_D_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM7_SHIFT)
#define GPIO_D_VM_03_0_VM7_RANGE                        13:12
#define GPIO_D_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_D_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_D_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_D_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_D_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM8_SHIFT)
#define GPIO_D_VM_03_0_VM8_RANGE                        15:14
#define GPIO_D_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_D_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_D_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_D_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_D_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_SCR_03_0
#define GPIO_D_SCR_03_0                 MK_ADDR_CONST(0x509c)
#define GPIO_D_SCR_03_0_SECURE                  0x0
#define GPIO_D_SCR_03_0_DUAL                    0x0
#define GPIO_D_SCR_03_0_SCR                     0
#define GPIO_D_SCR_03_0_SCRREG                  0
#define GPIO_D_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_D_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_D_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_D_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_D_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_D_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_D_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_D_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_D_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_D_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_D_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_D_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_D_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_D_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_D_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_D_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_D_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_D_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_D_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_D_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_D_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_D_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_D_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_D_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_D_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_D_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_D_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_D_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR7_SHIFT)
#define GPIO_D_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_D_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_D_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_D_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_D_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR6_SHIFT)
#define GPIO_D_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_D_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_D_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_D_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_D_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR5_SHIFT)
#define GPIO_D_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_D_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_D_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_D_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_D_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR4_SHIFT)
#define GPIO_D_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_D_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_D_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_D_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_D_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR3_SHIFT)
#define GPIO_D_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_D_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_D_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_D_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_D_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR2_SHIFT)
#define GPIO_D_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_D_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_D_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_D_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_D_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR1_SHIFT)
#define GPIO_D_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_D_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_D_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_D_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_D_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR0_SHIFT)
#define GPIO_D_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_D_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_D_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_D_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_D_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G7W_SHIFT)
#define GPIO_D_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_D_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_D_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_D_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_D_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G6W_SHIFT)
#define GPIO_D_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_D_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_D_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_D_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_D_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G5W_SHIFT)
#define GPIO_D_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_D_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_D_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_D_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_D_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G4W_SHIFT)
#define GPIO_D_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_D_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_D_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_D_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_D_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G3W_SHIFT)
#define GPIO_D_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_D_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_D_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_D_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_D_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G2W_SHIFT)
#define GPIO_D_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_D_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_D_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_D_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_D_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G1W_SHIFT)
#define GPIO_D_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_D_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_D_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_D_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_D_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G0W_SHIFT)
#define GPIO_D_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_D_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_D_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_D_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_D_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G7R_SHIFT)
#define GPIO_D_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_D_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_D_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_D_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_D_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G6R_SHIFT)
#define GPIO_D_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_D_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_D_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_D_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_D_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G5R_SHIFT)
#define GPIO_D_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_D_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_D_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_D_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_D_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G4R_SHIFT)
#define GPIO_D_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_D_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_D_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_D_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_D_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G3R_SHIFT)
#define GPIO_D_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_D_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_D_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_D_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_D_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G2R_SHIFT)
#define GPIO_D_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_D_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_D_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_D_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_D_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G1R_SHIFT)
#define GPIO_D_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_D_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_D_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_D_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_D_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_D_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G0R_SHIFT)
#define GPIO_D_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_D_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_D_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_D_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_D_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_D_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x50a0

// Reserved address 0x50a4

// Reserved address 0x50a8

// Reserved address 0x50ac

// Reserved address 0x50b0

// Reserved address 0x50b4

// Reserved address 0x50b8

// Reserved address 0x50bc

// Register GPIO_E_VM_00_0
#define GPIO_E_VM_00_0                  MK_ADDR_CONST(0x50c0)
#define GPIO_E_VM_00_0_SECURE                   0x0
#define GPIO_E_VM_00_0_DUAL                     0x0
#define GPIO_E_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_00_0_WORD_COUNT                       0x1
#define GPIO_E_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM1_SHIFT)
#define GPIO_E_VM_00_0_VM1_RANGE                        1:0
#define GPIO_E_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_E_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_E_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM2_SHIFT)
#define GPIO_E_VM_00_0_VM2_RANGE                        3:2
#define GPIO_E_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_E_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_E_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_E_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM3_SHIFT)
#define GPIO_E_VM_00_0_VM3_RANGE                        5:4
#define GPIO_E_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_E_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_E_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_E_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM4_SHIFT)
#define GPIO_E_VM_00_0_VM4_RANGE                        7:6
#define GPIO_E_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_E_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_E_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM5_SHIFT)
#define GPIO_E_VM_00_0_VM5_RANGE                        9:8
#define GPIO_E_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_E_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_E_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_E_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM6_SHIFT)
#define GPIO_E_VM_00_0_VM6_RANGE                        11:10
#define GPIO_E_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_E_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_E_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_E_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM7_SHIFT)
#define GPIO_E_VM_00_0_VM7_RANGE                        13:12
#define GPIO_E_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_E_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_E_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_E_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM8_SHIFT)
#define GPIO_E_VM_00_0_VM8_RANGE                        15:14
#define GPIO_E_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_E_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_E_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_00_0
#define GPIO_E_SCR_00_0                 MK_ADDR_CONST(0x50c4)
#define GPIO_E_SCR_00_0_SECURE                  0x0
#define GPIO_E_SCR_00_0_DUAL                    0x0
#define GPIO_E_SCR_00_0_SCR                     0
#define GPIO_E_SCR_00_0_SCRREG                  0
#define GPIO_E_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_E_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_E_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_E_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_E_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_E_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_E_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_E_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_E_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR7_SHIFT)
#define GPIO_E_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_E_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR6_SHIFT)
#define GPIO_E_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_E_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR5_SHIFT)
#define GPIO_E_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_E_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR4_SHIFT)
#define GPIO_E_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_E_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR3_SHIFT)
#define GPIO_E_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_E_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR2_SHIFT)
#define GPIO_E_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_E_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR1_SHIFT)
#define GPIO_E_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_E_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR0_SHIFT)
#define GPIO_E_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_E_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G7W_SHIFT)
#define GPIO_E_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_E_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G6W_SHIFT)
#define GPIO_E_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_E_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G5W_SHIFT)
#define GPIO_E_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_E_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G4W_SHIFT)
#define GPIO_E_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_E_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G3W_SHIFT)
#define GPIO_E_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_E_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G2W_SHIFT)
#define GPIO_E_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_E_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G1W_SHIFT)
#define GPIO_E_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_E_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G0W_SHIFT)
#define GPIO_E_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_E_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G7R_SHIFT)
#define GPIO_E_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_E_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G6R_SHIFT)
#define GPIO_E_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G5R_SHIFT)
#define GPIO_E_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_E_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G4R_SHIFT)
#define GPIO_E_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_E_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G3R_SHIFT)
#define GPIO_E_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_E_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G2R_SHIFT)
#define GPIO_E_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_E_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G1R_SHIFT)
#define GPIO_E_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G0R_SHIFT)
#define GPIO_E_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_E_VM_01_0
#define GPIO_E_VM_01_0                  MK_ADDR_CONST(0x50c8)
#define GPIO_E_VM_01_0_SECURE                   0x0
#define GPIO_E_VM_01_0_DUAL                     0x0
#define GPIO_E_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_01_0_WORD_COUNT                       0x1
#define GPIO_E_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM1_SHIFT)
#define GPIO_E_VM_01_0_VM1_RANGE                        1:0
#define GPIO_E_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_E_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_E_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM2_SHIFT)
#define GPIO_E_VM_01_0_VM2_RANGE                        3:2
#define GPIO_E_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_E_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_E_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_E_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM3_SHIFT)
#define GPIO_E_VM_01_0_VM3_RANGE                        5:4
#define GPIO_E_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_E_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_E_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_E_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM4_SHIFT)
#define GPIO_E_VM_01_0_VM4_RANGE                        7:6
#define GPIO_E_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_E_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_E_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM5_SHIFT)
#define GPIO_E_VM_01_0_VM5_RANGE                        9:8
#define GPIO_E_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_E_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_E_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_E_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM6_SHIFT)
#define GPIO_E_VM_01_0_VM6_RANGE                        11:10
#define GPIO_E_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_E_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_E_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_E_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM7_SHIFT)
#define GPIO_E_VM_01_0_VM7_RANGE                        13:12
#define GPIO_E_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_E_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_E_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_E_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM8_SHIFT)
#define GPIO_E_VM_01_0_VM8_RANGE                        15:14
#define GPIO_E_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_E_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_E_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_01_0
#define GPIO_E_SCR_01_0                 MK_ADDR_CONST(0x50cc)
#define GPIO_E_SCR_01_0_SECURE                  0x0
#define GPIO_E_SCR_01_0_DUAL                    0x0
#define GPIO_E_SCR_01_0_SCR                     0
#define GPIO_E_SCR_01_0_SCRREG                  0
#define GPIO_E_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_E_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_E_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_E_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_E_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_E_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_E_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_E_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_E_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR7_SHIFT)
#define GPIO_E_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_E_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR6_SHIFT)
#define GPIO_E_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_E_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR5_SHIFT)
#define GPIO_E_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_E_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR4_SHIFT)
#define GPIO_E_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_E_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR3_SHIFT)
#define GPIO_E_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_E_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR2_SHIFT)
#define GPIO_E_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_E_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR1_SHIFT)
#define GPIO_E_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_E_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR0_SHIFT)
#define GPIO_E_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_E_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G7W_SHIFT)
#define GPIO_E_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_E_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G6W_SHIFT)
#define GPIO_E_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_E_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G5W_SHIFT)
#define GPIO_E_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_E_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G4W_SHIFT)
#define GPIO_E_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_E_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G3W_SHIFT)
#define GPIO_E_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_E_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G2W_SHIFT)
#define GPIO_E_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_E_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G1W_SHIFT)
#define GPIO_E_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_E_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G0W_SHIFT)
#define GPIO_E_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_E_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G7R_SHIFT)
#define GPIO_E_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_E_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G6R_SHIFT)
#define GPIO_E_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G5R_SHIFT)
#define GPIO_E_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_E_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G4R_SHIFT)
#define GPIO_E_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_E_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G3R_SHIFT)
#define GPIO_E_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_E_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G2R_SHIFT)
#define GPIO_E_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_E_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G1R_SHIFT)
#define GPIO_E_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G0R_SHIFT)
#define GPIO_E_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_E_VM_02_0
#define GPIO_E_VM_02_0                  MK_ADDR_CONST(0x50d0)
#define GPIO_E_VM_02_0_SECURE                   0x0
#define GPIO_E_VM_02_0_DUAL                     0x0
#define GPIO_E_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_02_0_WORD_COUNT                       0x1
#define GPIO_E_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM1_SHIFT)
#define GPIO_E_VM_02_0_VM1_RANGE                        1:0
#define GPIO_E_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_E_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_E_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM2_SHIFT)
#define GPIO_E_VM_02_0_VM2_RANGE                        3:2
#define GPIO_E_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_E_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_E_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_E_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM3_SHIFT)
#define GPIO_E_VM_02_0_VM3_RANGE                        5:4
#define GPIO_E_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_E_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_E_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_E_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM4_SHIFT)
#define GPIO_E_VM_02_0_VM4_RANGE                        7:6
#define GPIO_E_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_E_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_E_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM5_SHIFT)
#define GPIO_E_VM_02_0_VM5_RANGE                        9:8
#define GPIO_E_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_E_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_E_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_E_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM6_SHIFT)
#define GPIO_E_VM_02_0_VM6_RANGE                        11:10
#define GPIO_E_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_E_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_E_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_E_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM7_SHIFT)
#define GPIO_E_VM_02_0_VM7_RANGE                        13:12
#define GPIO_E_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_E_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_E_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_E_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM8_SHIFT)
#define GPIO_E_VM_02_0_VM8_RANGE                        15:14
#define GPIO_E_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_E_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_E_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_02_0
#define GPIO_E_SCR_02_0                 MK_ADDR_CONST(0x50d4)
#define GPIO_E_SCR_02_0_SECURE                  0x0
#define GPIO_E_SCR_02_0_DUAL                    0x0
#define GPIO_E_SCR_02_0_SCR                     0
#define GPIO_E_SCR_02_0_SCRREG                  0
#define GPIO_E_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_E_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_E_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_E_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_E_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_E_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_E_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_E_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_E_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR7_SHIFT)
#define GPIO_E_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_E_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR6_SHIFT)
#define GPIO_E_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_E_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR5_SHIFT)
#define GPIO_E_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_E_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR4_SHIFT)
#define GPIO_E_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_E_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR3_SHIFT)
#define GPIO_E_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_E_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR2_SHIFT)
#define GPIO_E_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_E_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR1_SHIFT)
#define GPIO_E_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_E_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR0_SHIFT)
#define GPIO_E_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_E_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G7W_SHIFT)
#define GPIO_E_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_E_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G6W_SHIFT)
#define GPIO_E_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_E_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G5W_SHIFT)
#define GPIO_E_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_E_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G4W_SHIFT)
#define GPIO_E_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_E_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G3W_SHIFT)
#define GPIO_E_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_E_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G2W_SHIFT)
#define GPIO_E_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_E_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G1W_SHIFT)
#define GPIO_E_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_E_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G0W_SHIFT)
#define GPIO_E_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_E_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G7R_SHIFT)
#define GPIO_E_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_E_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G6R_SHIFT)
#define GPIO_E_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G5R_SHIFT)
#define GPIO_E_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_E_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G4R_SHIFT)
#define GPIO_E_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_E_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G3R_SHIFT)
#define GPIO_E_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_E_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G2R_SHIFT)
#define GPIO_E_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_E_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G1R_SHIFT)
#define GPIO_E_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G0R_SHIFT)
#define GPIO_E_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_E_VM_03_0
#define GPIO_E_VM_03_0                  MK_ADDR_CONST(0x50d8)
#define GPIO_E_VM_03_0_SECURE                   0x0
#define GPIO_E_VM_03_0_DUAL                     0x0
#define GPIO_E_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_03_0_WORD_COUNT                       0x1
#define GPIO_E_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM1_SHIFT)
#define GPIO_E_VM_03_0_VM1_RANGE                        1:0
#define GPIO_E_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_E_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_E_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM2_SHIFT)
#define GPIO_E_VM_03_0_VM2_RANGE                        3:2
#define GPIO_E_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_E_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_E_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_E_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM3_SHIFT)
#define GPIO_E_VM_03_0_VM3_RANGE                        5:4
#define GPIO_E_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_E_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_E_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_E_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM4_SHIFT)
#define GPIO_E_VM_03_0_VM4_RANGE                        7:6
#define GPIO_E_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_E_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_E_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM5_SHIFT)
#define GPIO_E_VM_03_0_VM5_RANGE                        9:8
#define GPIO_E_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_E_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_E_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_E_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM6_SHIFT)
#define GPIO_E_VM_03_0_VM6_RANGE                        11:10
#define GPIO_E_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_E_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_E_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_E_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM7_SHIFT)
#define GPIO_E_VM_03_0_VM7_RANGE                        13:12
#define GPIO_E_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_E_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_E_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_E_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM8_SHIFT)
#define GPIO_E_VM_03_0_VM8_RANGE                        15:14
#define GPIO_E_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_E_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_E_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_03_0
#define GPIO_E_SCR_03_0                 MK_ADDR_CONST(0x50dc)
#define GPIO_E_SCR_03_0_SECURE                  0x0
#define GPIO_E_SCR_03_0_DUAL                    0x0
#define GPIO_E_SCR_03_0_SCR                     0
#define GPIO_E_SCR_03_0_SCRREG                  0
#define GPIO_E_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_E_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_E_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_E_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_E_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_E_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_E_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_E_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_E_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR7_SHIFT)
#define GPIO_E_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_E_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR6_SHIFT)
#define GPIO_E_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_E_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR5_SHIFT)
#define GPIO_E_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_E_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR4_SHIFT)
#define GPIO_E_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_E_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR3_SHIFT)
#define GPIO_E_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_E_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR2_SHIFT)
#define GPIO_E_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_E_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR1_SHIFT)
#define GPIO_E_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_E_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR0_SHIFT)
#define GPIO_E_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_E_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G7W_SHIFT)
#define GPIO_E_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_E_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G6W_SHIFT)
#define GPIO_E_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_E_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G5W_SHIFT)
#define GPIO_E_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_E_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G4W_SHIFT)
#define GPIO_E_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_E_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G3W_SHIFT)
#define GPIO_E_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_E_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G2W_SHIFT)
#define GPIO_E_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_E_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G1W_SHIFT)
#define GPIO_E_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_E_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G0W_SHIFT)
#define GPIO_E_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_E_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G7R_SHIFT)
#define GPIO_E_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_E_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G6R_SHIFT)
#define GPIO_E_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G5R_SHIFT)
#define GPIO_E_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_E_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G4R_SHIFT)
#define GPIO_E_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_E_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G3R_SHIFT)
#define GPIO_E_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_E_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G2R_SHIFT)
#define GPIO_E_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_E_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G1R_SHIFT)
#define GPIO_E_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G0R_SHIFT)
#define GPIO_E_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_E_VM_04_0
#define GPIO_E_VM_04_0                  MK_ADDR_CONST(0x50e0)
#define GPIO_E_VM_04_0_SECURE                   0x0
#define GPIO_E_VM_04_0_DUAL                     0x0
#define GPIO_E_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_04_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_04_0_WORD_COUNT                       0x1
#define GPIO_E_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM1_SHIFT)
#define GPIO_E_VM_04_0_VM1_RANGE                        1:0
#define GPIO_E_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_E_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_E_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM2_SHIFT)
#define GPIO_E_VM_04_0_VM2_RANGE                        3:2
#define GPIO_E_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_E_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_E_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_E_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM3_SHIFT)
#define GPIO_E_VM_04_0_VM3_RANGE                        5:4
#define GPIO_E_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_E_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_E_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_E_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM4_SHIFT)
#define GPIO_E_VM_04_0_VM4_RANGE                        7:6
#define GPIO_E_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_E_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_E_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM5_SHIFT)
#define GPIO_E_VM_04_0_VM5_RANGE                        9:8
#define GPIO_E_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_E_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_E_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_E_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM6_SHIFT)
#define GPIO_E_VM_04_0_VM6_RANGE                        11:10
#define GPIO_E_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_E_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_E_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_E_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM7_SHIFT)
#define GPIO_E_VM_04_0_VM7_RANGE                        13:12
#define GPIO_E_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_E_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_E_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_E_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM8_SHIFT)
#define GPIO_E_VM_04_0_VM8_RANGE                        15:14
#define GPIO_E_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_E_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_E_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_04_0
#define GPIO_E_SCR_04_0                 MK_ADDR_CONST(0x50e4)
#define GPIO_E_SCR_04_0_SECURE                  0x0
#define GPIO_E_SCR_04_0_DUAL                    0x0
#define GPIO_E_SCR_04_0_SCR                     0
#define GPIO_E_SCR_04_0_SCRREG                  0
#define GPIO_E_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_E_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_E_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_E_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_E_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_E_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_E_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_E_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_E_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR7_SHIFT)
#define GPIO_E_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_E_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR6_SHIFT)
#define GPIO_E_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_E_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR5_SHIFT)
#define GPIO_E_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_E_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR4_SHIFT)
#define GPIO_E_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_E_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR3_SHIFT)
#define GPIO_E_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_E_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR2_SHIFT)
#define GPIO_E_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_E_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR1_SHIFT)
#define GPIO_E_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_E_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR0_SHIFT)
#define GPIO_E_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_E_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G7W_SHIFT)
#define GPIO_E_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_E_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G6W_SHIFT)
#define GPIO_E_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_E_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G5W_SHIFT)
#define GPIO_E_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_E_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G4W_SHIFT)
#define GPIO_E_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_E_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G3W_SHIFT)
#define GPIO_E_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_E_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G2W_SHIFT)
#define GPIO_E_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_E_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G1W_SHIFT)
#define GPIO_E_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_E_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G0W_SHIFT)
#define GPIO_E_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_E_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G7R_SHIFT)
#define GPIO_E_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_E_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G6R_SHIFT)
#define GPIO_E_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G5R_SHIFT)
#define GPIO_E_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_E_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G4R_SHIFT)
#define GPIO_E_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_E_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G3R_SHIFT)
#define GPIO_E_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_E_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G2R_SHIFT)
#define GPIO_E_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_E_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G1R_SHIFT)
#define GPIO_E_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G0R_SHIFT)
#define GPIO_E_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_E_VM_05_0
#define GPIO_E_VM_05_0                  MK_ADDR_CONST(0x50e8)
#define GPIO_E_VM_05_0_SECURE                   0x0
#define GPIO_E_VM_05_0_DUAL                     0x0
#define GPIO_E_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_05_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_05_0_WORD_COUNT                       0x1
#define GPIO_E_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM1_SHIFT)
#define GPIO_E_VM_05_0_VM1_RANGE                        1:0
#define GPIO_E_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_E_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_E_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM2_SHIFT)
#define GPIO_E_VM_05_0_VM2_RANGE                        3:2
#define GPIO_E_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_E_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_E_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_E_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM3_SHIFT)
#define GPIO_E_VM_05_0_VM3_RANGE                        5:4
#define GPIO_E_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_E_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_E_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_E_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM4_SHIFT)
#define GPIO_E_VM_05_0_VM4_RANGE                        7:6
#define GPIO_E_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_E_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_E_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM5_SHIFT)
#define GPIO_E_VM_05_0_VM5_RANGE                        9:8
#define GPIO_E_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_E_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_E_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_E_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM6_SHIFT)
#define GPIO_E_VM_05_0_VM6_RANGE                        11:10
#define GPIO_E_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_E_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_E_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_E_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM7_SHIFT)
#define GPIO_E_VM_05_0_VM7_RANGE                        13:12
#define GPIO_E_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_E_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_E_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_E_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM8_SHIFT)
#define GPIO_E_VM_05_0_VM8_RANGE                        15:14
#define GPIO_E_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_E_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_E_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_05_0
#define GPIO_E_SCR_05_0                 MK_ADDR_CONST(0x50ec)
#define GPIO_E_SCR_05_0_SECURE                  0x0
#define GPIO_E_SCR_05_0_DUAL                    0x0
#define GPIO_E_SCR_05_0_SCR                     0
#define GPIO_E_SCR_05_0_SCRREG                  0
#define GPIO_E_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_E_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_E_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_E_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_E_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_E_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_E_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_E_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_E_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR7_SHIFT)
#define GPIO_E_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_E_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR6_SHIFT)
#define GPIO_E_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_E_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR5_SHIFT)
#define GPIO_E_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_E_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR4_SHIFT)
#define GPIO_E_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_E_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR3_SHIFT)
#define GPIO_E_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_E_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR2_SHIFT)
#define GPIO_E_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_E_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR1_SHIFT)
#define GPIO_E_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_E_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR0_SHIFT)
#define GPIO_E_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_E_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G7W_SHIFT)
#define GPIO_E_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_E_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G6W_SHIFT)
#define GPIO_E_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_E_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G5W_SHIFT)
#define GPIO_E_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_E_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G4W_SHIFT)
#define GPIO_E_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_E_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G3W_SHIFT)
#define GPIO_E_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_E_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G2W_SHIFT)
#define GPIO_E_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_E_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G1W_SHIFT)
#define GPIO_E_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_E_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G0W_SHIFT)
#define GPIO_E_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_E_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G7R_SHIFT)
#define GPIO_E_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_E_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G6R_SHIFT)
#define GPIO_E_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G5R_SHIFT)
#define GPIO_E_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_E_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G4R_SHIFT)
#define GPIO_E_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_E_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G3R_SHIFT)
#define GPIO_E_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_E_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G2R_SHIFT)
#define GPIO_E_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_E_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G1R_SHIFT)
#define GPIO_E_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G0R_SHIFT)
#define GPIO_E_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_E_VM_06_0
#define GPIO_E_VM_06_0                  MK_ADDR_CONST(0x50f0)
#define GPIO_E_VM_06_0_SECURE                   0x0
#define GPIO_E_VM_06_0_DUAL                     0x0
#define GPIO_E_VM_06_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_06_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_06_0_WORD_COUNT                       0x1
#define GPIO_E_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM1_SHIFT)
#define GPIO_E_VM_06_0_VM1_RANGE                        1:0
#define GPIO_E_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_E_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_VM_06_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_E_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM2_SHIFT)
#define GPIO_E_VM_06_0_VM2_RANGE                        3:2
#define GPIO_E_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_E_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_E_VM_06_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_E_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM3_SHIFT)
#define GPIO_E_VM_06_0_VM3_RANGE                        5:4
#define GPIO_E_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_E_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_E_VM_06_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_E_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM4_SHIFT)
#define GPIO_E_VM_06_0_VM4_RANGE                        7:6
#define GPIO_E_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_E_VM_06_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_E_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM5_SHIFT)
#define GPIO_E_VM_06_0_VM5_RANGE                        9:8
#define GPIO_E_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_E_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_E_VM_06_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_E_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM6_SHIFT)
#define GPIO_E_VM_06_0_VM6_RANGE                        11:10
#define GPIO_E_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_E_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_E_VM_06_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_E_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM7_SHIFT)
#define GPIO_E_VM_06_0_VM7_RANGE                        13:12
#define GPIO_E_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_E_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_E_VM_06_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_E_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM8_SHIFT)
#define GPIO_E_VM_06_0_VM8_RANGE                        15:14
#define GPIO_E_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_E_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_E_VM_06_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_06_0
#define GPIO_E_SCR_06_0                 MK_ADDR_CONST(0x50f4)
#define GPIO_E_SCR_06_0_SECURE                  0x0
#define GPIO_E_SCR_06_0_DUAL                    0x0
#define GPIO_E_SCR_06_0_SCR                     0
#define GPIO_E_SCR_06_0_SCRREG                  0
#define GPIO_E_SCR_06_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_E_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_06_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_06_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_E_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_06_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_06_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_E_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_06_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_06_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_E_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_06_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_06_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_E_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_E_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_E_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_E_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR7_SHIFT)
#define GPIO_E_SCR_06_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_06_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_E_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR6_SHIFT)
#define GPIO_E_SCR_06_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_06_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_E_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR5_SHIFT)
#define GPIO_E_SCR_06_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_06_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_E_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR4_SHIFT)
#define GPIO_E_SCR_06_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_06_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_E_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR3_SHIFT)
#define GPIO_E_SCR_06_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_06_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_E_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR2_SHIFT)
#define GPIO_E_SCR_06_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_06_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_E_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR1_SHIFT)
#define GPIO_E_SCR_06_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_06_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_E_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR0_SHIFT)
#define GPIO_E_SCR_06_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_06_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_E_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G7W_SHIFT)
#define GPIO_E_SCR_06_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_06_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_E_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G6W_SHIFT)
#define GPIO_E_SCR_06_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_06_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_E_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G5W_SHIFT)
#define GPIO_E_SCR_06_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_06_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_E_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G4W_SHIFT)
#define GPIO_E_SCR_06_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_06_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_E_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G3W_SHIFT)
#define GPIO_E_SCR_06_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_06_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_E_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G2W_SHIFT)
#define GPIO_E_SCR_06_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_06_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_E_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G1W_SHIFT)
#define GPIO_E_SCR_06_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_06_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_E_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G0W_SHIFT)
#define GPIO_E_SCR_06_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_06_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_E_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G7R_SHIFT)
#define GPIO_E_SCR_06_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_06_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_E_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G6R_SHIFT)
#define GPIO_E_SCR_06_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_06_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G5R_SHIFT)
#define GPIO_E_SCR_06_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_06_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_E_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G4R_SHIFT)
#define GPIO_E_SCR_06_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_06_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_E_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G3R_SHIFT)
#define GPIO_E_SCR_06_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_06_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_E_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G2R_SHIFT)
#define GPIO_E_SCR_06_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_06_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_E_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G1R_SHIFT)
#define GPIO_E_SCR_06_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_06_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G0R_SHIFT)
#define GPIO_E_SCR_06_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_06_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_E_VM_07_0
#define GPIO_E_VM_07_0                  MK_ADDR_CONST(0x50f8)
#define GPIO_E_VM_07_0_SECURE                   0x0
#define GPIO_E_VM_07_0_DUAL                     0x0
#define GPIO_E_VM_07_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_07_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_E_VM_07_0_WORD_COUNT                       0x1
#define GPIO_E_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_E_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM1_SHIFT)
#define GPIO_E_VM_07_0_VM1_RANGE                        1:0
#define GPIO_E_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_E_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_VM_07_0_VM1_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_E_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM2_SHIFT)
#define GPIO_E_VM_07_0_VM2_RANGE                        3:2
#define GPIO_E_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_E_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_E_VM_07_0_VM2_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_E_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM3_SHIFT)
#define GPIO_E_VM_07_0_VM3_RANGE                        5:4
#define GPIO_E_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_E_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_E_VM_07_0_VM3_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_E_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM4_SHIFT)
#define GPIO_E_VM_07_0_VM4_RANGE                        7:6
#define GPIO_E_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_E_VM_07_0_VM4_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_E_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM5_SHIFT)
#define GPIO_E_VM_07_0_VM5_RANGE                        9:8
#define GPIO_E_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_E_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_E_VM_07_0_VM5_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_E_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM6_SHIFT)
#define GPIO_E_VM_07_0_VM6_RANGE                        11:10
#define GPIO_E_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_E_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_E_VM_07_0_VM6_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_E_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM7_SHIFT)
#define GPIO_E_VM_07_0_VM7_RANGE                        13:12
#define GPIO_E_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_E_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_E_VM_07_0_VM7_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_E_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_E_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM8_SHIFT)
#define GPIO_E_VM_07_0_VM8_RANGE                        15:14
#define GPIO_E_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_E_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_E_VM_07_0_VM8_WOFFSET                      0x0
#define GPIO_E_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_E_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_SCR_07_0
#define GPIO_E_SCR_07_0                 MK_ADDR_CONST(0x50fc)
#define GPIO_E_SCR_07_0_SECURE                  0x0
#define GPIO_E_SCR_07_0_DUAL                    0x0
#define GPIO_E_SCR_07_0_SCR                     0
#define GPIO_E_SCR_07_0_SCRREG                  0
#define GPIO_E_SCR_07_0_WORD_COUNT                      0x1
#define GPIO_E_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_E_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_E_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_LCK_SHIFT)
#define GPIO_E_SCR_07_0_SEC_LCK_RANGE                   29:29
#define GPIO_E_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_E_SCR_07_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_E_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_WEN_SHIFT)
#define GPIO_E_SCR_07_0_SEC_WEN_RANGE                   28:28
#define GPIO_E_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_E_SCR_07_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_E_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_REN_SHIFT)
#define GPIO_E_SCR_07_0_SEC_REN_RANGE                   27:27
#define GPIO_E_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_E_SCR_07_0_SEC_REN_WOFFSET                 0x0
#define GPIO_E_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_E_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_07_0_SEC_OWNER_SHIFT)
#define GPIO_E_SCR_07_0_SEC_OWNER_RANGE                 26:24
#define GPIO_E_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_E_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_E_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_E_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_E_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_E_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR7_SHIFT)
#define GPIO_E_SCR_07_0_PR7_RANGE                       23:23
#define GPIO_E_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_E_SCR_07_0_PR7_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_E_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR6_SHIFT)
#define GPIO_E_SCR_07_0_PR6_RANGE                       22:22
#define GPIO_E_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_E_SCR_07_0_PR6_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_E_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR5_SHIFT)
#define GPIO_E_SCR_07_0_PR5_RANGE                       21:21
#define GPIO_E_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_E_SCR_07_0_PR5_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_E_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR4_SHIFT)
#define GPIO_E_SCR_07_0_PR4_RANGE                       20:20
#define GPIO_E_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_E_SCR_07_0_PR4_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_E_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR3_SHIFT)
#define GPIO_E_SCR_07_0_PR3_RANGE                       19:19
#define GPIO_E_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_E_SCR_07_0_PR3_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_E_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR2_SHIFT)
#define GPIO_E_SCR_07_0_PR2_RANGE                       18:18
#define GPIO_E_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_E_SCR_07_0_PR2_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_E_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR1_SHIFT)
#define GPIO_E_SCR_07_0_PR1_RANGE                       17:17
#define GPIO_E_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_E_SCR_07_0_PR1_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_E_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR0_SHIFT)
#define GPIO_E_SCR_07_0_PR0_RANGE                       16:16
#define GPIO_E_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_E_SCR_07_0_PR0_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_E_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G7W_SHIFT)
#define GPIO_E_SCR_07_0_G7W_RANGE                       15:15
#define GPIO_E_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_E_SCR_07_0_G7W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_E_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G6W_SHIFT)
#define GPIO_E_SCR_07_0_G6W_RANGE                       14:14
#define GPIO_E_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_E_SCR_07_0_G6W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_E_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G5W_SHIFT)
#define GPIO_E_SCR_07_0_G5W_RANGE                       13:13
#define GPIO_E_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_E_SCR_07_0_G5W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_E_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G4W_SHIFT)
#define GPIO_E_SCR_07_0_G4W_RANGE                       12:12
#define GPIO_E_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_E_SCR_07_0_G4W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_E_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G3W_SHIFT)
#define GPIO_E_SCR_07_0_G3W_RANGE                       11:11
#define GPIO_E_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_E_SCR_07_0_G3W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_E_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G2W_SHIFT)
#define GPIO_E_SCR_07_0_G2W_RANGE                       10:10
#define GPIO_E_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_E_SCR_07_0_G2W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_E_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G1W_SHIFT)
#define GPIO_E_SCR_07_0_G1W_RANGE                       9:9
#define GPIO_E_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_E_SCR_07_0_G1W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_E_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G0W_SHIFT)
#define GPIO_E_SCR_07_0_G0W_RANGE                       8:8
#define GPIO_E_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_E_SCR_07_0_G0W_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_E_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G7R_SHIFT)
#define GPIO_E_SCR_07_0_G7R_RANGE                       7:7
#define GPIO_E_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_E_SCR_07_0_G7R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_E_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G6R_SHIFT)
#define GPIO_E_SCR_07_0_G6R_RANGE                       6:6
#define GPIO_E_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_E_SCR_07_0_G6R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G5R_SHIFT)
#define GPIO_E_SCR_07_0_G5R_RANGE                       5:5
#define GPIO_E_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_SCR_07_0_G5R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_E_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G4R_SHIFT)
#define GPIO_E_SCR_07_0_G4R_RANGE                       4:4
#define GPIO_E_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_E_SCR_07_0_G4R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_E_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G3R_SHIFT)
#define GPIO_E_SCR_07_0_G3R_RANGE                       3:3
#define GPIO_E_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_E_SCR_07_0_G3R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_E_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G2R_SHIFT)
#define GPIO_E_SCR_07_0_G2R_RANGE                       2:2
#define GPIO_E_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_E_SCR_07_0_G2R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_E_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G1R_SHIFT)
#define GPIO_E_SCR_07_0_G1R_RANGE                       1:1
#define GPIO_E_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_E_SCR_07_0_G1R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_E_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G0R_SHIFT)
#define GPIO_E_SCR_07_0_G0R_RANGE                       0:0
#define GPIO_E_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_SCR_07_0_G0R_WOFFSET                     0x0
#define GPIO_E_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_E_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_F_VM_00_0
#define GPIO_F_VM_00_0                  MK_ADDR_CONST(0x5100)
#define GPIO_F_VM_00_0_SECURE                   0x0
#define GPIO_F_VM_00_0_DUAL                     0x0
#define GPIO_F_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_00_0_WORD_COUNT                       0x1
#define GPIO_F_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM1_SHIFT)
#define GPIO_F_VM_00_0_VM1_RANGE                        1:0
#define GPIO_F_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_F_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_VM_00_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_F_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM2_SHIFT)
#define GPIO_F_VM_00_0_VM2_RANGE                        3:2
#define GPIO_F_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_F_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_F_VM_00_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_F_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM3_SHIFT)
#define GPIO_F_VM_00_0_VM3_RANGE                        5:4
#define GPIO_F_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_F_VM_00_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_F_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM4_SHIFT)
#define GPIO_F_VM_00_0_VM4_RANGE                        7:6
#define GPIO_F_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_F_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_F_VM_00_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_F_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM5_SHIFT)
#define GPIO_F_VM_00_0_VM5_RANGE                        9:8
#define GPIO_F_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_F_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_F_VM_00_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_F_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM6_SHIFT)
#define GPIO_F_VM_00_0_VM6_RANGE                        11:10
#define GPIO_F_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_F_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_F_VM_00_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_F_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM7_SHIFT)
#define GPIO_F_VM_00_0_VM7_RANGE                        13:12
#define GPIO_F_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_F_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_F_VM_00_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_F_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM8_SHIFT)
#define GPIO_F_VM_00_0_VM8_RANGE                        15:14
#define GPIO_F_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_F_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_F_VM_00_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_00_0
#define GPIO_F_SCR_00_0                 MK_ADDR_CONST(0x5104)
#define GPIO_F_SCR_00_0_SECURE                  0x0
#define GPIO_F_SCR_00_0_DUAL                    0x0
#define GPIO_F_SCR_00_0_SCR                     0
#define GPIO_F_SCR_00_0_SCRREG                  0
#define GPIO_F_SCR_00_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_F_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_00_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_00_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_F_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_00_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_00_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_F_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_00_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_00_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_F_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_00_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_00_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_F_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_F_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_F_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_F_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR7_SHIFT)
#define GPIO_F_SCR_00_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_00_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_F_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR6_SHIFT)
#define GPIO_F_SCR_00_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_00_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_F_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR5_SHIFT)
#define GPIO_F_SCR_00_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_00_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_F_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR4_SHIFT)
#define GPIO_F_SCR_00_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_00_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_F_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR3_SHIFT)
#define GPIO_F_SCR_00_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_00_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_F_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR2_SHIFT)
#define GPIO_F_SCR_00_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_00_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_F_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR1_SHIFT)
#define GPIO_F_SCR_00_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_00_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_F_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR0_SHIFT)
#define GPIO_F_SCR_00_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_00_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_F_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G7W_SHIFT)
#define GPIO_F_SCR_00_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_00_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_F_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G6W_SHIFT)
#define GPIO_F_SCR_00_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_00_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_F_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G5W_SHIFT)
#define GPIO_F_SCR_00_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_00_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_F_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G4W_SHIFT)
#define GPIO_F_SCR_00_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_00_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_F_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G3W_SHIFT)
#define GPIO_F_SCR_00_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_00_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_F_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G2W_SHIFT)
#define GPIO_F_SCR_00_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_00_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_F_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G1W_SHIFT)
#define GPIO_F_SCR_00_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_00_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_F_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G0W_SHIFT)
#define GPIO_F_SCR_00_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_00_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_F_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G7R_SHIFT)
#define GPIO_F_SCR_00_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_00_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_F_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G6R_SHIFT)
#define GPIO_F_SCR_00_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_00_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G5R_SHIFT)
#define GPIO_F_SCR_00_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_00_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_F_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G4R_SHIFT)
#define GPIO_F_SCR_00_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_00_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_F_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G3R_SHIFT)
#define GPIO_F_SCR_00_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_00_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_F_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G2R_SHIFT)
#define GPIO_F_SCR_00_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_00_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_F_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G1R_SHIFT)
#define GPIO_F_SCR_00_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_00_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G0R_SHIFT)
#define GPIO_F_SCR_00_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_00_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_F_VM_01_0
#define GPIO_F_VM_01_0                  MK_ADDR_CONST(0x5108)
#define GPIO_F_VM_01_0_SECURE                   0x0
#define GPIO_F_VM_01_0_DUAL                     0x0
#define GPIO_F_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_01_0_WORD_COUNT                       0x1
#define GPIO_F_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM1_SHIFT)
#define GPIO_F_VM_01_0_VM1_RANGE                        1:0
#define GPIO_F_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_F_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_VM_01_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_F_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM2_SHIFT)
#define GPIO_F_VM_01_0_VM2_RANGE                        3:2
#define GPIO_F_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_F_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_F_VM_01_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_F_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM3_SHIFT)
#define GPIO_F_VM_01_0_VM3_RANGE                        5:4
#define GPIO_F_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_F_VM_01_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_F_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM4_SHIFT)
#define GPIO_F_VM_01_0_VM4_RANGE                        7:6
#define GPIO_F_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_F_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_F_VM_01_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_F_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM5_SHIFT)
#define GPIO_F_VM_01_0_VM5_RANGE                        9:8
#define GPIO_F_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_F_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_F_VM_01_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_F_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM6_SHIFT)
#define GPIO_F_VM_01_0_VM6_RANGE                        11:10
#define GPIO_F_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_F_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_F_VM_01_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_F_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM7_SHIFT)
#define GPIO_F_VM_01_0_VM7_RANGE                        13:12
#define GPIO_F_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_F_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_F_VM_01_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_F_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM8_SHIFT)
#define GPIO_F_VM_01_0_VM8_RANGE                        15:14
#define GPIO_F_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_F_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_F_VM_01_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_01_0
#define GPIO_F_SCR_01_0                 MK_ADDR_CONST(0x510c)
#define GPIO_F_SCR_01_0_SECURE                  0x0
#define GPIO_F_SCR_01_0_DUAL                    0x0
#define GPIO_F_SCR_01_0_SCR                     0
#define GPIO_F_SCR_01_0_SCRREG                  0
#define GPIO_F_SCR_01_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_F_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_01_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_01_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_F_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_01_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_01_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_F_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_01_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_01_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_F_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_01_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_01_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_F_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_F_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_F_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_F_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR7_SHIFT)
#define GPIO_F_SCR_01_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_01_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_F_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR6_SHIFT)
#define GPIO_F_SCR_01_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_01_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_F_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR5_SHIFT)
#define GPIO_F_SCR_01_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_01_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_F_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR4_SHIFT)
#define GPIO_F_SCR_01_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_01_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_F_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR3_SHIFT)
#define GPIO_F_SCR_01_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_01_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_F_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR2_SHIFT)
#define GPIO_F_SCR_01_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_01_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_F_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR1_SHIFT)
#define GPIO_F_SCR_01_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_01_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_F_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR0_SHIFT)
#define GPIO_F_SCR_01_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_01_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_F_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G7W_SHIFT)
#define GPIO_F_SCR_01_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_01_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_F_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G6W_SHIFT)
#define GPIO_F_SCR_01_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_01_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_F_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G5W_SHIFT)
#define GPIO_F_SCR_01_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_01_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_F_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G4W_SHIFT)
#define GPIO_F_SCR_01_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_01_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_F_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G3W_SHIFT)
#define GPIO_F_SCR_01_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_01_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_F_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G2W_SHIFT)
#define GPIO_F_SCR_01_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_01_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_F_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G1W_SHIFT)
#define GPIO_F_SCR_01_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_01_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_F_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G0W_SHIFT)
#define GPIO_F_SCR_01_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_01_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_F_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G7R_SHIFT)
#define GPIO_F_SCR_01_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_01_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_F_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G6R_SHIFT)
#define GPIO_F_SCR_01_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_01_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G5R_SHIFT)
#define GPIO_F_SCR_01_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_01_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_F_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G4R_SHIFT)
#define GPIO_F_SCR_01_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_01_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_F_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G3R_SHIFT)
#define GPIO_F_SCR_01_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_01_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_F_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G2R_SHIFT)
#define GPIO_F_SCR_01_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_01_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_F_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G1R_SHIFT)
#define GPIO_F_SCR_01_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_01_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G0R_SHIFT)
#define GPIO_F_SCR_01_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_01_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_F_VM_02_0
#define GPIO_F_VM_02_0                  MK_ADDR_CONST(0x5110)
#define GPIO_F_VM_02_0_SECURE                   0x0
#define GPIO_F_VM_02_0_DUAL                     0x0
#define GPIO_F_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_02_0_WORD_COUNT                       0x1
#define GPIO_F_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM1_SHIFT)
#define GPIO_F_VM_02_0_VM1_RANGE                        1:0
#define GPIO_F_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_F_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_VM_02_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_F_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM2_SHIFT)
#define GPIO_F_VM_02_0_VM2_RANGE                        3:2
#define GPIO_F_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_F_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_F_VM_02_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_F_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM3_SHIFT)
#define GPIO_F_VM_02_0_VM3_RANGE                        5:4
#define GPIO_F_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_F_VM_02_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_F_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM4_SHIFT)
#define GPIO_F_VM_02_0_VM4_RANGE                        7:6
#define GPIO_F_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_F_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_F_VM_02_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_F_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM5_SHIFT)
#define GPIO_F_VM_02_0_VM5_RANGE                        9:8
#define GPIO_F_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_F_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_F_VM_02_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_F_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM6_SHIFT)
#define GPIO_F_VM_02_0_VM6_RANGE                        11:10
#define GPIO_F_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_F_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_F_VM_02_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_F_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM7_SHIFT)
#define GPIO_F_VM_02_0_VM7_RANGE                        13:12
#define GPIO_F_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_F_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_F_VM_02_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_F_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM8_SHIFT)
#define GPIO_F_VM_02_0_VM8_RANGE                        15:14
#define GPIO_F_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_F_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_F_VM_02_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_02_0
#define GPIO_F_SCR_02_0                 MK_ADDR_CONST(0x5114)
#define GPIO_F_SCR_02_0_SECURE                  0x0
#define GPIO_F_SCR_02_0_DUAL                    0x0
#define GPIO_F_SCR_02_0_SCR                     0
#define GPIO_F_SCR_02_0_SCRREG                  0
#define GPIO_F_SCR_02_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_F_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_02_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_02_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_F_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_02_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_02_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_F_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_02_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_02_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_F_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_02_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_02_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_F_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_F_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_F_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_F_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR7_SHIFT)
#define GPIO_F_SCR_02_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_02_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_F_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR6_SHIFT)
#define GPIO_F_SCR_02_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_02_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_F_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR5_SHIFT)
#define GPIO_F_SCR_02_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_02_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_F_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR4_SHIFT)
#define GPIO_F_SCR_02_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_02_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_F_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR3_SHIFT)
#define GPIO_F_SCR_02_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_02_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_F_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR2_SHIFT)
#define GPIO_F_SCR_02_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_02_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_F_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR1_SHIFT)
#define GPIO_F_SCR_02_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_02_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_F_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR0_SHIFT)
#define GPIO_F_SCR_02_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_02_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_F_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G7W_SHIFT)
#define GPIO_F_SCR_02_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_02_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_F_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G6W_SHIFT)
#define GPIO_F_SCR_02_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_02_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_F_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G5W_SHIFT)
#define GPIO_F_SCR_02_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_02_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_F_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G4W_SHIFT)
#define GPIO_F_SCR_02_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_02_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_F_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G3W_SHIFT)
#define GPIO_F_SCR_02_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_02_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_F_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G2W_SHIFT)
#define GPIO_F_SCR_02_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_02_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_F_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G1W_SHIFT)
#define GPIO_F_SCR_02_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_02_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_F_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G0W_SHIFT)
#define GPIO_F_SCR_02_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_02_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_F_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G7R_SHIFT)
#define GPIO_F_SCR_02_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_02_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_F_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G6R_SHIFT)
#define GPIO_F_SCR_02_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_02_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G5R_SHIFT)
#define GPIO_F_SCR_02_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_02_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_F_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G4R_SHIFT)
#define GPIO_F_SCR_02_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_02_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_F_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G3R_SHIFT)
#define GPIO_F_SCR_02_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_02_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_F_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G2R_SHIFT)
#define GPIO_F_SCR_02_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_02_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_F_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G1R_SHIFT)
#define GPIO_F_SCR_02_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_02_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G0R_SHIFT)
#define GPIO_F_SCR_02_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_02_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_F_VM_03_0
#define GPIO_F_VM_03_0                  MK_ADDR_CONST(0x5118)
#define GPIO_F_VM_03_0_SECURE                   0x0
#define GPIO_F_VM_03_0_DUAL                     0x0
#define GPIO_F_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_03_0_WORD_COUNT                       0x1
#define GPIO_F_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM1_SHIFT)
#define GPIO_F_VM_03_0_VM1_RANGE                        1:0
#define GPIO_F_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_F_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_VM_03_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_F_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM2_SHIFT)
#define GPIO_F_VM_03_0_VM2_RANGE                        3:2
#define GPIO_F_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_F_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_F_VM_03_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_F_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM3_SHIFT)
#define GPIO_F_VM_03_0_VM3_RANGE                        5:4
#define GPIO_F_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_F_VM_03_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_F_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM4_SHIFT)
#define GPIO_F_VM_03_0_VM4_RANGE                        7:6
#define GPIO_F_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_F_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_F_VM_03_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_F_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM5_SHIFT)
#define GPIO_F_VM_03_0_VM5_RANGE                        9:8
#define GPIO_F_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_F_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_F_VM_03_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_F_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM6_SHIFT)
#define GPIO_F_VM_03_0_VM6_RANGE                        11:10
#define GPIO_F_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_F_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_F_VM_03_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_F_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM7_SHIFT)
#define GPIO_F_VM_03_0_VM7_RANGE                        13:12
#define GPIO_F_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_F_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_F_VM_03_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_F_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM8_SHIFT)
#define GPIO_F_VM_03_0_VM8_RANGE                        15:14
#define GPIO_F_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_F_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_F_VM_03_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_03_0
#define GPIO_F_SCR_03_0                 MK_ADDR_CONST(0x511c)
#define GPIO_F_SCR_03_0_SECURE                  0x0
#define GPIO_F_SCR_03_0_DUAL                    0x0
#define GPIO_F_SCR_03_0_SCR                     0
#define GPIO_F_SCR_03_0_SCRREG                  0
#define GPIO_F_SCR_03_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_F_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_03_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_03_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_F_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_03_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_03_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_F_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_03_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_03_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_F_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_03_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_03_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_F_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_F_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_F_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_F_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR7_SHIFT)
#define GPIO_F_SCR_03_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_03_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_F_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR6_SHIFT)
#define GPIO_F_SCR_03_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_03_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_F_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR5_SHIFT)
#define GPIO_F_SCR_03_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_03_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_F_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR4_SHIFT)
#define GPIO_F_SCR_03_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_03_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_F_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR3_SHIFT)
#define GPIO_F_SCR_03_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_03_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_F_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR2_SHIFT)
#define GPIO_F_SCR_03_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_03_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_F_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR1_SHIFT)
#define GPIO_F_SCR_03_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_03_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_F_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR0_SHIFT)
#define GPIO_F_SCR_03_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_03_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_F_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G7W_SHIFT)
#define GPIO_F_SCR_03_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_03_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_F_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G6W_SHIFT)
#define GPIO_F_SCR_03_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_03_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_F_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G5W_SHIFT)
#define GPIO_F_SCR_03_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_03_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_F_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G4W_SHIFT)
#define GPIO_F_SCR_03_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_03_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_F_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G3W_SHIFT)
#define GPIO_F_SCR_03_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_03_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_F_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G2W_SHIFT)
#define GPIO_F_SCR_03_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_03_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_F_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G1W_SHIFT)
#define GPIO_F_SCR_03_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_03_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_F_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G0W_SHIFT)
#define GPIO_F_SCR_03_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_03_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_F_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G7R_SHIFT)
#define GPIO_F_SCR_03_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_03_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_F_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G6R_SHIFT)
#define GPIO_F_SCR_03_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_03_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G5R_SHIFT)
#define GPIO_F_SCR_03_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_03_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_F_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G4R_SHIFT)
#define GPIO_F_SCR_03_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_03_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_F_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G3R_SHIFT)
#define GPIO_F_SCR_03_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_03_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_F_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G2R_SHIFT)
#define GPIO_F_SCR_03_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_03_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_F_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G1R_SHIFT)
#define GPIO_F_SCR_03_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_03_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G0R_SHIFT)
#define GPIO_F_SCR_03_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_03_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_F_VM_04_0
#define GPIO_F_VM_04_0                  MK_ADDR_CONST(0x5120)
#define GPIO_F_VM_04_0_SECURE                   0x0
#define GPIO_F_VM_04_0_DUAL                     0x0
#define GPIO_F_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_04_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_04_0_WORD_COUNT                       0x1
#define GPIO_F_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM1_SHIFT)
#define GPIO_F_VM_04_0_VM1_RANGE                        1:0
#define GPIO_F_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_F_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_VM_04_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_F_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM2_SHIFT)
#define GPIO_F_VM_04_0_VM2_RANGE                        3:2
#define GPIO_F_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_F_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_F_VM_04_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_F_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM3_SHIFT)
#define GPIO_F_VM_04_0_VM3_RANGE                        5:4
#define GPIO_F_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_F_VM_04_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_F_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM4_SHIFT)
#define GPIO_F_VM_04_0_VM4_RANGE                        7:6
#define GPIO_F_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_F_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_F_VM_04_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_F_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM5_SHIFT)
#define GPIO_F_VM_04_0_VM5_RANGE                        9:8
#define GPIO_F_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_F_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_F_VM_04_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_F_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM6_SHIFT)
#define GPIO_F_VM_04_0_VM6_RANGE                        11:10
#define GPIO_F_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_F_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_F_VM_04_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_F_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM7_SHIFT)
#define GPIO_F_VM_04_0_VM7_RANGE                        13:12
#define GPIO_F_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_F_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_F_VM_04_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_F_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM8_SHIFT)
#define GPIO_F_VM_04_0_VM8_RANGE                        15:14
#define GPIO_F_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_F_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_F_VM_04_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_04_0
#define GPIO_F_SCR_04_0                 MK_ADDR_CONST(0x5124)
#define GPIO_F_SCR_04_0_SECURE                  0x0
#define GPIO_F_SCR_04_0_DUAL                    0x0
#define GPIO_F_SCR_04_0_SCR                     0
#define GPIO_F_SCR_04_0_SCRREG                  0
#define GPIO_F_SCR_04_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_F_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_04_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_04_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_F_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_04_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_04_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_F_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_04_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_04_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_F_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_04_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_04_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_F_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_F_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_F_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_F_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR7_SHIFT)
#define GPIO_F_SCR_04_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_04_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_F_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR6_SHIFT)
#define GPIO_F_SCR_04_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_04_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_F_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR5_SHIFT)
#define GPIO_F_SCR_04_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_04_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_F_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR4_SHIFT)
#define GPIO_F_SCR_04_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_04_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_F_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR3_SHIFT)
#define GPIO_F_SCR_04_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_04_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_F_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR2_SHIFT)
#define GPIO_F_SCR_04_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_04_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_F_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR1_SHIFT)
#define GPIO_F_SCR_04_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_04_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_F_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR0_SHIFT)
#define GPIO_F_SCR_04_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_04_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_F_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G7W_SHIFT)
#define GPIO_F_SCR_04_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_04_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_F_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G6W_SHIFT)
#define GPIO_F_SCR_04_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_04_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_F_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G5W_SHIFT)
#define GPIO_F_SCR_04_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_04_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_F_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G4W_SHIFT)
#define GPIO_F_SCR_04_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_04_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_F_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G3W_SHIFT)
#define GPIO_F_SCR_04_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_04_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_F_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G2W_SHIFT)
#define GPIO_F_SCR_04_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_04_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_F_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G1W_SHIFT)
#define GPIO_F_SCR_04_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_04_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_F_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G0W_SHIFT)
#define GPIO_F_SCR_04_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_04_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_F_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G7R_SHIFT)
#define GPIO_F_SCR_04_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_04_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_F_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G6R_SHIFT)
#define GPIO_F_SCR_04_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_04_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G5R_SHIFT)
#define GPIO_F_SCR_04_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_04_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_F_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G4R_SHIFT)
#define GPIO_F_SCR_04_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_04_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_F_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G3R_SHIFT)
#define GPIO_F_SCR_04_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_04_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_F_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G2R_SHIFT)
#define GPIO_F_SCR_04_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_04_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_F_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G1R_SHIFT)
#define GPIO_F_SCR_04_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_04_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G0R_SHIFT)
#define GPIO_F_SCR_04_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_04_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_F_VM_05_0
#define GPIO_F_VM_05_0                  MK_ADDR_CONST(0x5128)
#define GPIO_F_VM_05_0_SECURE                   0x0
#define GPIO_F_VM_05_0_DUAL                     0x0
#define GPIO_F_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_05_0_SCRREG                   GPIO_CTL5_VM_SCR_0
#define GPIO_F_VM_05_0_WORD_COUNT                       0x1
#define GPIO_F_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
#define GPIO_F_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM1_SHIFT)
#define GPIO_F_VM_05_0_VM1_RANGE                        1:0
#define GPIO_F_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
#define GPIO_F_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_VM_05_0_VM1_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
#define GPIO_F_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM2_SHIFT)
#define GPIO_F_VM_05_0_VM2_RANGE                        3:2
#define GPIO_F_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
#define GPIO_F_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
#define GPIO_F_VM_05_0_VM2_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
#define GPIO_F_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM3_SHIFT)
#define GPIO_F_VM_05_0_VM3_RANGE                        5:4
#define GPIO_F_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
#define GPIO_F_VM_05_0_VM3_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
#define GPIO_F_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM4_SHIFT)
#define GPIO_F_VM_05_0_VM4_RANGE                        7:6
#define GPIO_F_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
#define GPIO_F_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
#define GPIO_F_VM_05_0_VM4_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
#define GPIO_F_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM5_SHIFT)
#define GPIO_F_VM_05_0_VM5_RANGE                        9:8
#define GPIO_F_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
#define GPIO_F_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
#define GPIO_F_VM_05_0_VM5_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
#define GPIO_F_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM6_SHIFT)
#define GPIO_F_VM_05_0_VM6_RANGE                        11:10
#define GPIO_F_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
#define GPIO_F_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
#define GPIO_F_VM_05_0_VM6_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
#define GPIO_F_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM7_SHIFT)
#define GPIO_F_VM_05_0_VM7_RANGE                        13:12
#define GPIO_F_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
#define GPIO_F_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
#define GPIO_F_VM_05_0_VM7_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_F_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
#define GPIO_F_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM8_SHIFT)
#define GPIO_F_VM_05_0_VM8_RANGE                        15:14
#define GPIO_F_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
#define GPIO_F_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
#define GPIO_F_VM_05_0_VM8_WOFFSET                      0x0
#define GPIO_F_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
#define GPIO_F_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_SCR_05_0
#define GPIO_F_SCR_05_0                 MK_ADDR_CONST(0x512c)
#define GPIO_F_SCR_05_0_SECURE                  0x0
#define GPIO_F_SCR_05_0_DUAL                    0x0
#define GPIO_F_SCR_05_0_SCR                     0
#define GPIO_F_SCR_05_0_SCRREG                  0
#define GPIO_F_SCR_05_0_WORD_COUNT                      0x1
#define GPIO_F_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_F_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_F_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_LCK_SHIFT)
#define GPIO_F_SCR_05_0_SEC_LCK_RANGE                   29:29
#define GPIO_F_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_F_SCR_05_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_F_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_WEN_SHIFT)
#define GPIO_F_SCR_05_0_SEC_WEN_RANGE                   28:28
#define GPIO_F_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_F_SCR_05_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_F_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_REN_SHIFT)
#define GPIO_F_SCR_05_0_SEC_REN_RANGE                   27:27
#define GPIO_F_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_F_SCR_05_0_SEC_REN_WOFFSET                 0x0
#define GPIO_F_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_F_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_05_0_SEC_OWNER_SHIFT)
#define GPIO_F_SCR_05_0_SEC_OWNER_RANGE                 26:24
#define GPIO_F_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_F_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_F_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_F_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_F_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_F_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR7_SHIFT)
#define GPIO_F_SCR_05_0_PR7_RANGE                       23:23
#define GPIO_F_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_F_SCR_05_0_PR7_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_F_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR6_SHIFT)
#define GPIO_F_SCR_05_0_PR6_RANGE                       22:22
#define GPIO_F_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_F_SCR_05_0_PR6_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_F_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR5_SHIFT)
#define GPIO_F_SCR_05_0_PR5_RANGE                       21:21
#define GPIO_F_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_F_SCR_05_0_PR5_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_F_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR4_SHIFT)
#define GPIO_F_SCR_05_0_PR4_RANGE                       20:20
#define GPIO_F_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_F_SCR_05_0_PR4_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_F_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR3_SHIFT)
#define GPIO_F_SCR_05_0_PR3_RANGE                       19:19
#define GPIO_F_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_F_SCR_05_0_PR3_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_F_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR2_SHIFT)
#define GPIO_F_SCR_05_0_PR2_RANGE                       18:18
#define GPIO_F_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_F_SCR_05_0_PR2_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_F_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR1_SHIFT)
#define GPIO_F_SCR_05_0_PR1_RANGE                       17:17
#define GPIO_F_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_F_SCR_05_0_PR1_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_F_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR0_SHIFT)
#define GPIO_F_SCR_05_0_PR0_RANGE                       16:16
#define GPIO_F_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_F_SCR_05_0_PR0_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_F_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G7W_SHIFT)
#define GPIO_F_SCR_05_0_G7W_RANGE                       15:15
#define GPIO_F_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_F_SCR_05_0_G7W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_F_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G6W_SHIFT)
#define GPIO_F_SCR_05_0_G6W_RANGE                       14:14
#define GPIO_F_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_F_SCR_05_0_G6W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_F_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G5W_SHIFT)
#define GPIO_F_SCR_05_0_G5W_RANGE                       13:13
#define GPIO_F_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_F_SCR_05_0_G5W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_F_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G4W_SHIFT)
#define GPIO_F_SCR_05_0_G4W_RANGE                       12:12
#define GPIO_F_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_F_SCR_05_0_G4W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_F_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G3W_SHIFT)
#define GPIO_F_SCR_05_0_G3W_RANGE                       11:11
#define GPIO_F_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_F_SCR_05_0_G3W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_F_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G2W_SHIFT)
#define GPIO_F_SCR_05_0_G2W_RANGE                       10:10
#define GPIO_F_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_F_SCR_05_0_G2W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_F_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G1W_SHIFT)
#define GPIO_F_SCR_05_0_G1W_RANGE                       9:9
#define GPIO_F_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_F_SCR_05_0_G1W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_F_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G0W_SHIFT)
#define GPIO_F_SCR_05_0_G0W_RANGE                       8:8
#define GPIO_F_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_F_SCR_05_0_G0W_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_F_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G7R_SHIFT)
#define GPIO_F_SCR_05_0_G7R_RANGE                       7:7
#define GPIO_F_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_F_SCR_05_0_G7R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_F_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G6R_SHIFT)
#define GPIO_F_SCR_05_0_G6R_RANGE                       6:6
#define GPIO_F_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_F_SCR_05_0_G6R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G5R_SHIFT)
#define GPIO_F_SCR_05_0_G5R_RANGE                       5:5
#define GPIO_F_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_SCR_05_0_G5R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_F_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G4R_SHIFT)
#define GPIO_F_SCR_05_0_G4R_RANGE                       4:4
#define GPIO_F_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_F_SCR_05_0_G4R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_F_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G3R_SHIFT)
#define GPIO_F_SCR_05_0_G3R_RANGE                       3:3
#define GPIO_F_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_F_SCR_05_0_G3R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_F_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G2R_SHIFT)
#define GPIO_F_SCR_05_0_G2R_RANGE                       2:2
#define GPIO_F_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_F_SCR_05_0_G2R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_F_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G1R_SHIFT)
#define GPIO_F_SCR_05_0_G1R_RANGE                       1:1
#define GPIO_F_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_F_SCR_05_0_G1R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_F_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G0R_SHIFT)
#define GPIO_F_SCR_05_0_G0R_RANGE                       0:0
#define GPIO_F_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_SCR_05_0_G0R_WOFFSET                     0x0
#define GPIO_F_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_F_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x5130

// Reserved address 0x5134

// Reserved address 0x5138

// Reserved address 0x513c

// Register GPIO_CTL5_VM_SCR_0
#define GPIO_CTL5_VM_SCR_0                      MK_ADDR_CONST(0x5800)
#define GPIO_CTL5_VM_SCR_0_SECURE                       0x0
#define GPIO_CTL5_VM_SCR_0_DUAL                         0x0
#define GPIO_CTL5_VM_SCR_0_SCR                  0
#define GPIO_CTL5_VM_SCR_0_SCRREG                       0
#define GPIO_CTL5_VM_SCR_0_WORD_COUNT                   0x1
#define GPIO_CTL5_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_RANGE                        29:29
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_RANGE                        28:28
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_RANGE                        27:27
#define GPIO_CTL5_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_WOFFSET                      0x0
#define GPIO_CTL5_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL5_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_RANGE                      26:24
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
#define GPIO_CTL5_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR7_RANGE                    23:23
#define GPIO_CTL5_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL5_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
#define GPIO_CTL5_VM_SCR_0_PR7_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
#define GPIO_CTL5_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR6_RANGE                    22:22
#define GPIO_CTL5_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL5_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
#define GPIO_CTL5_VM_SCR_0_PR6_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
#define GPIO_CTL5_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR5_RANGE                    21:21
#define GPIO_CTL5_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL5_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
#define GPIO_CTL5_VM_SCR_0_PR5_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
#define GPIO_CTL5_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR4_RANGE                    20:20
#define GPIO_CTL5_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL5_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
#define GPIO_CTL5_VM_SCR_0_PR4_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
#define GPIO_CTL5_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR3_RANGE                    19:19
#define GPIO_CTL5_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL5_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
#define GPIO_CTL5_VM_SCR_0_PR3_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
#define GPIO_CTL5_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR2_RANGE                    18:18
#define GPIO_CTL5_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL5_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
#define GPIO_CTL5_VM_SCR_0_PR2_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
#define GPIO_CTL5_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR1_RANGE                    17:17
#define GPIO_CTL5_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL5_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
#define GPIO_CTL5_VM_SCR_0_PR1_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
#define GPIO_CTL5_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_VM_SCR_0_PR0_RANGE                    16:16
#define GPIO_CTL5_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL5_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
#define GPIO_CTL5_VM_SCR_0_PR0_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
#define GPIO_CTL5_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G7W_RANGE                    15:15
#define GPIO_CTL5_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL5_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
#define GPIO_CTL5_VM_SCR_0_G7W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
#define GPIO_CTL5_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G6W_RANGE                    14:14
#define GPIO_CTL5_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL5_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
#define GPIO_CTL5_VM_SCR_0_G6W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
#define GPIO_CTL5_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G5W_RANGE                    13:13
#define GPIO_CTL5_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL5_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
#define GPIO_CTL5_VM_SCR_0_G5W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
#define GPIO_CTL5_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G4W_RANGE                    12:12
#define GPIO_CTL5_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL5_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
#define GPIO_CTL5_VM_SCR_0_G4W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
#define GPIO_CTL5_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G3W_RANGE                    11:11
#define GPIO_CTL5_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL5_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
#define GPIO_CTL5_VM_SCR_0_G3W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
#define GPIO_CTL5_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G2W_RANGE                    10:10
#define GPIO_CTL5_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL5_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
#define GPIO_CTL5_VM_SCR_0_G2W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
#define GPIO_CTL5_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G1W_RANGE                    9:9
#define GPIO_CTL5_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL5_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
#define GPIO_CTL5_VM_SCR_0_G1W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
#define GPIO_CTL5_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G0W_RANGE                    8:8
#define GPIO_CTL5_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL5_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
#define GPIO_CTL5_VM_SCR_0_G0W_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
#define GPIO_CTL5_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G7R_RANGE                    7:7
#define GPIO_CTL5_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL5_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
#define GPIO_CTL5_VM_SCR_0_G7R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
#define GPIO_CTL5_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G6R_RANGE                    6:6
#define GPIO_CTL5_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL5_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
#define GPIO_CTL5_VM_SCR_0_G6R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
#define GPIO_CTL5_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G5R_RANGE                    5:5
#define GPIO_CTL5_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL5_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
#define GPIO_CTL5_VM_SCR_0_G5R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
#define GPIO_CTL5_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G4R_RANGE                    4:4
#define GPIO_CTL5_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL5_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
#define GPIO_CTL5_VM_SCR_0_G4R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
#define GPIO_CTL5_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G3R_RANGE                    3:3
#define GPIO_CTL5_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL5_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
#define GPIO_CTL5_VM_SCR_0_G3R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_CTL5_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G2R_RANGE                    2:2
#define GPIO_CTL5_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL5_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
#define GPIO_CTL5_VM_SCR_0_G2R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
#define GPIO_CTL5_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G1R_RANGE                    1:1
#define GPIO_CTL5_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL5_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
#define GPIO_CTL5_VM_SCR_0_G1R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)

#define GPIO_CTL5_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_CTL5_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_VM_SCR_0_G0R_RANGE                    0:0
#define GPIO_CTL5_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL5_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
#define GPIO_CTL5_VM_SCR_0_G0R_WOFFSET                  0x0
#define GPIO_CTL5_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_CTL5_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x5804)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL5_INTERRUPT_STATUS_VM_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x5808)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SECURE                  0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_DUAL                    0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_CTL5_SCR_0
#define GPIO_CTL5_SCR_0                 MK_ADDR_CONST(0x580c)
#define GPIO_CTL5_SCR_0_SECURE                  0x0
#define GPIO_CTL5_SCR_0_DUAL                    0x0
#define GPIO_CTL5_SCR_0_SCR                     0
#define GPIO_CTL5_SCR_0_SCRREG                  0
#define GPIO_CTL5_SCR_0_WORD_COUNT                      0x1
#define GPIO_CTL5_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
#define GPIO_CTL5_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
#define GPIO_CTL5_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_LCK_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_LCK_RANGE                   29:29
#define GPIO_CTL5_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL5_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
#define GPIO_CTL5_SCR_0_SEC_LCK_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
#define GPIO_CTL5_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_WEN_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_WEN_RANGE                   28:28
#define GPIO_CTL5_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL5_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
#define GPIO_CTL5_SCR_0_SEC_WEN_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
#define GPIO_CTL5_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_REN_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_REN_RANGE                   27:27
#define GPIO_CTL5_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL5_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
#define GPIO_CTL5_SCR_0_SEC_REN_WOFFSET                 0x0
#define GPIO_CTL5_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
#define GPIO_CTL5_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL5_SCR_0_SEC_OWNER_SHIFT)
#define GPIO_CTL5_SCR_0_SEC_OWNER_RANGE                 26:24
#define GPIO_CTL5_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
#define GPIO_CTL5_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
#define GPIO_CTL5_SCR_0_SEC_OWNER_WOFFSET                       0x0
#define GPIO_CTL5_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
#define GPIO_CTL5_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
#define GPIO_CTL5_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR7_SHIFT)
#define GPIO_CTL5_SCR_0_PR7_RANGE                       23:23
#define GPIO_CTL5_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL5_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
#define GPIO_CTL5_SCR_0_PR7_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
#define GPIO_CTL5_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR6_SHIFT)
#define GPIO_CTL5_SCR_0_PR6_RANGE                       22:22
#define GPIO_CTL5_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL5_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
#define GPIO_CTL5_SCR_0_PR6_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
#define GPIO_CTL5_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR5_SHIFT)
#define GPIO_CTL5_SCR_0_PR5_RANGE                       21:21
#define GPIO_CTL5_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL5_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
#define GPIO_CTL5_SCR_0_PR5_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
#define GPIO_CTL5_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR4_SHIFT)
#define GPIO_CTL5_SCR_0_PR4_RANGE                       20:20
#define GPIO_CTL5_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL5_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
#define GPIO_CTL5_SCR_0_PR4_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
#define GPIO_CTL5_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR3_SHIFT)
#define GPIO_CTL5_SCR_0_PR3_RANGE                       19:19
#define GPIO_CTL5_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL5_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
#define GPIO_CTL5_SCR_0_PR3_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
#define GPIO_CTL5_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR2_SHIFT)
#define GPIO_CTL5_SCR_0_PR2_RANGE                       18:18
#define GPIO_CTL5_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL5_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
#define GPIO_CTL5_SCR_0_PR2_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
#define GPIO_CTL5_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR1_SHIFT)
#define GPIO_CTL5_SCR_0_PR1_RANGE                       17:17
#define GPIO_CTL5_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL5_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
#define GPIO_CTL5_SCR_0_PR1_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
#define GPIO_CTL5_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR0_SHIFT)
#define GPIO_CTL5_SCR_0_PR0_RANGE                       16:16
#define GPIO_CTL5_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL5_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
#define GPIO_CTL5_SCR_0_PR0_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
#define GPIO_CTL5_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G7W_SHIFT)
#define GPIO_CTL5_SCR_0_G7W_RANGE                       15:15
#define GPIO_CTL5_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL5_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
#define GPIO_CTL5_SCR_0_G7W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
#define GPIO_CTL5_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G6W_SHIFT)
#define GPIO_CTL5_SCR_0_G6W_RANGE                       14:14
#define GPIO_CTL5_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL5_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
#define GPIO_CTL5_SCR_0_G6W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
#define GPIO_CTL5_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G5W_SHIFT)
#define GPIO_CTL5_SCR_0_G5W_RANGE                       13:13
#define GPIO_CTL5_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL5_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
#define GPIO_CTL5_SCR_0_G5W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
#define GPIO_CTL5_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G4W_SHIFT)
#define GPIO_CTL5_SCR_0_G4W_RANGE                       12:12
#define GPIO_CTL5_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL5_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
#define GPIO_CTL5_SCR_0_G4W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
#define GPIO_CTL5_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G3W_SHIFT)
#define GPIO_CTL5_SCR_0_G3W_RANGE                       11:11
#define GPIO_CTL5_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL5_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
#define GPIO_CTL5_SCR_0_G3W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
#define GPIO_CTL5_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G2W_SHIFT)
#define GPIO_CTL5_SCR_0_G2W_RANGE                       10:10
#define GPIO_CTL5_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL5_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
#define GPIO_CTL5_SCR_0_G2W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
#define GPIO_CTL5_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G1W_SHIFT)
#define GPIO_CTL5_SCR_0_G1W_RANGE                       9:9
#define GPIO_CTL5_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL5_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
#define GPIO_CTL5_SCR_0_G1W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
#define GPIO_CTL5_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G0W_SHIFT)
#define GPIO_CTL5_SCR_0_G0W_RANGE                       8:8
#define GPIO_CTL5_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL5_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
#define GPIO_CTL5_SCR_0_G0W_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
#define GPIO_CTL5_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G7R_SHIFT)
#define GPIO_CTL5_SCR_0_G7R_RANGE                       7:7
#define GPIO_CTL5_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL5_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
#define GPIO_CTL5_SCR_0_G7R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
#define GPIO_CTL5_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G6R_SHIFT)
#define GPIO_CTL5_SCR_0_G6R_RANGE                       6:6
#define GPIO_CTL5_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL5_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
#define GPIO_CTL5_SCR_0_G6R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_CTL5_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G5R_SHIFT)
#define GPIO_CTL5_SCR_0_G5R_RANGE                       5:5
#define GPIO_CTL5_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL5_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
#define GPIO_CTL5_SCR_0_G5R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
#define GPIO_CTL5_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G4R_SHIFT)
#define GPIO_CTL5_SCR_0_G4R_RANGE                       4:4
#define GPIO_CTL5_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL5_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
#define GPIO_CTL5_SCR_0_G4R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
#define GPIO_CTL5_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G3R_SHIFT)
#define GPIO_CTL5_SCR_0_G3R_RANGE                       3:3
#define GPIO_CTL5_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL5_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
#define GPIO_CTL5_SCR_0_G3R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
#define GPIO_CTL5_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G2R_SHIFT)
#define GPIO_CTL5_SCR_0_G2R_RANGE                       2:2
#define GPIO_CTL5_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL5_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
#define GPIO_CTL5_SCR_0_G2R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
#define GPIO_CTL5_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G1R_SHIFT)
#define GPIO_CTL5_SCR_0_G1R_RANGE                       1:1
#define GPIO_CTL5_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL5_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
#define GPIO_CTL5_SCR_0_G1R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)

#define GPIO_CTL5_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_CTL5_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G0R_SHIFT)
#define GPIO_CTL5_SCR_0_G0R_RANGE                       0:0
#define GPIO_CTL5_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL5_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
#define GPIO_CTL5_SCR_0_G0R_WOFFSET                     0x0
#define GPIO_CTL5_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_CTL5_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_CTL5_ICG_EN_OVERRIDE_0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x5810)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SECURE                      0x0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_DUAL                        0x0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)


// Register GPIO_J_INT0_ROUTE_MAPPING_0
#define GPIO_J_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5814)
#define GPIO_J_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_J_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_J_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_J_INT1_ROUTE_MAPPING_0
#define GPIO_J_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5818)
#define GPIO_J_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_J_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_J_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_J_INT2_ROUTE_MAPPING_0
#define GPIO_J_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x581c)
#define GPIO_J_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_J_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_J_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_J_INT3_ROUTE_MAPPING_0
#define GPIO_J_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5820)
#define GPIO_J_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_J_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_J_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_J_INT4_ROUTE_MAPPING_0
#define GPIO_J_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5824)
#define GPIO_J_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_J_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_J_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_J_INT5_ROUTE_MAPPING_0
#define GPIO_J_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5828)
#define GPIO_J_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_J_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_J_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_J_INT6_ROUTE_MAPPING_0
#define GPIO_J_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x582c)
#define GPIO_J_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_J_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_J_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_J_INT7_ROUTE_MAPPING_0
#define GPIO_J_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5830)
#define GPIO_J_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_J_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_J_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_J_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_J_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_J_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_J_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_C_INT0_ROUTE_MAPPING_0
#define GPIO_C_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5834)
#define GPIO_C_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_C_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_C_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_C_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_C_INT1_ROUTE_MAPPING_0
#define GPIO_C_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5838)
#define GPIO_C_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_C_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_C_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_C_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_C_INT2_ROUTE_MAPPING_0
#define GPIO_C_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x583c)
#define GPIO_C_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_C_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_C_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_C_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_C_INT3_ROUTE_MAPPING_0
#define GPIO_C_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5840)
#define GPIO_C_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_C_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_C_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_C_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_C_INT4_ROUTE_MAPPING_0
#define GPIO_C_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5844)
#define GPIO_C_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_C_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_C_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_C_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_C_INT5_ROUTE_MAPPING_0
#define GPIO_C_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5848)
#define GPIO_C_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_C_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_C_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_C_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_C_INT6_ROUTE_MAPPING_0
#define GPIO_C_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x584c)
#define GPIO_C_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_C_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_C_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_C_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_C_INT7_ROUTE_MAPPING_0
#define GPIO_C_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5850)
#define GPIO_C_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_C_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_C_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_C_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_C_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_C_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_C_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_D_INT0_ROUTE_MAPPING_0
#define GPIO_D_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5854)
#define GPIO_D_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_D_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_D_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_D_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_D_INT1_ROUTE_MAPPING_0
#define GPIO_D_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5858)
#define GPIO_D_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_D_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_D_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_D_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_D_INT2_ROUTE_MAPPING_0
#define GPIO_D_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x585c)
#define GPIO_D_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_D_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_D_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_D_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_D_INT3_ROUTE_MAPPING_0
#define GPIO_D_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5860)
#define GPIO_D_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_D_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_D_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_D_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_D_INT4_ROUTE_MAPPING_0
#define GPIO_D_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5864)
#define GPIO_D_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_D_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_D_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_D_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_D_INT5_ROUTE_MAPPING_0
#define GPIO_D_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5868)
#define GPIO_D_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_D_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_D_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_D_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_D_INT6_ROUTE_MAPPING_0
#define GPIO_D_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x586c)
#define GPIO_D_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_D_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_D_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_D_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_D_INT7_ROUTE_MAPPING_0
#define GPIO_D_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5870)
#define GPIO_D_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_D_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_D_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_D_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_D_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_D_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
#define GPIO_D_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_RANGE                   3:0
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_E_INT0_ROUTE_MAPPING_0
#define GPIO_E_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5874)
#define GPIO_E_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_E_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_E_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_E_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_E_INT1_ROUTE_MAPPING_0
#define GPIO_E_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5878)
#define GPIO_E_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_E_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_E_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_E_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_E_INT2_ROUTE_MAPPING_0
#define GPIO_E_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x587c)
#define GPIO_E_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_E_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_E_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_E_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_E_INT3_ROUTE_MAPPING_0
#define GPIO_E_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5880)
#define GPIO_E_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_E_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_E_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_E_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_E_INT4_ROUTE_MAPPING_0
#define GPIO_E_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5884)
#define GPIO_E_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_E_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_E_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_E_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_E_INT5_ROUTE_MAPPING_0
#define GPIO_E_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5888)
#define GPIO_E_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_E_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_E_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_E_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_E_INT6_ROUTE_MAPPING_0
#define GPIO_E_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x588c)
#define GPIO_E_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_E_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_E_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_E_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_E_INT7_ROUTE_MAPPING_0
#define GPIO_E_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5890)
#define GPIO_E_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_E_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_E_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_E_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_E_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_E_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
#define GPIO_E_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_F_INT0_ROUTE_MAPPING_0
#define GPIO_F_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5894)
#define GPIO_F_INT0_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT0_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_F_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_F_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_F_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_F_INT1_ROUTE_MAPPING_0
#define GPIO_F_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5898)
#define GPIO_F_INT1_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT1_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_F_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_F_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_F_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_F_INT2_ROUTE_MAPPING_0
#define GPIO_F_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x589c)
#define GPIO_F_INT2_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT2_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_F_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_F_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_F_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_F_INT3_ROUTE_MAPPING_0
#define GPIO_F_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58a0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT3_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_F_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_F_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_F_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_F_INT4_ROUTE_MAPPING_0
#define GPIO_F_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58a4)
#define GPIO_F_INT4_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT4_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_F_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_F_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_F_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_F_INT5_ROUTE_MAPPING_0
#define GPIO_F_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58a8)
#define GPIO_F_INT5_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT5_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_F_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_F_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_F_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_F_INT6_ROUTE_MAPPING_0
#define GPIO_F_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58ac)
#define GPIO_F_INT6_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT6_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_F_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_F_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_F_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_F_INT7_ROUTE_MAPPING_0
#define GPIO_F_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58b0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_SECURE                      0x0
#define GPIO_F_INT7_ROUTE_MAPPING_0_DUAL                        0x0
#define GPIO_F_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
#define GPIO_F_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
#define GPIO_F_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
#define GPIO_F_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
#define GPIO_F_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_CTL5_SPARE_0
#define GPIO_CTL5_SPARE_0                       MK_ADDR_CONST(0x58b4)
#define GPIO_CTL5_SPARE_0_SECURE                        0x0
#define GPIO_CTL5_SPARE_0_DUAL                  0x0
#define GPIO_CTL5_SPARE_0_SCR                   0
#define GPIO_CTL5_SPARE_0_SCRREG                        0
#define GPIO_CTL5_SPARE_0_WORD_COUNT                    0x1
#define GPIO_CTL5_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
#define GPIO_CTL5_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL5_SPARE_0_SPARE_SHIFT)
#define GPIO_CTL5_SPARE_0_SPARE_RANGE                   15:0
#define GPIO_CTL5_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
#define GPIO_CTL5_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
#define GPIO_CTL5_SPARE_0_SPARE_WOFFSET                 0x0
#define GPIO_CTL5_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
#define GPIO_CTL5_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
#define GPIO_CTL5_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)


// Register GPIO_A_ENABLE_CONFIG_00_0
#define GPIO_A_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x10000)
#define GPIO_A_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_00_0_SCR                   GPIO_A_SCR_00_0
#define GPIO_A_ENABLE_CONFIG_00_0_SCRREG                        GPIO_A_SCR_00_0
#define GPIO_A_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_00_0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x10004)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_A_SCR_00_0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_A_SCR_00_0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_00_0
#define GPIO_A_INPUT_00_0                       MK_ADDR_CONST(0x10008)
#define GPIO_A_INPUT_00_0_SECURE                        0x0
#define GPIO_A_INPUT_00_0_DUAL                  0x0
#define GPIO_A_INPUT_00_0_SCR                   GPIO_A_SCR_00_0
#define GPIO_A_INPUT_00_0_SCRREG                        GPIO_A_SCR_00_0
#define GPIO_A_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_00_0
#define GPIO_A_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1000c)
#define GPIO_A_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_00_0_SCR                  GPIO_A_SCR_00_0
#define GPIO_A_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_A_SCR_00_0
#define GPIO_A_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_00_0
#define GPIO_A_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x10010)
#define GPIO_A_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_00_0_SCR                    GPIO_A_SCR_00_0
#define GPIO_A_OUTPUT_VALUE_00_0_SCRREG                         GPIO_A_SCR_00_0
#define GPIO_A_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_00_0
#define GPIO_A_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x10014)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_00_0_SCR                         GPIO_A_SCR_00_0
#define GPIO_A_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_A_SCR_00_0
#define GPIO_A_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x10018

// Reserved address 0x1001c

// Register GPIO_A_ENABLE_CONFIG_01_0
#define GPIO_A_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x10020)
#define GPIO_A_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_01_0_SCR                   GPIO_A_SCR_01_0
#define GPIO_A_ENABLE_CONFIG_01_0_SCRREG                        GPIO_A_SCR_01_0
#define GPIO_A_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_01_0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x10024)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_A_SCR_01_0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_A_SCR_01_0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_01_0
#define GPIO_A_INPUT_01_0                       MK_ADDR_CONST(0x10028)
#define GPIO_A_INPUT_01_0_SECURE                        0x0
#define GPIO_A_INPUT_01_0_DUAL                  0x0
#define GPIO_A_INPUT_01_0_SCR                   GPIO_A_SCR_01_0
#define GPIO_A_INPUT_01_0_SCRREG                        GPIO_A_SCR_01_0
#define GPIO_A_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_01_0
#define GPIO_A_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1002c)
#define GPIO_A_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_01_0_SCR                  GPIO_A_SCR_01_0
#define GPIO_A_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_A_SCR_01_0
#define GPIO_A_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_01_0
#define GPIO_A_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x10030)
#define GPIO_A_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_01_0_SCR                    GPIO_A_SCR_01_0
#define GPIO_A_OUTPUT_VALUE_01_0_SCRREG                         GPIO_A_SCR_01_0
#define GPIO_A_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_01_0
#define GPIO_A_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x10034)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_01_0_SCR                         GPIO_A_SCR_01_0
#define GPIO_A_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_A_SCR_01_0
#define GPIO_A_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x10038

// Reserved address 0x1003c

// Register GPIO_A_ENABLE_CONFIG_02_0
#define GPIO_A_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x10040)
#define GPIO_A_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_02_0_SCR                   GPIO_A_SCR_02_0
#define GPIO_A_ENABLE_CONFIG_02_0_SCRREG                        GPIO_A_SCR_02_0
#define GPIO_A_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_02_0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x10044)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_A_SCR_02_0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_A_SCR_02_0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_02_0
#define GPIO_A_INPUT_02_0                       MK_ADDR_CONST(0x10048)
#define GPIO_A_INPUT_02_0_SECURE                        0x0
#define GPIO_A_INPUT_02_0_DUAL                  0x0
#define GPIO_A_INPUT_02_0_SCR                   GPIO_A_SCR_02_0
#define GPIO_A_INPUT_02_0_SCRREG                        GPIO_A_SCR_02_0
#define GPIO_A_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_02_0
#define GPIO_A_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1004c)
#define GPIO_A_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_02_0_SCR                  GPIO_A_SCR_02_0
#define GPIO_A_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_A_SCR_02_0
#define GPIO_A_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_02_0
#define GPIO_A_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x10050)
#define GPIO_A_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_02_0_SCR                    GPIO_A_SCR_02_0
#define GPIO_A_OUTPUT_VALUE_02_0_SCRREG                         GPIO_A_SCR_02_0
#define GPIO_A_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_02_0
#define GPIO_A_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x10054)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_02_0_SCR                         GPIO_A_SCR_02_0
#define GPIO_A_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_A_SCR_02_0
#define GPIO_A_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x10058

// Reserved address 0x1005c

// Register GPIO_A_ENABLE_CONFIG_03_0
#define GPIO_A_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x10060)
#define GPIO_A_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_03_0_SCR                   GPIO_A_SCR_03_0
#define GPIO_A_ENABLE_CONFIG_03_0_SCRREG                        GPIO_A_SCR_03_0
#define GPIO_A_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_03_0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x10064)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_A_SCR_03_0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_A_SCR_03_0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_03_0
#define GPIO_A_INPUT_03_0                       MK_ADDR_CONST(0x10068)
#define GPIO_A_INPUT_03_0_SECURE                        0x0
#define GPIO_A_INPUT_03_0_DUAL                  0x0
#define GPIO_A_INPUT_03_0_SCR                   GPIO_A_SCR_03_0
#define GPIO_A_INPUT_03_0_SCRREG                        GPIO_A_SCR_03_0
#define GPIO_A_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_03_0
#define GPIO_A_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1006c)
#define GPIO_A_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_03_0_SCR                  GPIO_A_SCR_03_0
#define GPIO_A_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_A_SCR_03_0
#define GPIO_A_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_03_0
#define GPIO_A_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x10070)
#define GPIO_A_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_03_0_SCR                    GPIO_A_SCR_03_0
#define GPIO_A_OUTPUT_VALUE_03_0_SCRREG                         GPIO_A_SCR_03_0
#define GPIO_A_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_03_0
#define GPIO_A_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x10074)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_03_0_SCR                         GPIO_A_SCR_03_0
#define GPIO_A_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_A_SCR_03_0
#define GPIO_A_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x10078

// Reserved address 0x1007c

// Register GPIO_A_ENABLE_CONFIG_04_0
#define GPIO_A_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x10080)
#define GPIO_A_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_04_0_SCR                   GPIO_A_SCR_04_0
#define GPIO_A_ENABLE_CONFIG_04_0_SCRREG                        GPIO_A_SCR_04_0
#define GPIO_A_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_04_0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x10084)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_A_SCR_04_0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_A_SCR_04_0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_04_0
#define GPIO_A_INPUT_04_0                       MK_ADDR_CONST(0x10088)
#define GPIO_A_INPUT_04_0_SECURE                        0x0
#define GPIO_A_INPUT_04_0_DUAL                  0x0
#define GPIO_A_INPUT_04_0_SCR                   GPIO_A_SCR_04_0
#define GPIO_A_INPUT_04_0_SCRREG                        GPIO_A_SCR_04_0
#define GPIO_A_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_04_0
#define GPIO_A_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1008c)
#define GPIO_A_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_04_0_SCR                  GPIO_A_SCR_04_0
#define GPIO_A_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_A_SCR_04_0
#define GPIO_A_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_04_0
#define GPIO_A_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x10090)
#define GPIO_A_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_04_0_SCR                    GPIO_A_SCR_04_0
#define GPIO_A_OUTPUT_VALUE_04_0_SCRREG                         GPIO_A_SCR_04_0
#define GPIO_A_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_04_0
#define GPIO_A_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x10094)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_04_0_SCR                         GPIO_A_SCR_04_0
#define GPIO_A_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_A_SCR_04_0
#define GPIO_A_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x10098

// Reserved address 0x1009c

// Register GPIO_A_ENABLE_CONFIG_05_0
#define GPIO_A_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x100a0)
#define GPIO_A_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_05_0_SCR                   GPIO_A_SCR_05_0
#define GPIO_A_ENABLE_CONFIG_05_0_SCRREG                        GPIO_A_SCR_05_0
#define GPIO_A_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_05_0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x100a4)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_A_SCR_05_0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_A_SCR_05_0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_05_0
#define GPIO_A_INPUT_05_0                       MK_ADDR_CONST(0x100a8)
#define GPIO_A_INPUT_05_0_SECURE                        0x0
#define GPIO_A_INPUT_05_0_DUAL                  0x0
#define GPIO_A_INPUT_05_0_SCR                   GPIO_A_SCR_05_0
#define GPIO_A_INPUT_05_0_SCRREG                        GPIO_A_SCR_05_0
#define GPIO_A_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_05_0
#define GPIO_A_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x100ac)
#define GPIO_A_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_05_0_SCR                  GPIO_A_SCR_05_0
#define GPIO_A_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_A_SCR_05_0
#define GPIO_A_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_05_0
#define GPIO_A_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x100b0)
#define GPIO_A_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_05_0_SCR                    GPIO_A_SCR_05_0
#define GPIO_A_OUTPUT_VALUE_05_0_SCRREG                         GPIO_A_SCR_05_0
#define GPIO_A_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_05_0
#define GPIO_A_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x100b4)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_05_0_SCR                         GPIO_A_SCR_05_0
#define GPIO_A_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_A_SCR_05_0
#define GPIO_A_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x100b8

// Reserved address 0x100bc

// Register GPIO_A_ENABLE_CONFIG_06_0
#define GPIO_A_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x100c0)
#define GPIO_A_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_06_0_SCR                   GPIO_A_SCR_06_0
#define GPIO_A_ENABLE_CONFIG_06_0_SCRREG                        GPIO_A_SCR_06_0
#define GPIO_A_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_06_0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x100c4)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_A_SCR_06_0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_A_SCR_06_0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_06_0
#define GPIO_A_INPUT_06_0                       MK_ADDR_CONST(0x100c8)
#define GPIO_A_INPUT_06_0_SECURE                        0x0
#define GPIO_A_INPUT_06_0_DUAL                  0x0
#define GPIO_A_INPUT_06_0_SCR                   GPIO_A_SCR_06_0
#define GPIO_A_INPUT_06_0_SCRREG                        GPIO_A_SCR_06_0
#define GPIO_A_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_06_0
#define GPIO_A_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x100cc)
#define GPIO_A_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_06_0_SCR                  GPIO_A_SCR_06_0
#define GPIO_A_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_A_SCR_06_0
#define GPIO_A_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_06_0
#define GPIO_A_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x100d0)
#define GPIO_A_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_06_0_SCR                    GPIO_A_SCR_06_0
#define GPIO_A_OUTPUT_VALUE_06_0_SCRREG                         GPIO_A_SCR_06_0
#define GPIO_A_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_06_0
#define GPIO_A_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x100d4)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_06_0_SCR                         GPIO_A_SCR_06_0
#define GPIO_A_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_A_SCR_06_0
#define GPIO_A_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x100d8

// Reserved address 0x100dc

// Register GPIO_A_ENABLE_CONFIG_07_0
#define GPIO_A_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x100e0)
#define GPIO_A_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_A_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_A_ENABLE_CONFIG_07_0_SCR                   GPIO_A_SCR_07_0
#define GPIO_A_ENABLE_CONFIG_07_0_SCRREG                        GPIO_A_SCR_07_0
#define GPIO_A_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_A_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_A_DEBOUNCE_THRESHOLD_07_0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x100e4)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_A_SCR_07_0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_A_SCR_07_0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_INPUT_07_0
#define GPIO_A_INPUT_07_0                       MK_ADDR_CONST(0x100e8)
#define GPIO_A_INPUT_07_0_SECURE                        0x0
#define GPIO_A_INPUT_07_0_DUAL                  0x0
#define GPIO_A_INPUT_07_0_SCR                   GPIO_A_SCR_07_0
#define GPIO_A_INPUT_07_0_SCRREG                        GPIO_A_SCR_07_0
#define GPIO_A_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_A_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_A_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_A_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_A_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_A_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_A_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_A_OUTPUT_CONTROL_07_0
#define GPIO_A_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x100ec)
#define GPIO_A_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_A_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_A_OUTPUT_CONTROL_07_0_SCR                  GPIO_A_SCR_07_0
#define GPIO_A_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_A_SCR_07_0
#define GPIO_A_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_A_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_A_OUTPUT_VALUE_07_0
#define GPIO_A_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x100f0)
#define GPIO_A_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_A_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_A_OUTPUT_VALUE_07_0_SCR                    GPIO_A_SCR_07_0
#define GPIO_A_OUTPUT_VALUE_07_0_SCRREG                         GPIO_A_SCR_07_0
#define GPIO_A_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_A_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_CLEAR_07_0
#define GPIO_A_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x100f4)
#define GPIO_A_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_A_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_A_INTERRUPT_CLEAR_07_0_SCR                         GPIO_A_SCR_07_0
#define GPIO_A_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_A_SCR_07_0
#define GPIO_A_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_A_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x100f8

// Reserved address 0x100fc

// Register GPIO_A_INTERRUPT_STATUS_G0_0
#define GPIO_A_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x10100)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_A_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G1_0
#define GPIO_A_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x10104)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_A_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G2_0
#define GPIO_A_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x10108)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_A_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G3_0
#define GPIO_A_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1010c)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_A_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G4_0
#define GPIO_A_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x10110)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_A_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G5_0
#define GPIO_A_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x10114)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_A_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G6_0
#define GPIO_A_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x10118)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_A_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_A_INTERRUPT_STATUS_G7_0
#define GPIO_A_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1011c)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_A_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_A_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_A_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_A_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_A_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x10120

// Reserved address 0x10124

// Reserved address 0x10128

// Reserved address 0x1012c

// Reserved address 0x10130

// Reserved address 0x10134

// Reserved address 0x10138

// Reserved address 0x1013c

// Reserved address 0x10140

// Reserved address 0x10144

// Reserved address 0x10148

// Reserved address 0x1014c

// Reserved address 0x10150

// Reserved address 0x10154

// Reserved address 0x10158

// Reserved address 0x1015c

// Reserved address 0x10160

// Reserved address 0x10164

// Reserved address 0x10168

// Reserved address 0x1016c

// Reserved address 0x10170

// Reserved address 0x10174

// Reserved address 0x10178

// Reserved address 0x1017c

// Reserved address 0x10180

// Reserved address 0x10184

// Reserved address 0x10188

// Reserved address 0x1018c

// Reserved address 0x10190

// Reserved address 0x10194

// Reserved address 0x10198

// Reserved address 0x1019c

// Reserved address 0x101a0

// Reserved address 0x101a4

// Reserved address 0x101a8

// Reserved address 0x101ac

// Reserved address 0x101b0

// Reserved address 0x101b4

// Reserved address 0x101b8

// Reserved address 0x101bc

// Reserved address 0x101c0

// Reserved address 0x101c4

// Reserved address 0x101c8

// Reserved address 0x101cc

// Reserved address 0x101d0

// Reserved address 0x101d4

// Reserved address 0x101d8

// Reserved address 0x101dc

// Reserved address 0x101e0

// Reserved address 0x101e4

// Reserved address 0x101e8

// Reserved address 0x101ec

// Reserved address 0x101f0

// Reserved address 0x101f4

// Reserved address 0x101f8

// Reserved address 0x101fc

// Register GPIO_AC_ENABLE_CONFIG_00_0
#define GPIO_AC_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x10200)
#define GPIO_AC_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_SCR                  GPIO_AC_SCR_00_0
#define GPIO_AC_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AC_SCR_00_0
#define GPIO_AC_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_AC_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AC_DEBOUNCE_THRESHOLD_00_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x10204)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AC_SCR_00_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AC_SCR_00_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_INPUT_00_0
#define GPIO_AC_INPUT_00_0                      MK_ADDR_CONST(0x10208)
#define GPIO_AC_INPUT_00_0_SECURE                       0x0
#define GPIO_AC_INPUT_00_0_DUAL                         0x0
#define GPIO_AC_INPUT_00_0_SCR                  GPIO_AC_SCR_00_0
#define GPIO_AC_INPUT_00_0_SCRREG                       GPIO_AC_SCR_00_0
#define GPIO_AC_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_AC_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_AC_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_AC_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AC_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_OUTPUT_CONTROL_00_0
#define GPIO_AC_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1020c)
#define GPIO_AC_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_AC_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_AC_OUTPUT_CONTROL_00_0_SCR                         GPIO_AC_SCR_00_0
#define GPIO_AC_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AC_SCR_00_0
#define GPIO_AC_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_AC_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AC_OUTPUT_VALUE_00_0
#define GPIO_AC_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x10210)
#define GPIO_AC_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_AC_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_AC_OUTPUT_VALUE_00_0_SCR                   GPIO_AC_SCR_00_0
#define GPIO_AC_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AC_SCR_00_0
#define GPIO_AC_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_AC_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_CLEAR_00_0
#define GPIO_AC_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x10214)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_AC_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AC_SCR_00_0
#define GPIO_AC_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AC_SCR_00_0
#define GPIO_AC_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_AC_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10218

// Reserved address 0x1021c

// Register GPIO_AC_ENABLE_CONFIG_01_0
#define GPIO_AC_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x10220)
#define GPIO_AC_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_SCR                  GPIO_AC_SCR_01_0
#define GPIO_AC_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AC_SCR_01_0
#define GPIO_AC_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_AC_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AC_DEBOUNCE_THRESHOLD_01_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x10224)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AC_SCR_01_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AC_SCR_01_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_INPUT_01_0
#define GPIO_AC_INPUT_01_0                      MK_ADDR_CONST(0x10228)
#define GPIO_AC_INPUT_01_0_SECURE                       0x0
#define GPIO_AC_INPUT_01_0_DUAL                         0x0
#define GPIO_AC_INPUT_01_0_SCR                  GPIO_AC_SCR_01_0
#define GPIO_AC_INPUT_01_0_SCRREG                       GPIO_AC_SCR_01_0
#define GPIO_AC_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_AC_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_AC_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_AC_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AC_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_OUTPUT_CONTROL_01_0
#define GPIO_AC_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1022c)
#define GPIO_AC_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_AC_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_AC_OUTPUT_CONTROL_01_0_SCR                         GPIO_AC_SCR_01_0
#define GPIO_AC_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AC_SCR_01_0
#define GPIO_AC_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_AC_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AC_OUTPUT_VALUE_01_0
#define GPIO_AC_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x10230)
#define GPIO_AC_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_AC_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_AC_OUTPUT_VALUE_01_0_SCR                   GPIO_AC_SCR_01_0
#define GPIO_AC_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AC_SCR_01_0
#define GPIO_AC_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_AC_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_CLEAR_01_0
#define GPIO_AC_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x10234)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_AC_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AC_SCR_01_0
#define GPIO_AC_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AC_SCR_01_0
#define GPIO_AC_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_AC_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10238

// Reserved address 0x1023c

// Register GPIO_AC_ENABLE_CONFIG_02_0
#define GPIO_AC_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x10240)
#define GPIO_AC_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_SCR                  GPIO_AC_SCR_02_0
#define GPIO_AC_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AC_SCR_02_0
#define GPIO_AC_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_AC_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AC_DEBOUNCE_THRESHOLD_02_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x10244)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AC_SCR_02_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AC_SCR_02_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_INPUT_02_0
#define GPIO_AC_INPUT_02_0                      MK_ADDR_CONST(0x10248)
#define GPIO_AC_INPUT_02_0_SECURE                       0x0
#define GPIO_AC_INPUT_02_0_DUAL                         0x0
#define GPIO_AC_INPUT_02_0_SCR                  GPIO_AC_SCR_02_0
#define GPIO_AC_INPUT_02_0_SCRREG                       GPIO_AC_SCR_02_0
#define GPIO_AC_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_AC_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_AC_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_AC_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AC_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_OUTPUT_CONTROL_02_0
#define GPIO_AC_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1024c)
#define GPIO_AC_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_AC_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_AC_OUTPUT_CONTROL_02_0_SCR                         GPIO_AC_SCR_02_0
#define GPIO_AC_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AC_SCR_02_0
#define GPIO_AC_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_AC_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AC_OUTPUT_VALUE_02_0
#define GPIO_AC_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x10250)
#define GPIO_AC_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_AC_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_AC_OUTPUT_VALUE_02_0_SCR                   GPIO_AC_SCR_02_0
#define GPIO_AC_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AC_SCR_02_0
#define GPIO_AC_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_AC_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_CLEAR_02_0
#define GPIO_AC_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x10254)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_AC_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AC_SCR_02_0
#define GPIO_AC_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AC_SCR_02_0
#define GPIO_AC_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_AC_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10258

// Reserved address 0x1025c

// Register GPIO_AC_ENABLE_CONFIG_03_0
#define GPIO_AC_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x10260)
#define GPIO_AC_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_DUAL                         0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_SCR                  GPIO_AC_SCR_03_0
#define GPIO_AC_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AC_SCR_03_0
#define GPIO_AC_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_AC_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AC_DEBOUNCE_THRESHOLD_03_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x10264)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AC_SCR_03_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AC_SCR_03_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_INPUT_03_0
#define GPIO_AC_INPUT_03_0                      MK_ADDR_CONST(0x10268)
#define GPIO_AC_INPUT_03_0_SECURE                       0x0
#define GPIO_AC_INPUT_03_0_DUAL                         0x0
#define GPIO_AC_INPUT_03_0_SCR                  GPIO_AC_SCR_03_0
#define GPIO_AC_INPUT_03_0_SCRREG                       GPIO_AC_SCR_03_0
#define GPIO_AC_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_AC_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_AC_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_AC_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AC_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_OUTPUT_CONTROL_03_0
#define GPIO_AC_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1026c)
#define GPIO_AC_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_AC_OUTPUT_CONTROL_03_0_DUAL                        0x0
#define GPIO_AC_OUTPUT_CONTROL_03_0_SCR                         GPIO_AC_SCR_03_0
#define GPIO_AC_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AC_SCR_03_0
#define GPIO_AC_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_AC_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AC_OUTPUT_VALUE_03_0
#define GPIO_AC_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x10270)
#define GPIO_AC_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_AC_OUTPUT_VALUE_03_0_DUAL                  0x0
#define GPIO_AC_OUTPUT_VALUE_03_0_SCR                   GPIO_AC_SCR_03_0
#define GPIO_AC_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AC_SCR_03_0
#define GPIO_AC_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_AC_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_CLEAR_03_0
#define GPIO_AC_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x10274)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_AC_INTERRUPT_CLEAR_03_0_DUAL                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AC_SCR_03_0
#define GPIO_AC_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AC_SCR_03_0
#define GPIO_AC_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_AC_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10278

// Reserved address 0x1027c

// Register GPIO_AC_ENABLE_CONFIG_04_0
#define GPIO_AC_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x10280)
#define GPIO_AC_ENABLE_CONFIG_04_0_SECURE                       0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_DUAL                         0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_SCR                  GPIO_AC_SCR_04_0
#define GPIO_AC_ENABLE_CONFIG_04_0_SCRREG                       GPIO_AC_SCR_04_0
#define GPIO_AC_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
#define GPIO_AC_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AC_DEBOUNCE_THRESHOLD_04_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x10284)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_AC_SCR_04_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_AC_SCR_04_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_INPUT_04_0
#define GPIO_AC_INPUT_04_0                      MK_ADDR_CONST(0x10288)
#define GPIO_AC_INPUT_04_0_SECURE                       0x0
#define GPIO_AC_INPUT_04_0_DUAL                         0x0
#define GPIO_AC_INPUT_04_0_SCR                  GPIO_AC_SCR_04_0
#define GPIO_AC_INPUT_04_0_SCRREG                       GPIO_AC_SCR_04_0
#define GPIO_AC_INPUT_04_0_WORD_COUNT                   0x1
#define GPIO_AC_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_AC_INPUT_04_0_GPIO_IN_RANGE                        0:0
#define GPIO_AC_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AC_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_OUTPUT_CONTROL_04_0
#define GPIO_AC_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x1028c)
#define GPIO_AC_OUTPUT_CONTROL_04_0_SECURE                      0x0
#define GPIO_AC_OUTPUT_CONTROL_04_0_DUAL                        0x0
#define GPIO_AC_OUTPUT_CONTROL_04_0_SCR                         GPIO_AC_SCR_04_0
#define GPIO_AC_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_AC_SCR_04_0
#define GPIO_AC_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
#define GPIO_AC_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AC_OUTPUT_VALUE_04_0
#define GPIO_AC_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x10290)
#define GPIO_AC_OUTPUT_VALUE_04_0_SECURE                        0x0
#define GPIO_AC_OUTPUT_VALUE_04_0_DUAL                  0x0
#define GPIO_AC_OUTPUT_VALUE_04_0_SCR                   GPIO_AC_SCR_04_0
#define GPIO_AC_OUTPUT_VALUE_04_0_SCRREG                        GPIO_AC_SCR_04_0
#define GPIO_AC_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
#define GPIO_AC_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_CLEAR_04_0
#define GPIO_AC_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x10294)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_SECURE                     0x0
#define GPIO_AC_INTERRUPT_CLEAR_04_0_DUAL                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_04_0_SCR                        GPIO_AC_SCR_04_0
#define GPIO_AC_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_AC_SCR_04_0
#define GPIO_AC_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
#define GPIO_AC_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10298

// Reserved address 0x1029c

// Register GPIO_AC_ENABLE_CONFIG_05_0
#define GPIO_AC_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x102a0)
#define GPIO_AC_ENABLE_CONFIG_05_0_SECURE                       0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_DUAL                         0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_SCR                  GPIO_AC_SCR_05_0
#define GPIO_AC_ENABLE_CONFIG_05_0_SCRREG                       GPIO_AC_SCR_05_0
#define GPIO_AC_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
#define GPIO_AC_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AC_DEBOUNCE_THRESHOLD_05_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x102a4)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_AC_SCR_05_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_AC_SCR_05_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_INPUT_05_0
#define GPIO_AC_INPUT_05_0                      MK_ADDR_CONST(0x102a8)
#define GPIO_AC_INPUT_05_0_SECURE                       0x0
#define GPIO_AC_INPUT_05_0_DUAL                         0x0
#define GPIO_AC_INPUT_05_0_SCR                  GPIO_AC_SCR_05_0
#define GPIO_AC_INPUT_05_0_SCRREG                       GPIO_AC_SCR_05_0
#define GPIO_AC_INPUT_05_0_WORD_COUNT                   0x1
#define GPIO_AC_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_AC_INPUT_05_0_GPIO_IN_RANGE                        0:0
#define GPIO_AC_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AC_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_OUTPUT_CONTROL_05_0
#define GPIO_AC_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x102ac)
#define GPIO_AC_OUTPUT_CONTROL_05_0_SECURE                      0x0
#define GPIO_AC_OUTPUT_CONTROL_05_0_DUAL                        0x0
#define GPIO_AC_OUTPUT_CONTROL_05_0_SCR                         GPIO_AC_SCR_05_0
#define GPIO_AC_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_AC_SCR_05_0
#define GPIO_AC_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
#define GPIO_AC_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AC_OUTPUT_VALUE_05_0
#define GPIO_AC_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x102b0)
#define GPIO_AC_OUTPUT_VALUE_05_0_SECURE                        0x0
#define GPIO_AC_OUTPUT_VALUE_05_0_DUAL                  0x0
#define GPIO_AC_OUTPUT_VALUE_05_0_SCR                   GPIO_AC_SCR_05_0
#define GPIO_AC_OUTPUT_VALUE_05_0_SCRREG                        GPIO_AC_SCR_05_0
#define GPIO_AC_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
#define GPIO_AC_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_CLEAR_05_0
#define GPIO_AC_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x102b4)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_SECURE                     0x0
#define GPIO_AC_INTERRUPT_CLEAR_05_0_DUAL                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_05_0_SCR                        GPIO_AC_SCR_05_0
#define GPIO_AC_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_AC_SCR_05_0
#define GPIO_AC_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
#define GPIO_AC_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x102b8

// Reserved address 0x102bc

// Register GPIO_AC_ENABLE_CONFIG_06_0
#define GPIO_AC_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x102c0)
#define GPIO_AC_ENABLE_CONFIG_06_0_SECURE                       0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_DUAL                         0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_SCR                  GPIO_AC_SCR_06_0
#define GPIO_AC_ENABLE_CONFIG_06_0_SCRREG                       GPIO_AC_SCR_06_0
#define GPIO_AC_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
#define GPIO_AC_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AC_DEBOUNCE_THRESHOLD_06_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x102c4)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_AC_SCR_06_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_AC_SCR_06_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_INPUT_06_0
#define GPIO_AC_INPUT_06_0                      MK_ADDR_CONST(0x102c8)
#define GPIO_AC_INPUT_06_0_SECURE                       0x0
#define GPIO_AC_INPUT_06_0_DUAL                         0x0
#define GPIO_AC_INPUT_06_0_SCR                  GPIO_AC_SCR_06_0
#define GPIO_AC_INPUT_06_0_SCRREG                       GPIO_AC_SCR_06_0
#define GPIO_AC_INPUT_06_0_WORD_COUNT                   0x1
#define GPIO_AC_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_AC_INPUT_06_0_GPIO_IN_RANGE                        0:0
#define GPIO_AC_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AC_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_OUTPUT_CONTROL_06_0
#define GPIO_AC_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x102cc)
#define GPIO_AC_OUTPUT_CONTROL_06_0_SECURE                      0x0
#define GPIO_AC_OUTPUT_CONTROL_06_0_DUAL                        0x0
#define GPIO_AC_OUTPUT_CONTROL_06_0_SCR                         GPIO_AC_SCR_06_0
#define GPIO_AC_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_AC_SCR_06_0
#define GPIO_AC_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
#define GPIO_AC_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AC_OUTPUT_VALUE_06_0
#define GPIO_AC_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x102d0)
#define GPIO_AC_OUTPUT_VALUE_06_0_SECURE                        0x0
#define GPIO_AC_OUTPUT_VALUE_06_0_DUAL                  0x0
#define GPIO_AC_OUTPUT_VALUE_06_0_SCR                   GPIO_AC_SCR_06_0
#define GPIO_AC_OUTPUT_VALUE_06_0_SCRREG                        GPIO_AC_SCR_06_0
#define GPIO_AC_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
#define GPIO_AC_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_CLEAR_06_0
#define GPIO_AC_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x102d4)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_SECURE                     0x0
#define GPIO_AC_INTERRUPT_CLEAR_06_0_DUAL                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_06_0_SCR                        GPIO_AC_SCR_06_0
#define GPIO_AC_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_AC_SCR_06_0
#define GPIO_AC_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
#define GPIO_AC_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x102d8

// Reserved address 0x102dc

// Register GPIO_AC_ENABLE_CONFIG_07_0
#define GPIO_AC_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x102e0)
#define GPIO_AC_ENABLE_CONFIG_07_0_SECURE                       0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_DUAL                         0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_SCR                  GPIO_AC_SCR_07_0
#define GPIO_AC_ENABLE_CONFIG_07_0_SCRREG                       GPIO_AC_SCR_07_0
#define GPIO_AC_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
#define GPIO_AC_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AC_DEBOUNCE_THRESHOLD_07_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x102e4)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_AC_SCR_07_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_AC_SCR_07_0
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_INPUT_07_0
#define GPIO_AC_INPUT_07_0                      MK_ADDR_CONST(0x102e8)
#define GPIO_AC_INPUT_07_0_SECURE                       0x0
#define GPIO_AC_INPUT_07_0_DUAL                         0x0
#define GPIO_AC_INPUT_07_0_SCR                  GPIO_AC_SCR_07_0
#define GPIO_AC_INPUT_07_0_SCRREG                       GPIO_AC_SCR_07_0
#define GPIO_AC_INPUT_07_0_WORD_COUNT                   0x1
#define GPIO_AC_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_AC_INPUT_07_0_GPIO_IN_RANGE                        0:0
#define GPIO_AC_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AC_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AC_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AC_OUTPUT_CONTROL_07_0
#define GPIO_AC_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x102ec)
#define GPIO_AC_OUTPUT_CONTROL_07_0_SECURE                      0x0
#define GPIO_AC_OUTPUT_CONTROL_07_0_DUAL                        0x0
#define GPIO_AC_OUTPUT_CONTROL_07_0_SCR                         GPIO_AC_SCR_07_0
#define GPIO_AC_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_AC_SCR_07_0
#define GPIO_AC_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
#define GPIO_AC_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AC_OUTPUT_VALUE_07_0
#define GPIO_AC_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x102f0)
#define GPIO_AC_OUTPUT_VALUE_07_0_SECURE                        0x0
#define GPIO_AC_OUTPUT_VALUE_07_0_DUAL                  0x0
#define GPIO_AC_OUTPUT_VALUE_07_0_SCR                   GPIO_AC_SCR_07_0
#define GPIO_AC_OUTPUT_VALUE_07_0_SCRREG                        GPIO_AC_SCR_07_0
#define GPIO_AC_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
#define GPIO_AC_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_CLEAR_07_0
#define GPIO_AC_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x102f4)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_SECURE                     0x0
#define GPIO_AC_INTERRUPT_CLEAR_07_0_DUAL                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_07_0_SCR                        GPIO_AC_SCR_07_0
#define GPIO_AC_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_AC_SCR_07_0
#define GPIO_AC_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
#define GPIO_AC_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x102f8

// Reserved address 0x102fc

// Register GPIO_AC_INTERRUPT_STATUS_G0_0
#define GPIO_AC_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x10300)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_AC_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_AC_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_AC_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_AC_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_AC_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_STATUS_G1_0
#define GPIO_AC_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x10304)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_AC_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_AC_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_AC_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_AC_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_AC_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_STATUS_G2_0
#define GPIO_AC_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x10308)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_AC_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_AC_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_AC_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_AC_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_AC_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_STATUS_G3_0
#define GPIO_AC_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1030c)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_AC_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_AC_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_AC_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_AC_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_AC_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_STATUS_G4_0
#define GPIO_AC_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x10310)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_AC_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_AC_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_AC_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_AC_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_AC_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_STATUS_G5_0
#define GPIO_AC_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x10314)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_AC_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_AC_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_AC_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_AC_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_AC_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_STATUS_G6_0
#define GPIO_AC_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x10318)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_AC_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_AC_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_AC_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_AC_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_AC_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AC_INTERRUPT_STATUS_G7_0
#define GPIO_AC_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1031c)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_AC_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_AC_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_AC_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_AC_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_AC_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x10320

// Reserved address 0x10324

// Reserved address 0x10328

// Reserved address 0x1032c

// Reserved address 0x10330

// Reserved address 0x10334

// Reserved address 0x10338

// Reserved address 0x1033c

// Reserved address 0x10340

// Reserved address 0x10344

// Reserved address 0x10348

// Reserved address 0x1034c

// Reserved address 0x10350

// Reserved address 0x10354

// Reserved address 0x10358

// Reserved address 0x1035c

// Reserved address 0x10360

// Reserved address 0x10364

// Reserved address 0x10368

// Reserved address 0x1036c

// Reserved address 0x10370

// Reserved address 0x10374

// Reserved address 0x10378

// Reserved address 0x1037c

// Reserved address 0x10380

// Reserved address 0x10384

// Reserved address 0x10388

// Reserved address 0x1038c

// Reserved address 0x10390

// Reserved address 0x10394

// Reserved address 0x10398

// Reserved address 0x1039c

// Reserved address 0x103a0

// Reserved address 0x103a4

// Reserved address 0x103a8

// Reserved address 0x103ac

// Reserved address 0x103b0

// Reserved address 0x103b4

// Reserved address 0x103b8

// Reserved address 0x103bc

// Reserved address 0x103c0

// Reserved address 0x103c4

// Reserved address 0x103c8

// Reserved address 0x103cc

// Reserved address 0x103d0

// Reserved address 0x103d4

// Reserved address 0x103d8

// Reserved address 0x103dc

// Reserved address 0x103e0

// Reserved address 0x103e4

// Reserved address 0x103e8

// Reserved address 0x103ec

// Reserved address 0x103f0

// Reserved address 0x103f4

// Reserved address 0x103f8

// Reserved address 0x103fc

// Register GPIO_AD_ENABLE_CONFIG_00_0
#define GPIO_AD_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x10400)
#define GPIO_AD_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_SCR                  GPIO_AD_SCR_00_0
#define GPIO_AD_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AD_SCR_00_0
#define GPIO_AD_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_AD_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AD_DEBOUNCE_THRESHOLD_00_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x10404)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AD_SCR_00_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AD_SCR_00_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AD_INPUT_00_0
#define GPIO_AD_INPUT_00_0                      MK_ADDR_CONST(0x10408)
#define GPIO_AD_INPUT_00_0_SECURE                       0x0
#define GPIO_AD_INPUT_00_0_DUAL                         0x0
#define GPIO_AD_INPUT_00_0_SCR                  GPIO_AD_SCR_00_0
#define GPIO_AD_INPUT_00_0_SCRREG                       GPIO_AD_SCR_00_0
#define GPIO_AD_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_AD_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AD_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_AD_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_AD_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AD_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AD_OUTPUT_CONTROL_00_0
#define GPIO_AD_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1040c)
#define GPIO_AD_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_AD_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_AD_OUTPUT_CONTROL_00_0_SCR                         GPIO_AD_SCR_00_0
#define GPIO_AD_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AD_SCR_00_0
#define GPIO_AD_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_AD_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AD_OUTPUT_VALUE_00_0
#define GPIO_AD_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x10410)
#define GPIO_AD_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_AD_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_AD_OUTPUT_VALUE_00_0_SCR                   GPIO_AD_SCR_00_0
#define GPIO_AD_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AD_SCR_00_0
#define GPIO_AD_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_AD_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_CLEAR_00_0
#define GPIO_AD_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x10414)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_AD_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_AD_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AD_SCR_00_0
#define GPIO_AD_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AD_SCR_00_0
#define GPIO_AD_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_AD_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10418

// Reserved address 0x1041c

// Register GPIO_AD_ENABLE_CONFIG_01_0
#define GPIO_AD_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x10420)
#define GPIO_AD_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_SCR                  GPIO_AD_SCR_01_0
#define GPIO_AD_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AD_SCR_01_0
#define GPIO_AD_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_AD_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AD_DEBOUNCE_THRESHOLD_01_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x10424)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AD_SCR_01_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AD_SCR_01_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AD_INPUT_01_0
#define GPIO_AD_INPUT_01_0                      MK_ADDR_CONST(0x10428)
#define GPIO_AD_INPUT_01_0_SECURE                       0x0
#define GPIO_AD_INPUT_01_0_DUAL                         0x0
#define GPIO_AD_INPUT_01_0_SCR                  GPIO_AD_SCR_01_0
#define GPIO_AD_INPUT_01_0_SCRREG                       GPIO_AD_SCR_01_0
#define GPIO_AD_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_AD_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AD_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_AD_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_AD_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AD_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AD_OUTPUT_CONTROL_01_0
#define GPIO_AD_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1042c)
#define GPIO_AD_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_AD_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_AD_OUTPUT_CONTROL_01_0_SCR                         GPIO_AD_SCR_01_0
#define GPIO_AD_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AD_SCR_01_0
#define GPIO_AD_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_AD_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AD_OUTPUT_VALUE_01_0
#define GPIO_AD_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x10430)
#define GPIO_AD_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_AD_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_AD_OUTPUT_VALUE_01_0_SCR                   GPIO_AD_SCR_01_0
#define GPIO_AD_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AD_SCR_01_0
#define GPIO_AD_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_AD_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_CLEAR_01_0
#define GPIO_AD_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x10434)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_AD_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_AD_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AD_SCR_01_0
#define GPIO_AD_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AD_SCR_01_0
#define GPIO_AD_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_AD_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10438

// Reserved address 0x1043c

// Register GPIO_AD_ENABLE_CONFIG_02_0
#define GPIO_AD_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x10440)
#define GPIO_AD_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_SCR                  GPIO_AD_SCR_02_0
#define GPIO_AD_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AD_SCR_02_0
#define GPIO_AD_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_AD_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AD_DEBOUNCE_THRESHOLD_02_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x10444)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AD_SCR_02_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AD_SCR_02_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AD_INPUT_02_0
#define GPIO_AD_INPUT_02_0                      MK_ADDR_CONST(0x10448)
#define GPIO_AD_INPUT_02_0_SECURE                       0x0
#define GPIO_AD_INPUT_02_0_DUAL                         0x0
#define GPIO_AD_INPUT_02_0_SCR                  GPIO_AD_SCR_02_0
#define GPIO_AD_INPUT_02_0_SCRREG                       GPIO_AD_SCR_02_0
#define GPIO_AD_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_AD_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AD_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_AD_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_AD_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AD_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AD_OUTPUT_CONTROL_02_0
#define GPIO_AD_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1044c)
#define GPIO_AD_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_AD_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_AD_OUTPUT_CONTROL_02_0_SCR                         GPIO_AD_SCR_02_0
#define GPIO_AD_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AD_SCR_02_0
#define GPIO_AD_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_AD_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AD_OUTPUT_VALUE_02_0
#define GPIO_AD_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x10450)
#define GPIO_AD_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_AD_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_AD_OUTPUT_VALUE_02_0_SCR                   GPIO_AD_SCR_02_0
#define GPIO_AD_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AD_SCR_02_0
#define GPIO_AD_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_AD_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_CLEAR_02_0
#define GPIO_AD_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x10454)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_AD_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_AD_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AD_SCR_02_0
#define GPIO_AD_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AD_SCR_02_0
#define GPIO_AD_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_AD_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10458

// Reserved address 0x1045c

// Register GPIO_AD_ENABLE_CONFIG_03_0
#define GPIO_AD_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x10460)
#define GPIO_AD_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_DUAL                         0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_SCR                  GPIO_AD_SCR_03_0
#define GPIO_AD_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AD_SCR_03_0
#define GPIO_AD_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_AD_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AD_DEBOUNCE_THRESHOLD_03_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x10464)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AD_SCR_03_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AD_SCR_03_0
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AD_INPUT_03_0
#define GPIO_AD_INPUT_03_0                      MK_ADDR_CONST(0x10468)
#define GPIO_AD_INPUT_03_0_SECURE                       0x0
#define GPIO_AD_INPUT_03_0_DUAL                         0x0
#define GPIO_AD_INPUT_03_0_SCR                  GPIO_AD_SCR_03_0
#define GPIO_AD_INPUT_03_0_SCRREG                       GPIO_AD_SCR_03_0
#define GPIO_AD_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_AD_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AD_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_AD_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_AD_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AD_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AD_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AD_OUTPUT_CONTROL_03_0
#define GPIO_AD_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1046c)
#define GPIO_AD_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_AD_OUTPUT_CONTROL_03_0_DUAL                        0x0
#define GPIO_AD_OUTPUT_CONTROL_03_0_SCR                         GPIO_AD_SCR_03_0
#define GPIO_AD_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AD_SCR_03_0
#define GPIO_AD_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_AD_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AD_OUTPUT_VALUE_03_0
#define GPIO_AD_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x10470)
#define GPIO_AD_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_AD_OUTPUT_VALUE_03_0_DUAL                  0x0
#define GPIO_AD_OUTPUT_VALUE_03_0_SCR                   GPIO_AD_SCR_03_0
#define GPIO_AD_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AD_SCR_03_0
#define GPIO_AD_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_AD_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_CLEAR_03_0
#define GPIO_AD_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x10474)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_AD_INTERRUPT_CLEAR_03_0_DUAL                       0x0
#define GPIO_AD_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AD_SCR_03_0
#define GPIO_AD_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AD_SCR_03_0
#define GPIO_AD_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_AD_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x10478

// Reserved address 0x1047c

// Reserved address 0x10480

// Reserved address 0x10484

// Reserved address 0x10488

// Reserved address 0x1048c

// Reserved address 0x10490

// Reserved address 0x10494

// Reserved address 0x10498

// Reserved address 0x1049c

// Reserved address 0x104a0

// Reserved address 0x104a4

// Reserved address 0x104a8

// Reserved address 0x104ac

// Reserved address 0x104b0

// Reserved address 0x104b4

// Reserved address 0x104b8

// Reserved address 0x104bc

// Reserved address 0x104c0

// Reserved address 0x104c4

// Reserved address 0x104c8

// Reserved address 0x104cc

// Reserved address 0x104d0

// Reserved address 0x104d4

// Reserved address 0x104d8

// Reserved address 0x104dc

// Reserved address 0x104e0

// Reserved address 0x104e4

// Reserved address 0x104e8

// Reserved address 0x104ec

// Reserved address 0x104f0

// Reserved address 0x104f4

// Reserved address 0x104f8

// Reserved address 0x104fc

// Register GPIO_AD_INTERRUPT_STATUS_G0_0
#define GPIO_AD_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x10500)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_AD_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_AD_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_AD_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_AD_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_AD_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_STATUS_G1_0
#define GPIO_AD_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x10504)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_AD_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_AD_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_AD_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_AD_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_AD_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_STATUS_G2_0
#define GPIO_AD_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x10508)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_AD_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_AD_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_AD_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_AD_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_AD_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_STATUS_G3_0
#define GPIO_AD_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1050c)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_AD_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_AD_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_AD_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_AD_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_AD_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_STATUS_G4_0
#define GPIO_AD_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x10510)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_AD_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_AD_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_AD_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_AD_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_AD_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_STATUS_G5_0
#define GPIO_AD_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x10514)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_AD_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_AD_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_AD_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_AD_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_AD_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_STATUS_G6_0
#define GPIO_AD_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x10518)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_AD_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_AD_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_AD_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_AD_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_AD_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AD_INTERRUPT_STATUS_G7_0
#define GPIO_AD_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1051c)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_AD_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_AD_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_AD_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_AD_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_AD_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x10520

// Reserved address 0x10524

// Reserved address 0x10528

// Reserved address 0x1052c

// Reserved address 0x10530

// Reserved address 0x10534

// Reserved address 0x10538

// Reserved address 0x1053c

// Reserved address 0x10540

// Reserved address 0x10544

// Reserved address 0x10548

// Reserved address 0x1054c

// Reserved address 0x10550

// Reserved address 0x10554

// Reserved address 0x10558

// Reserved address 0x1055c

// Reserved address 0x10560

// Reserved address 0x10564

// Reserved address 0x10568

// Reserved address 0x1056c

// Reserved address 0x10570

// Reserved address 0x10574

// Reserved address 0x10578

// Reserved address 0x1057c

// Reserved address 0x10580

// Reserved address 0x10584

// Reserved address 0x10588

// Reserved address 0x1058c

// Reserved address 0x10590

// Reserved address 0x10594

// Reserved address 0x10598

// Reserved address 0x1059c

// Reserved address 0x105a0

// Reserved address 0x105a4

// Reserved address 0x105a8

// Reserved address 0x105ac

// Reserved address 0x105b0

// Reserved address 0x105b4

// Reserved address 0x105b8

// Reserved address 0x105bc

// Reserved address 0x105c0

// Reserved address 0x105c4

// Reserved address 0x105c8

// Reserved address 0x105cc

// Reserved address 0x105d0

// Reserved address 0x105d4

// Reserved address 0x105d8

// Reserved address 0x105dc

// Reserved address 0x105e0

// Reserved address 0x105e4

// Reserved address 0x105e8

// Reserved address 0x105ec

// Reserved address 0x105f0

// Reserved address 0x105f4

// Reserved address 0x105f8

// Reserved address 0x105fc

// Register GPIO_B_ENABLE_CONFIG_00_0
#define GPIO_B_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x10600)
#define GPIO_B_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_B_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_B_ENABLE_CONFIG_00_0_SCR                   GPIO_B_SCR_00_0
#define GPIO_B_ENABLE_CONFIG_00_0_SCRREG                        GPIO_B_SCR_00_0
#define GPIO_B_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_B_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_B_DEBOUNCE_THRESHOLD_00_0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x10604)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_B_SCR_00_0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_B_SCR_00_0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_B_INPUT_00_0
#define GPIO_B_INPUT_00_0                       MK_ADDR_CONST(0x10608)
#define GPIO_B_INPUT_00_0_SECURE                        0x0
#define GPIO_B_INPUT_00_0_DUAL                  0x0
#define GPIO_B_INPUT_00_0_SCR                   GPIO_B_SCR_00_0
#define GPIO_B_INPUT_00_0_SCRREG                        GPIO_B_SCR_00_0
#define GPIO_B_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_B_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_B_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_B_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_B_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_B_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_B_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_B_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_B_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_B_OUTPUT_CONTROL_00_0
#define GPIO_B_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1060c)
#define GPIO_B_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_B_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_B_OUTPUT_CONTROL_00_0_SCR                  GPIO_B_SCR_00_0
#define GPIO_B_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_B_SCR_00_0
#define GPIO_B_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_B_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_B_OUTPUT_VALUE_00_0
#define GPIO_B_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x10610)
#define GPIO_B_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_B_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_B_OUTPUT_VALUE_00_0_SCR                    GPIO_B_SCR_00_0
#define GPIO_B_OUTPUT_VALUE_00_0_SCRREG                         GPIO_B_SCR_00_0
#define GPIO_B_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_B_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_CLEAR_00_0
#define GPIO_B_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x10614)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_B_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_B_INTERRUPT_CLEAR_00_0_SCR                         GPIO_B_SCR_00_0
#define GPIO_B_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_B_SCR_00_0
#define GPIO_B_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_B_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x10618

// Reserved address 0x1061c

// Reserved address 0x10620

// Reserved address 0x10624

// Reserved address 0x10628

// Reserved address 0x1062c

// Reserved address 0x10630

// Reserved address 0x10634

// Reserved address 0x10638

// Reserved address 0x1063c

// Reserved address 0x10640

// Reserved address 0x10644

// Reserved address 0x10648

// Reserved address 0x1064c

// Reserved address 0x10650

// Reserved address 0x10654

// Reserved address 0x10658

// Reserved address 0x1065c

// Reserved address 0x10660

// Reserved address 0x10664

// Reserved address 0x10668

// Reserved address 0x1066c

// Reserved address 0x10670

// Reserved address 0x10674

// Reserved address 0x10678

// Reserved address 0x1067c

// Reserved address 0x10680

// Reserved address 0x10684

// Reserved address 0x10688

// Reserved address 0x1068c

// Reserved address 0x10690

// Reserved address 0x10694

// Reserved address 0x10698

// Reserved address 0x1069c

// Reserved address 0x106a0

// Reserved address 0x106a4

// Reserved address 0x106a8

// Reserved address 0x106ac

// Reserved address 0x106b0

// Reserved address 0x106b4

// Reserved address 0x106b8

// Reserved address 0x106bc

// Reserved address 0x106c0

// Reserved address 0x106c4

// Reserved address 0x106c8

// Reserved address 0x106cc

// Reserved address 0x106d0

// Reserved address 0x106d4

// Reserved address 0x106d8

// Reserved address 0x106dc

// Reserved address 0x106e0

// Reserved address 0x106e4

// Reserved address 0x106e8

// Reserved address 0x106ec

// Reserved address 0x106f0

// Reserved address 0x106f4

// Reserved address 0x106f8

// Reserved address 0x106fc

// Register GPIO_B_INTERRUPT_STATUS_G0_0
#define GPIO_B_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x10700)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_B_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G1_0
#define GPIO_B_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x10704)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_B_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G2_0
#define GPIO_B_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x10708)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_B_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G3_0
#define GPIO_B_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1070c)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_B_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G4_0
#define GPIO_B_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x10710)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_B_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G5_0
#define GPIO_B_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x10714)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_B_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G6_0
#define GPIO_B_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x10718)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_B_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_B_INTERRUPT_STATUS_G7_0
#define GPIO_B_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1071c)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_B_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_B_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_B_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_B_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_B_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x10720

// Reserved address 0x10724

// Reserved address 0x10728

// Reserved address 0x1072c

// Reserved address 0x10730

// Reserved address 0x10734

// Reserved address 0x10738

// Reserved address 0x1073c

// Reserved address 0x10740

// Reserved address 0x10744

// Reserved address 0x10748

// Reserved address 0x1074c

// Reserved address 0x10750

// Reserved address 0x10754

// Reserved address 0x10758

// Reserved address 0x1075c

// Reserved address 0x10760

// Reserved address 0x10764

// Reserved address 0x10768

// Reserved address 0x1076c

// Reserved address 0x10770

// Reserved address 0x10774

// Reserved address 0x10778

// Reserved address 0x1077c

// Reserved address 0x10780

// Reserved address 0x10784

// Reserved address 0x10788

// Reserved address 0x1078c

// Reserved address 0x10790

// Reserved address 0x10794

// Reserved address 0x10798

// Reserved address 0x1079c

// Reserved address 0x107a0

// Reserved address 0x107a4

// Reserved address 0x107a8

// Reserved address 0x107ac

// Reserved address 0x107b0

// Reserved address 0x107b4

// Reserved address 0x107b8

// Reserved address 0x107bc

// Reserved address 0x107c0

// Reserved address 0x107c4

// Reserved address 0x107c8

// Reserved address 0x107cc

// Reserved address 0x107d0

// Reserved address 0x107d4

// Reserved address 0x107d8

// Reserved address 0x107dc

// Reserved address 0x107e0

// Reserved address 0x107e4

// Reserved address 0x107e8

// Reserved address 0x107ec

// Reserved address 0x107f0

// Reserved address 0x107f4

// Reserved address 0x107f8

// Reserved address 0x107fc

// Register GPIO_X_ENABLE_CONFIG_00_0
#define GPIO_X_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x11000)
#define GPIO_X_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_00_0_SCR                   GPIO_X_SCR_00_0
#define GPIO_X_ENABLE_CONFIG_00_0_SCRREG                        GPIO_X_SCR_00_0
#define GPIO_X_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_00_0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x11004)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_X_SCR_00_0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_X_SCR_00_0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_00_0
#define GPIO_X_INPUT_00_0                       MK_ADDR_CONST(0x11008)
#define GPIO_X_INPUT_00_0_SECURE                        0x0
#define GPIO_X_INPUT_00_0_DUAL                  0x0
#define GPIO_X_INPUT_00_0_SCR                   GPIO_X_SCR_00_0
#define GPIO_X_INPUT_00_0_SCRREG                        GPIO_X_SCR_00_0
#define GPIO_X_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_00_0
#define GPIO_X_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1100c)
#define GPIO_X_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_00_0_SCR                  GPIO_X_SCR_00_0
#define GPIO_X_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_X_SCR_00_0
#define GPIO_X_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_00_0
#define GPIO_X_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x11010)
#define GPIO_X_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_00_0_SCR                    GPIO_X_SCR_00_0
#define GPIO_X_OUTPUT_VALUE_00_0_SCRREG                         GPIO_X_SCR_00_0
#define GPIO_X_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_00_0
#define GPIO_X_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x11014)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_00_0_SCR                         GPIO_X_SCR_00_0
#define GPIO_X_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_X_SCR_00_0
#define GPIO_X_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11018

// Reserved address 0x1101c

// Register GPIO_X_ENABLE_CONFIG_01_0
#define GPIO_X_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x11020)
#define GPIO_X_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_01_0_SCR                   GPIO_X_SCR_01_0
#define GPIO_X_ENABLE_CONFIG_01_0_SCRREG                        GPIO_X_SCR_01_0
#define GPIO_X_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_01_0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x11024)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_X_SCR_01_0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_X_SCR_01_0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_01_0
#define GPIO_X_INPUT_01_0                       MK_ADDR_CONST(0x11028)
#define GPIO_X_INPUT_01_0_SECURE                        0x0
#define GPIO_X_INPUT_01_0_DUAL                  0x0
#define GPIO_X_INPUT_01_0_SCR                   GPIO_X_SCR_01_0
#define GPIO_X_INPUT_01_0_SCRREG                        GPIO_X_SCR_01_0
#define GPIO_X_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_01_0
#define GPIO_X_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1102c)
#define GPIO_X_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_01_0_SCR                  GPIO_X_SCR_01_0
#define GPIO_X_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_X_SCR_01_0
#define GPIO_X_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_01_0
#define GPIO_X_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x11030)
#define GPIO_X_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_01_0_SCR                    GPIO_X_SCR_01_0
#define GPIO_X_OUTPUT_VALUE_01_0_SCRREG                         GPIO_X_SCR_01_0
#define GPIO_X_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_01_0
#define GPIO_X_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x11034)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_01_0_SCR                         GPIO_X_SCR_01_0
#define GPIO_X_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_X_SCR_01_0
#define GPIO_X_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11038

// Reserved address 0x1103c

// Register GPIO_X_ENABLE_CONFIG_02_0
#define GPIO_X_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x11040)
#define GPIO_X_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_02_0_SCR                   GPIO_X_SCR_02_0
#define GPIO_X_ENABLE_CONFIG_02_0_SCRREG                        GPIO_X_SCR_02_0
#define GPIO_X_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_02_0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x11044)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_X_SCR_02_0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_X_SCR_02_0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_02_0
#define GPIO_X_INPUT_02_0                       MK_ADDR_CONST(0x11048)
#define GPIO_X_INPUT_02_0_SECURE                        0x0
#define GPIO_X_INPUT_02_0_DUAL                  0x0
#define GPIO_X_INPUT_02_0_SCR                   GPIO_X_SCR_02_0
#define GPIO_X_INPUT_02_0_SCRREG                        GPIO_X_SCR_02_0
#define GPIO_X_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_02_0
#define GPIO_X_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1104c)
#define GPIO_X_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_02_0_SCR                  GPIO_X_SCR_02_0
#define GPIO_X_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_X_SCR_02_0
#define GPIO_X_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_02_0
#define GPIO_X_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x11050)
#define GPIO_X_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_02_0_SCR                    GPIO_X_SCR_02_0
#define GPIO_X_OUTPUT_VALUE_02_0_SCRREG                         GPIO_X_SCR_02_0
#define GPIO_X_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_02_0
#define GPIO_X_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x11054)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_02_0_SCR                         GPIO_X_SCR_02_0
#define GPIO_X_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_X_SCR_02_0
#define GPIO_X_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11058

// Reserved address 0x1105c

// Register GPIO_X_ENABLE_CONFIG_03_0
#define GPIO_X_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x11060)
#define GPIO_X_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_03_0_SCR                   GPIO_X_SCR_03_0
#define GPIO_X_ENABLE_CONFIG_03_0_SCRREG                        GPIO_X_SCR_03_0
#define GPIO_X_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_03_0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x11064)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_X_SCR_03_0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_X_SCR_03_0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_03_0
#define GPIO_X_INPUT_03_0                       MK_ADDR_CONST(0x11068)
#define GPIO_X_INPUT_03_0_SECURE                        0x0
#define GPIO_X_INPUT_03_0_DUAL                  0x0
#define GPIO_X_INPUT_03_0_SCR                   GPIO_X_SCR_03_0
#define GPIO_X_INPUT_03_0_SCRREG                        GPIO_X_SCR_03_0
#define GPIO_X_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_03_0
#define GPIO_X_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1106c)
#define GPIO_X_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_03_0_SCR                  GPIO_X_SCR_03_0
#define GPIO_X_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_X_SCR_03_0
#define GPIO_X_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_03_0
#define GPIO_X_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x11070)
#define GPIO_X_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_03_0_SCR                    GPIO_X_SCR_03_0
#define GPIO_X_OUTPUT_VALUE_03_0_SCRREG                         GPIO_X_SCR_03_0
#define GPIO_X_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_03_0
#define GPIO_X_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x11074)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_03_0_SCR                         GPIO_X_SCR_03_0
#define GPIO_X_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_X_SCR_03_0
#define GPIO_X_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11078

// Reserved address 0x1107c

// Register GPIO_X_ENABLE_CONFIG_04_0
#define GPIO_X_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x11080)
#define GPIO_X_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_04_0_SCR                   GPIO_X_SCR_04_0
#define GPIO_X_ENABLE_CONFIG_04_0_SCRREG                        GPIO_X_SCR_04_0
#define GPIO_X_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_04_0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x11084)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_X_SCR_04_0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_X_SCR_04_0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_04_0
#define GPIO_X_INPUT_04_0                       MK_ADDR_CONST(0x11088)
#define GPIO_X_INPUT_04_0_SECURE                        0x0
#define GPIO_X_INPUT_04_0_DUAL                  0x0
#define GPIO_X_INPUT_04_0_SCR                   GPIO_X_SCR_04_0
#define GPIO_X_INPUT_04_0_SCRREG                        GPIO_X_SCR_04_0
#define GPIO_X_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_04_0
#define GPIO_X_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1108c)
#define GPIO_X_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_04_0_SCR                  GPIO_X_SCR_04_0
#define GPIO_X_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_X_SCR_04_0
#define GPIO_X_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_04_0
#define GPIO_X_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x11090)
#define GPIO_X_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_04_0_SCR                    GPIO_X_SCR_04_0
#define GPIO_X_OUTPUT_VALUE_04_0_SCRREG                         GPIO_X_SCR_04_0
#define GPIO_X_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_04_0
#define GPIO_X_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x11094)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_04_0_SCR                         GPIO_X_SCR_04_0
#define GPIO_X_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_X_SCR_04_0
#define GPIO_X_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11098

// Reserved address 0x1109c

// Register GPIO_X_ENABLE_CONFIG_05_0
#define GPIO_X_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x110a0)
#define GPIO_X_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_05_0_SCR                   GPIO_X_SCR_05_0
#define GPIO_X_ENABLE_CONFIG_05_0_SCRREG                        GPIO_X_SCR_05_0
#define GPIO_X_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_05_0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x110a4)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_X_SCR_05_0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_X_SCR_05_0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_05_0
#define GPIO_X_INPUT_05_0                       MK_ADDR_CONST(0x110a8)
#define GPIO_X_INPUT_05_0_SECURE                        0x0
#define GPIO_X_INPUT_05_0_DUAL                  0x0
#define GPIO_X_INPUT_05_0_SCR                   GPIO_X_SCR_05_0
#define GPIO_X_INPUT_05_0_SCRREG                        GPIO_X_SCR_05_0
#define GPIO_X_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_05_0
#define GPIO_X_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x110ac)
#define GPIO_X_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_05_0_SCR                  GPIO_X_SCR_05_0
#define GPIO_X_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_X_SCR_05_0
#define GPIO_X_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_05_0
#define GPIO_X_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x110b0)
#define GPIO_X_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_05_0_SCR                    GPIO_X_SCR_05_0
#define GPIO_X_OUTPUT_VALUE_05_0_SCRREG                         GPIO_X_SCR_05_0
#define GPIO_X_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_05_0
#define GPIO_X_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x110b4)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_05_0_SCR                         GPIO_X_SCR_05_0
#define GPIO_X_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_X_SCR_05_0
#define GPIO_X_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x110b8

// Reserved address 0x110bc

// Register GPIO_X_ENABLE_CONFIG_06_0
#define GPIO_X_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x110c0)
#define GPIO_X_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_06_0_SCR                   GPIO_X_SCR_06_0
#define GPIO_X_ENABLE_CONFIG_06_0_SCRREG                        GPIO_X_SCR_06_0
#define GPIO_X_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_06_0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x110c4)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_X_SCR_06_0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_X_SCR_06_0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_06_0
#define GPIO_X_INPUT_06_0                       MK_ADDR_CONST(0x110c8)
#define GPIO_X_INPUT_06_0_SECURE                        0x0
#define GPIO_X_INPUT_06_0_DUAL                  0x0
#define GPIO_X_INPUT_06_0_SCR                   GPIO_X_SCR_06_0
#define GPIO_X_INPUT_06_0_SCRREG                        GPIO_X_SCR_06_0
#define GPIO_X_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_06_0
#define GPIO_X_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x110cc)
#define GPIO_X_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_06_0_SCR                  GPIO_X_SCR_06_0
#define GPIO_X_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_X_SCR_06_0
#define GPIO_X_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_06_0
#define GPIO_X_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x110d0)
#define GPIO_X_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_06_0_SCR                    GPIO_X_SCR_06_0
#define GPIO_X_OUTPUT_VALUE_06_0_SCRREG                         GPIO_X_SCR_06_0
#define GPIO_X_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_06_0
#define GPIO_X_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x110d4)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_06_0_SCR                         GPIO_X_SCR_06_0
#define GPIO_X_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_X_SCR_06_0
#define GPIO_X_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x110d8

// Reserved address 0x110dc

// Register GPIO_X_ENABLE_CONFIG_07_0
#define GPIO_X_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x110e0)
#define GPIO_X_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_X_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_X_ENABLE_CONFIG_07_0_SCR                   GPIO_X_SCR_07_0
#define GPIO_X_ENABLE_CONFIG_07_0_SCRREG                        GPIO_X_SCR_07_0
#define GPIO_X_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_X_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_X_DEBOUNCE_THRESHOLD_07_0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x110e4)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_X_SCR_07_0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_X_SCR_07_0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_INPUT_07_0
#define GPIO_X_INPUT_07_0                       MK_ADDR_CONST(0x110e8)
#define GPIO_X_INPUT_07_0_SECURE                        0x0
#define GPIO_X_INPUT_07_0_DUAL                  0x0
#define GPIO_X_INPUT_07_0_SCR                   GPIO_X_SCR_07_0
#define GPIO_X_INPUT_07_0_SCRREG                        GPIO_X_SCR_07_0
#define GPIO_X_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_X_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_X_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_X_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_X_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_X_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_X_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_X_OUTPUT_CONTROL_07_0
#define GPIO_X_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x110ec)
#define GPIO_X_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_X_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_X_OUTPUT_CONTROL_07_0_SCR                  GPIO_X_SCR_07_0
#define GPIO_X_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_X_SCR_07_0
#define GPIO_X_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_X_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_X_OUTPUT_VALUE_07_0
#define GPIO_X_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x110f0)
#define GPIO_X_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_X_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_X_OUTPUT_VALUE_07_0_SCR                    GPIO_X_SCR_07_0
#define GPIO_X_OUTPUT_VALUE_07_0_SCRREG                         GPIO_X_SCR_07_0
#define GPIO_X_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_X_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_CLEAR_07_0
#define GPIO_X_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x110f4)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_X_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_X_INTERRUPT_CLEAR_07_0_SCR                         GPIO_X_SCR_07_0
#define GPIO_X_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_X_SCR_07_0
#define GPIO_X_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_X_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x110f8

// Reserved address 0x110fc

// Register GPIO_X_INTERRUPT_STATUS_G0_0
#define GPIO_X_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x11100)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_X_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G1_0
#define GPIO_X_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x11104)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_X_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G2_0
#define GPIO_X_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x11108)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_X_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G3_0
#define GPIO_X_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1110c)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_X_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G4_0
#define GPIO_X_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x11110)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_X_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G5_0
#define GPIO_X_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x11114)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_X_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G6_0
#define GPIO_X_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x11118)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_X_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_X_INTERRUPT_STATUS_G7_0
#define GPIO_X_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1111c)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_X_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_X_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_X_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_X_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_X_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x11120

// Reserved address 0x11124

// Reserved address 0x11128

// Reserved address 0x1112c

// Reserved address 0x11130

// Reserved address 0x11134

// Reserved address 0x11138

// Reserved address 0x1113c

// Reserved address 0x11140

// Reserved address 0x11144

// Reserved address 0x11148

// Reserved address 0x1114c

// Reserved address 0x11150

// Reserved address 0x11154

// Reserved address 0x11158

// Reserved address 0x1115c

// Reserved address 0x11160

// Reserved address 0x11164

// Reserved address 0x11168

// Reserved address 0x1116c

// Reserved address 0x11170

// Reserved address 0x11174

// Reserved address 0x11178

// Reserved address 0x1117c

// Reserved address 0x11180

// Reserved address 0x11184

// Reserved address 0x11188

// Reserved address 0x1118c

// Reserved address 0x11190

// Reserved address 0x11194

// Reserved address 0x11198

// Reserved address 0x1119c

// Reserved address 0x111a0

// Reserved address 0x111a4

// Reserved address 0x111a8

// Reserved address 0x111ac

// Reserved address 0x111b0

// Reserved address 0x111b4

// Reserved address 0x111b8

// Reserved address 0x111bc

// Reserved address 0x111c0

// Reserved address 0x111c4

// Reserved address 0x111c8

// Reserved address 0x111cc

// Reserved address 0x111d0

// Reserved address 0x111d4

// Reserved address 0x111d8

// Reserved address 0x111dc

// Reserved address 0x111e0

// Reserved address 0x111e4

// Reserved address 0x111e8

// Reserved address 0x111ec

// Reserved address 0x111f0

// Reserved address 0x111f4

// Reserved address 0x111f8

// Reserved address 0x111fc

// Register GPIO_Y_ENABLE_CONFIG_00_0
#define GPIO_Y_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x11200)
#define GPIO_Y_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_SCR                   GPIO_Y_SCR_00_0
#define GPIO_Y_ENABLE_CONFIG_00_0_SCRREG                        GPIO_Y_SCR_00_0
#define GPIO_Y_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_00_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x11204)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Y_SCR_00_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_Y_SCR_00_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_00_0
#define GPIO_Y_INPUT_00_0                       MK_ADDR_CONST(0x11208)
#define GPIO_Y_INPUT_00_0_SECURE                        0x0
#define GPIO_Y_INPUT_00_0_DUAL                  0x0
#define GPIO_Y_INPUT_00_0_SCR                   GPIO_Y_SCR_00_0
#define GPIO_Y_INPUT_00_0_SCRREG                        GPIO_Y_SCR_00_0
#define GPIO_Y_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_00_0
#define GPIO_Y_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1120c)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_00_0_SCR                  GPIO_Y_SCR_00_0
#define GPIO_Y_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_Y_SCR_00_0
#define GPIO_Y_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_00_0
#define GPIO_Y_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x11210)
#define GPIO_Y_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_00_0_SCR                    GPIO_Y_SCR_00_0
#define GPIO_Y_OUTPUT_VALUE_00_0_SCRREG                         GPIO_Y_SCR_00_0
#define GPIO_Y_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_00_0
#define GPIO_Y_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x11214)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Y_SCR_00_0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_Y_SCR_00_0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11218

// Reserved address 0x1121c

// Register GPIO_Y_ENABLE_CONFIG_01_0
#define GPIO_Y_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x11220)
#define GPIO_Y_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_SCR                   GPIO_Y_SCR_01_0
#define GPIO_Y_ENABLE_CONFIG_01_0_SCRREG                        GPIO_Y_SCR_01_0
#define GPIO_Y_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_01_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x11224)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Y_SCR_01_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_Y_SCR_01_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_01_0
#define GPIO_Y_INPUT_01_0                       MK_ADDR_CONST(0x11228)
#define GPIO_Y_INPUT_01_0_SECURE                        0x0
#define GPIO_Y_INPUT_01_0_DUAL                  0x0
#define GPIO_Y_INPUT_01_0_SCR                   GPIO_Y_SCR_01_0
#define GPIO_Y_INPUT_01_0_SCRREG                        GPIO_Y_SCR_01_0
#define GPIO_Y_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_01_0
#define GPIO_Y_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1122c)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_01_0_SCR                  GPIO_Y_SCR_01_0
#define GPIO_Y_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_Y_SCR_01_0
#define GPIO_Y_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_01_0
#define GPIO_Y_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x11230)
#define GPIO_Y_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_01_0_SCR                    GPIO_Y_SCR_01_0
#define GPIO_Y_OUTPUT_VALUE_01_0_SCRREG                         GPIO_Y_SCR_01_0
#define GPIO_Y_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_01_0
#define GPIO_Y_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x11234)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Y_SCR_01_0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_Y_SCR_01_0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11238

// Reserved address 0x1123c

// Register GPIO_Y_ENABLE_CONFIG_02_0
#define GPIO_Y_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x11240)
#define GPIO_Y_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_SCR                   GPIO_Y_SCR_02_0
#define GPIO_Y_ENABLE_CONFIG_02_0_SCRREG                        GPIO_Y_SCR_02_0
#define GPIO_Y_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_02_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x11244)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Y_SCR_02_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_Y_SCR_02_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_02_0
#define GPIO_Y_INPUT_02_0                       MK_ADDR_CONST(0x11248)
#define GPIO_Y_INPUT_02_0_SECURE                        0x0
#define GPIO_Y_INPUT_02_0_DUAL                  0x0
#define GPIO_Y_INPUT_02_0_SCR                   GPIO_Y_SCR_02_0
#define GPIO_Y_INPUT_02_0_SCRREG                        GPIO_Y_SCR_02_0
#define GPIO_Y_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_02_0
#define GPIO_Y_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1124c)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_02_0_SCR                  GPIO_Y_SCR_02_0
#define GPIO_Y_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_Y_SCR_02_0
#define GPIO_Y_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_02_0
#define GPIO_Y_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x11250)
#define GPIO_Y_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_02_0_SCR                    GPIO_Y_SCR_02_0
#define GPIO_Y_OUTPUT_VALUE_02_0_SCRREG                         GPIO_Y_SCR_02_0
#define GPIO_Y_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_02_0
#define GPIO_Y_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x11254)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Y_SCR_02_0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_Y_SCR_02_0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11258

// Reserved address 0x1125c

// Register GPIO_Y_ENABLE_CONFIG_03_0
#define GPIO_Y_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x11260)
#define GPIO_Y_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_SCR                   GPIO_Y_SCR_03_0
#define GPIO_Y_ENABLE_CONFIG_03_0_SCRREG                        GPIO_Y_SCR_03_0
#define GPIO_Y_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_03_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x11264)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Y_SCR_03_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_Y_SCR_03_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_03_0
#define GPIO_Y_INPUT_03_0                       MK_ADDR_CONST(0x11268)
#define GPIO_Y_INPUT_03_0_SECURE                        0x0
#define GPIO_Y_INPUT_03_0_DUAL                  0x0
#define GPIO_Y_INPUT_03_0_SCR                   GPIO_Y_SCR_03_0
#define GPIO_Y_INPUT_03_0_SCRREG                        GPIO_Y_SCR_03_0
#define GPIO_Y_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_03_0
#define GPIO_Y_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1126c)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_03_0_SCR                  GPIO_Y_SCR_03_0
#define GPIO_Y_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_Y_SCR_03_0
#define GPIO_Y_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_03_0
#define GPIO_Y_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x11270)
#define GPIO_Y_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_03_0_SCR                    GPIO_Y_SCR_03_0
#define GPIO_Y_OUTPUT_VALUE_03_0_SCRREG                         GPIO_Y_SCR_03_0
#define GPIO_Y_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_03_0
#define GPIO_Y_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x11274)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Y_SCR_03_0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_Y_SCR_03_0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11278

// Reserved address 0x1127c

// Register GPIO_Y_ENABLE_CONFIG_04_0
#define GPIO_Y_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x11280)
#define GPIO_Y_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_SCR                   GPIO_Y_SCR_04_0
#define GPIO_Y_ENABLE_CONFIG_04_0_SCRREG                        GPIO_Y_SCR_04_0
#define GPIO_Y_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_04_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x11284)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Y_SCR_04_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_Y_SCR_04_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_04_0
#define GPIO_Y_INPUT_04_0                       MK_ADDR_CONST(0x11288)
#define GPIO_Y_INPUT_04_0_SECURE                        0x0
#define GPIO_Y_INPUT_04_0_DUAL                  0x0
#define GPIO_Y_INPUT_04_0_SCR                   GPIO_Y_SCR_04_0
#define GPIO_Y_INPUT_04_0_SCRREG                        GPIO_Y_SCR_04_0
#define GPIO_Y_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_04_0
#define GPIO_Y_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1128c)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_04_0_SCR                  GPIO_Y_SCR_04_0
#define GPIO_Y_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_Y_SCR_04_0
#define GPIO_Y_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_04_0
#define GPIO_Y_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x11290)
#define GPIO_Y_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_04_0_SCR                    GPIO_Y_SCR_04_0
#define GPIO_Y_OUTPUT_VALUE_04_0_SCRREG                         GPIO_Y_SCR_04_0
#define GPIO_Y_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_04_0
#define GPIO_Y_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x11294)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Y_SCR_04_0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_Y_SCR_04_0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11298

// Reserved address 0x1129c

// Register GPIO_Y_ENABLE_CONFIG_05_0
#define GPIO_Y_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x112a0)
#define GPIO_Y_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_SCR                   GPIO_Y_SCR_05_0
#define GPIO_Y_ENABLE_CONFIG_05_0_SCRREG                        GPIO_Y_SCR_05_0
#define GPIO_Y_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_05_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x112a4)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Y_SCR_05_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_Y_SCR_05_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_05_0
#define GPIO_Y_INPUT_05_0                       MK_ADDR_CONST(0x112a8)
#define GPIO_Y_INPUT_05_0_SECURE                        0x0
#define GPIO_Y_INPUT_05_0_DUAL                  0x0
#define GPIO_Y_INPUT_05_0_SCR                   GPIO_Y_SCR_05_0
#define GPIO_Y_INPUT_05_0_SCRREG                        GPIO_Y_SCR_05_0
#define GPIO_Y_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_05_0
#define GPIO_Y_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x112ac)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_05_0_SCR                  GPIO_Y_SCR_05_0
#define GPIO_Y_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_Y_SCR_05_0
#define GPIO_Y_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_05_0
#define GPIO_Y_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x112b0)
#define GPIO_Y_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_05_0_SCR                    GPIO_Y_SCR_05_0
#define GPIO_Y_OUTPUT_VALUE_05_0_SCRREG                         GPIO_Y_SCR_05_0
#define GPIO_Y_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_05_0
#define GPIO_Y_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x112b4)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Y_SCR_05_0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_Y_SCR_05_0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x112b8

// Reserved address 0x112bc

// Register GPIO_Y_ENABLE_CONFIG_06_0
#define GPIO_Y_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x112c0)
#define GPIO_Y_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_SCR                   GPIO_Y_SCR_06_0
#define GPIO_Y_ENABLE_CONFIG_06_0_SCRREG                        GPIO_Y_SCR_06_0
#define GPIO_Y_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_06_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x112c4)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Y_SCR_06_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_Y_SCR_06_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_06_0
#define GPIO_Y_INPUT_06_0                       MK_ADDR_CONST(0x112c8)
#define GPIO_Y_INPUT_06_0_SECURE                        0x0
#define GPIO_Y_INPUT_06_0_DUAL                  0x0
#define GPIO_Y_INPUT_06_0_SCR                   GPIO_Y_SCR_06_0
#define GPIO_Y_INPUT_06_0_SCRREG                        GPIO_Y_SCR_06_0
#define GPIO_Y_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_06_0
#define GPIO_Y_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x112cc)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_06_0_SCR                  GPIO_Y_SCR_06_0
#define GPIO_Y_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_Y_SCR_06_0
#define GPIO_Y_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_06_0
#define GPIO_Y_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x112d0)
#define GPIO_Y_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_06_0_SCR                    GPIO_Y_SCR_06_0
#define GPIO_Y_OUTPUT_VALUE_06_0_SCRREG                         GPIO_Y_SCR_06_0
#define GPIO_Y_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_06_0
#define GPIO_Y_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x112d4)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Y_SCR_06_0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_Y_SCR_06_0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x112d8

// Reserved address 0x112dc

// Register GPIO_Y_ENABLE_CONFIG_07_0
#define GPIO_Y_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x112e0)
#define GPIO_Y_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_SCR                   GPIO_Y_SCR_07_0
#define GPIO_Y_ENABLE_CONFIG_07_0_SCRREG                        GPIO_Y_SCR_07_0
#define GPIO_Y_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_Y_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Y_DEBOUNCE_THRESHOLD_07_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x112e4)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Y_SCR_07_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_Y_SCR_07_0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_INPUT_07_0
#define GPIO_Y_INPUT_07_0                       MK_ADDR_CONST(0x112e8)
#define GPIO_Y_INPUT_07_0_SECURE                        0x0
#define GPIO_Y_INPUT_07_0_DUAL                  0x0
#define GPIO_Y_INPUT_07_0_SCR                   GPIO_Y_SCR_07_0
#define GPIO_Y_INPUT_07_0_SCRREG                        GPIO_Y_SCR_07_0
#define GPIO_Y_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_Y_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_Y_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_Y_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Y_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Y_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Y_OUTPUT_CONTROL_07_0
#define GPIO_Y_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x112ec)
#define GPIO_Y_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_Y_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_Y_OUTPUT_CONTROL_07_0_SCR                  GPIO_Y_SCR_07_0
#define GPIO_Y_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_Y_SCR_07_0
#define GPIO_Y_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_Y_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Y_OUTPUT_VALUE_07_0
#define GPIO_Y_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x112f0)
#define GPIO_Y_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_Y_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_Y_OUTPUT_VALUE_07_0_SCR                    GPIO_Y_SCR_07_0
#define GPIO_Y_OUTPUT_VALUE_07_0_SCRREG                         GPIO_Y_SCR_07_0
#define GPIO_Y_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_Y_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_CLEAR_07_0
#define GPIO_Y_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x112f4)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Y_SCR_07_0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_Y_SCR_07_0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_Y_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x112f8

// Reserved address 0x112fc

// Register GPIO_Y_INTERRUPT_STATUS_G0_0
#define GPIO_Y_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x11300)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G1_0
#define GPIO_Y_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x11304)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G2_0
#define GPIO_Y_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x11308)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G3_0
#define GPIO_Y_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1130c)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G4_0
#define GPIO_Y_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x11310)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G5_0
#define GPIO_Y_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x11314)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G6_0
#define GPIO_Y_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x11318)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Y_INTERRUPT_STATUS_G7_0
#define GPIO_Y_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1131c)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_Y_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x11320

// Reserved address 0x11324

// Reserved address 0x11328

// Reserved address 0x1132c

// Reserved address 0x11330

// Reserved address 0x11334

// Reserved address 0x11338

// Reserved address 0x1133c

// Reserved address 0x11340

// Reserved address 0x11344

// Reserved address 0x11348

// Reserved address 0x1134c

// Reserved address 0x11350

// Reserved address 0x11354

// Reserved address 0x11358

// Reserved address 0x1135c

// Reserved address 0x11360

// Reserved address 0x11364

// Reserved address 0x11368

// Reserved address 0x1136c

// Reserved address 0x11370

// Reserved address 0x11374

// Reserved address 0x11378

// Reserved address 0x1137c

// Reserved address 0x11380

// Reserved address 0x11384

// Reserved address 0x11388

// Reserved address 0x1138c

// Reserved address 0x11390

// Reserved address 0x11394

// Reserved address 0x11398

// Reserved address 0x1139c

// Reserved address 0x113a0

// Reserved address 0x113a4

// Reserved address 0x113a8

// Reserved address 0x113ac

// Reserved address 0x113b0

// Reserved address 0x113b4

// Reserved address 0x113b8

// Reserved address 0x113bc

// Reserved address 0x113c0

// Reserved address 0x113c4

// Reserved address 0x113c8

// Reserved address 0x113cc

// Reserved address 0x113d0

// Reserved address 0x113d4

// Reserved address 0x113d8

// Reserved address 0x113dc

// Reserved address 0x113e0

// Reserved address 0x113e4

// Reserved address 0x113e8

// Reserved address 0x113ec

// Reserved address 0x113f0

// Reserved address 0x113f4

// Reserved address 0x113f8

// Reserved address 0x113fc

// Register GPIO_Z_ENABLE_CONFIG_00_0
#define GPIO_Z_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x11400)
#define GPIO_Z_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_SCR                   GPIO_Z_SCR_00_0
#define GPIO_Z_ENABLE_CONFIG_00_0_SCRREG                        GPIO_Z_SCR_00_0
#define GPIO_Z_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_00_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x11404)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Z_SCR_00_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_Z_SCR_00_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_00_0
#define GPIO_Z_INPUT_00_0                       MK_ADDR_CONST(0x11408)
#define GPIO_Z_INPUT_00_0_SECURE                        0x0
#define GPIO_Z_INPUT_00_0_DUAL                  0x0
#define GPIO_Z_INPUT_00_0_SCR                   GPIO_Z_SCR_00_0
#define GPIO_Z_INPUT_00_0_SCRREG                        GPIO_Z_SCR_00_0
#define GPIO_Z_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_00_0
#define GPIO_Z_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1140c)
#define GPIO_Z_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_00_0_SCR                  GPIO_Z_SCR_00_0
#define GPIO_Z_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_Z_SCR_00_0
#define GPIO_Z_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_00_0
#define GPIO_Z_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x11410)
#define GPIO_Z_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_00_0_SCR                    GPIO_Z_SCR_00_0
#define GPIO_Z_OUTPUT_VALUE_00_0_SCRREG                         GPIO_Z_SCR_00_0
#define GPIO_Z_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_00_0
#define GPIO_Z_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x11414)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Z_SCR_00_0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_Z_SCR_00_0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11418

// Reserved address 0x1141c

// Register GPIO_Z_ENABLE_CONFIG_01_0
#define GPIO_Z_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x11420)
#define GPIO_Z_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_SCR                   GPIO_Z_SCR_01_0
#define GPIO_Z_ENABLE_CONFIG_01_0_SCRREG                        GPIO_Z_SCR_01_0
#define GPIO_Z_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_01_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x11424)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Z_SCR_01_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_Z_SCR_01_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_01_0
#define GPIO_Z_INPUT_01_0                       MK_ADDR_CONST(0x11428)
#define GPIO_Z_INPUT_01_0_SECURE                        0x0
#define GPIO_Z_INPUT_01_0_DUAL                  0x0
#define GPIO_Z_INPUT_01_0_SCR                   GPIO_Z_SCR_01_0
#define GPIO_Z_INPUT_01_0_SCRREG                        GPIO_Z_SCR_01_0
#define GPIO_Z_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_01_0
#define GPIO_Z_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1142c)
#define GPIO_Z_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_01_0_SCR                  GPIO_Z_SCR_01_0
#define GPIO_Z_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_Z_SCR_01_0
#define GPIO_Z_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_01_0
#define GPIO_Z_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x11430)
#define GPIO_Z_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_01_0_SCR                    GPIO_Z_SCR_01_0
#define GPIO_Z_OUTPUT_VALUE_01_0_SCRREG                         GPIO_Z_SCR_01_0
#define GPIO_Z_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_01_0
#define GPIO_Z_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x11434)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Z_SCR_01_0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_Z_SCR_01_0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11438

// Reserved address 0x1143c

// Register GPIO_Z_ENABLE_CONFIG_02_0
#define GPIO_Z_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x11440)
#define GPIO_Z_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_SCR                   GPIO_Z_SCR_02_0
#define GPIO_Z_ENABLE_CONFIG_02_0_SCRREG                        GPIO_Z_SCR_02_0
#define GPIO_Z_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_02_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x11444)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Z_SCR_02_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_Z_SCR_02_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_02_0
#define GPIO_Z_INPUT_02_0                       MK_ADDR_CONST(0x11448)
#define GPIO_Z_INPUT_02_0_SECURE                        0x0
#define GPIO_Z_INPUT_02_0_DUAL                  0x0
#define GPIO_Z_INPUT_02_0_SCR                   GPIO_Z_SCR_02_0
#define GPIO_Z_INPUT_02_0_SCRREG                        GPIO_Z_SCR_02_0
#define GPIO_Z_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_02_0
#define GPIO_Z_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1144c)
#define GPIO_Z_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_02_0_SCR                  GPIO_Z_SCR_02_0
#define GPIO_Z_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_Z_SCR_02_0
#define GPIO_Z_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_02_0
#define GPIO_Z_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x11450)
#define GPIO_Z_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_02_0_SCR                    GPIO_Z_SCR_02_0
#define GPIO_Z_OUTPUT_VALUE_02_0_SCRREG                         GPIO_Z_SCR_02_0
#define GPIO_Z_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_02_0
#define GPIO_Z_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x11454)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Z_SCR_02_0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_Z_SCR_02_0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11458

// Reserved address 0x1145c

// Register GPIO_Z_ENABLE_CONFIG_03_0
#define GPIO_Z_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x11460)
#define GPIO_Z_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_SCR                   GPIO_Z_SCR_03_0
#define GPIO_Z_ENABLE_CONFIG_03_0_SCRREG                        GPIO_Z_SCR_03_0
#define GPIO_Z_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_03_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x11464)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Z_SCR_03_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_Z_SCR_03_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_03_0
#define GPIO_Z_INPUT_03_0                       MK_ADDR_CONST(0x11468)
#define GPIO_Z_INPUT_03_0_SECURE                        0x0
#define GPIO_Z_INPUT_03_0_DUAL                  0x0
#define GPIO_Z_INPUT_03_0_SCR                   GPIO_Z_SCR_03_0
#define GPIO_Z_INPUT_03_0_SCRREG                        GPIO_Z_SCR_03_0
#define GPIO_Z_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_03_0
#define GPIO_Z_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1146c)
#define GPIO_Z_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_03_0_SCR                  GPIO_Z_SCR_03_0
#define GPIO_Z_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_Z_SCR_03_0
#define GPIO_Z_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_03_0
#define GPIO_Z_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x11470)
#define GPIO_Z_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_03_0_SCR                    GPIO_Z_SCR_03_0
#define GPIO_Z_OUTPUT_VALUE_03_0_SCRREG                         GPIO_Z_SCR_03_0
#define GPIO_Z_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_03_0
#define GPIO_Z_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x11474)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Z_SCR_03_0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_Z_SCR_03_0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11478

// Reserved address 0x1147c

// Register GPIO_Z_ENABLE_CONFIG_04_0
#define GPIO_Z_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x11480)
#define GPIO_Z_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_SCR                   GPIO_Z_SCR_04_0
#define GPIO_Z_ENABLE_CONFIG_04_0_SCRREG                        GPIO_Z_SCR_04_0
#define GPIO_Z_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_04_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x11484)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Z_SCR_04_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_Z_SCR_04_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_04_0
#define GPIO_Z_INPUT_04_0                       MK_ADDR_CONST(0x11488)
#define GPIO_Z_INPUT_04_0_SECURE                        0x0
#define GPIO_Z_INPUT_04_0_DUAL                  0x0
#define GPIO_Z_INPUT_04_0_SCR                   GPIO_Z_SCR_04_0
#define GPIO_Z_INPUT_04_0_SCRREG                        GPIO_Z_SCR_04_0
#define GPIO_Z_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_04_0
#define GPIO_Z_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1148c)
#define GPIO_Z_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_04_0_SCR                  GPIO_Z_SCR_04_0
#define GPIO_Z_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_Z_SCR_04_0
#define GPIO_Z_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_04_0
#define GPIO_Z_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x11490)
#define GPIO_Z_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_04_0_SCR                    GPIO_Z_SCR_04_0
#define GPIO_Z_OUTPUT_VALUE_04_0_SCRREG                         GPIO_Z_SCR_04_0
#define GPIO_Z_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_04_0
#define GPIO_Z_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x11494)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Z_SCR_04_0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_Z_SCR_04_0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x11498

// Reserved address 0x1149c

// Register GPIO_Z_ENABLE_CONFIG_05_0
#define GPIO_Z_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x114a0)
#define GPIO_Z_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_SCR                   GPIO_Z_SCR_05_0
#define GPIO_Z_ENABLE_CONFIG_05_0_SCRREG                        GPIO_Z_SCR_05_0
#define GPIO_Z_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_05_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x114a4)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Z_SCR_05_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_Z_SCR_05_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_05_0
#define GPIO_Z_INPUT_05_0                       MK_ADDR_CONST(0x114a8)
#define GPIO_Z_INPUT_05_0_SECURE                        0x0
#define GPIO_Z_INPUT_05_0_DUAL                  0x0
#define GPIO_Z_INPUT_05_0_SCR                   GPIO_Z_SCR_05_0
#define GPIO_Z_INPUT_05_0_SCRREG                        GPIO_Z_SCR_05_0
#define GPIO_Z_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_05_0
#define GPIO_Z_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x114ac)
#define GPIO_Z_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_05_0_SCR                  GPIO_Z_SCR_05_0
#define GPIO_Z_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_Z_SCR_05_0
#define GPIO_Z_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_05_0
#define GPIO_Z_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x114b0)
#define GPIO_Z_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_05_0_SCR                    GPIO_Z_SCR_05_0
#define GPIO_Z_OUTPUT_VALUE_05_0_SCRREG                         GPIO_Z_SCR_05_0
#define GPIO_Z_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_05_0
#define GPIO_Z_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x114b4)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Z_SCR_05_0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_Z_SCR_05_0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x114b8

// Reserved address 0x114bc

// Register GPIO_Z_ENABLE_CONFIG_06_0
#define GPIO_Z_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x114c0)
#define GPIO_Z_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_SCR                   GPIO_Z_SCR_06_0
#define GPIO_Z_ENABLE_CONFIG_06_0_SCRREG                        GPIO_Z_SCR_06_0
#define GPIO_Z_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_06_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x114c4)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Z_SCR_06_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_Z_SCR_06_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_06_0
#define GPIO_Z_INPUT_06_0                       MK_ADDR_CONST(0x114c8)
#define GPIO_Z_INPUT_06_0_SECURE                        0x0
#define GPIO_Z_INPUT_06_0_DUAL                  0x0
#define GPIO_Z_INPUT_06_0_SCR                   GPIO_Z_SCR_06_0
#define GPIO_Z_INPUT_06_0_SCRREG                        GPIO_Z_SCR_06_0
#define GPIO_Z_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_06_0
#define GPIO_Z_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x114cc)
#define GPIO_Z_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_06_0_SCR                  GPIO_Z_SCR_06_0
#define GPIO_Z_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_Z_SCR_06_0
#define GPIO_Z_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_06_0
#define GPIO_Z_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x114d0)
#define GPIO_Z_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_06_0_SCR                    GPIO_Z_SCR_06_0
#define GPIO_Z_OUTPUT_VALUE_06_0_SCRREG                         GPIO_Z_SCR_06_0
#define GPIO_Z_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_06_0
#define GPIO_Z_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x114d4)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Z_SCR_06_0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_Z_SCR_06_0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x114d8

// Reserved address 0x114dc

// Register GPIO_Z_ENABLE_CONFIG_07_0
#define GPIO_Z_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x114e0)
#define GPIO_Z_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_SCR                   GPIO_Z_SCR_07_0
#define GPIO_Z_ENABLE_CONFIG_07_0_SCRREG                        GPIO_Z_SCR_07_0
#define GPIO_Z_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_Z_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Z_DEBOUNCE_THRESHOLD_07_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x114e4)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Z_SCR_07_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_Z_SCR_07_0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_INPUT_07_0
#define GPIO_Z_INPUT_07_0                       MK_ADDR_CONST(0x114e8)
#define GPIO_Z_INPUT_07_0_SECURE                        0x0
#define GPIO_Z_INPUT_07_0_DUAL                  0x0
#define GPIO_Z_INPUT_07_0_SCR                   GPIO_Z_SCR_07_0
#define GPIO_Z_INPUT_07_0_SCRREG                        GPIO_Z_SCR_07_0
#define GPIO_Z_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_Z_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_Z_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_Z_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Z_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Z_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Z_OUTPUT_CONTROL_07_0
#define GPIO_Z_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x114ec)
#define GPIO_Z_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_Z_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_Z_OUTPUT_CONTROL_07_0_SCR                  GPIO_Z_SCR_07_0
#define GPIO_Z_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_Z_SCR_07_0
#define GPIO_Z_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_Z_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Z_OUTPUT_VALUE_07_0
#define GPIO_Z_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x114f0)
#define GPIO_Z_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_Z_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_Z_OUTPUT_VALUE_07_0_SCR                    GPIO_Z_SCR_07_0
#define GPIO_Z_OUTPUT_VALUE_07_0_SCRREG                         GPIO_Z_SCR_07_0
#define GPIO_Z_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_Z_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_CLEAR_07_0
#define GPIO_Z_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x114f4)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Z_SCR_07_0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_Z_SCR_07_0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_Z_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x114f8

// Reserved address 0x114fc

// Register GPIO_Z_INTERRUPT_STATUS_G0_0
#define GPIO_Z_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x11500)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G1_0
#define GPIO_Z_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x11504)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G2_0
#define GPIO_Z_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x11508)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G3_0
#define GPIO_Z_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1150c)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G4_0
#define GPIO_Z_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x11510)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G5_0
#define GPIO_Z_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x11514)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G6_0
#define GPIO_Z_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x11518)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Z_INTERRUPT_STATUS_G7_0
#define GPIO_Z_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1151c)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_Z_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x11520

// Reserved address 0x11524

// Reserved address 0x11528

// Reserved address 0x1152c

// Reserved address 0x11530

// Reserved address 0x11534

// Reserved address 0x11538

// Reserved address 0x1153c

// Reserved address 0x11540

// Reserved address 0x11544

// Reserved address 0x11548

// Reserved address 0x1154c

// Reserved address 0x11550

// Reserved address 0x11554

// Reserved address 0x11558

// Reserved address 0x1155c

// Reserved address 0x11560

// Reserved address 0x11564

// Reserved address 0x11568

// Reserved address 0x1156c

// Reserved address 0x11570

// Reserved address 0x11574

// Reserved address 0x11578

// Reserved address 0x1157c

// Reserved address 0x11580

// Reserved address 0x11584

// Reserved address 0x11588

// Reserved address 0x1158c

// Reserved address 0x11590

// Reserved address 0x11594

// Reserved address 0x11598

// Reserved address 0x1159c

// Reserved address 0x115a0

// Reserved address 0x115a4

// Reserved address 0x115a8

// Reserved address 0x115ac

// Reserved address 0x115b0

// Reserved address 0x115b4

// Reserved address 0x115b8

// Reserved address 0x115bc

// Reserved address 0x115c0

// Reserved address 0x115c4

// Reserved address 0x115c8

// Reserved address 0x115cc

// Reserved address 0x115d0

// Reserved address 0x115d4

// Reserved address 0x115d8

// Reserved address 0x115dc

// Reserved address 0x115e0

// Reserved address 0x115e4

// Reserved address 0x115e8

// Reserved address 0x115ec

// Reserved address 0x115f0

// Reserved address 0x115f4

// Reserved address 0x115f8

// Reserved address 0x115fc

// Register GPIO_M_ENABLE_CONFIG_00_0
#define GPIO_M_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12000)
#define GPIO_M_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_00_0_SCR                   GPIO_M_SCR_00_0
#define GPIO_M_ENABLE_CONFIG_00_0_SCRREG                        GPIO_M_SCR_00_0
#define GPIO_M_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_00_0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12004)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_M_SCR_00_0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_M_SCR_00_0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_00_0
#define GPIO_M_INPUT_00_0                       MK_ADDR_CONST(0x12008)
#define GPIO_M_INPUT_00_0_SECURE                        0x0
#define GPIO_M_INPUT_00_0_DUAL                  0x0
#define GPIO_M_INPUT_00_0_SCR                   GPIO_M_SCR_00_0
#define GPIO_M_INPUT_00_0_SCRREG                        GPIO_M_SCR_00_0
#define GPIO_M_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_00_0
#define GPIO_M_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1200c)
#define GPIO_M_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_00_0_SCR                  GPIO_M_SCR_00_0
#define GPIO_M_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_M_SCR_00_0
#define GPIO_M_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_00_0
#define GPIO_M_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12010)
#define GPIO_M_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_00_0_SCR                    GPIO_M_SCR_00_0
#define GPIO_M_OUTPUT_VALUE_00_0_SCRREG                         GPIO_M_SCR_00_0
#define GPIO_M_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_00_0
#define GPIO_M_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12014)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_00_0_SCR                         GPIO_M_SCR_00_0
#define GPIO_M_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_M_SCR_00_0
#define GPIO_M_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12018

// Reserved address 0x1201c

// Register GPIO_M_ENABLE_CONFIG_01_0
#define GPIO_M_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12020)
#define GPIO_M_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_01_0_SCR                   GPIO_M_SCR_01_0
#define GPIO_M_ENABLE_CONFIG_01_0_SCRREG                        GPIO_M_SCR_01_0
#define GPIO_M_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_01_0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12024)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_M_SCR_01_0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_M_SCR_01_0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_01_0
#define GPIO_M_INPUT_01_0                       MK_ADDR_CONST(0x12028)
#define GPIO_M_INPUT_01_0_SECURE                        0x0
#define GPIO_M_INPUT_01_0_DUAL                  0x0
#define GPIO_M_INPUT_01_0_SCR                   GPIO_M_SCR_01_0
#define GPIO_M_INPUT_01_0_SCRREG                        GPIO_M_SCR_01_0
#define GPIO_M_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_01_0
#define GPIO_M_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1202c)
#define GPIO_M_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_01_0_SCR                  GPIO_M_SCR_01_0
#define GPIO_M_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_M_SCR_01_0
#define GPIO_M_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_01_0
#define GPIO_M_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12030)
#define GPIO_M_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_01_0_SCR                    GPIO_M_SCR_01_0
#define GPIO_M_OUTPUT_VALUE_01_0_SCRREG                         GPIO_M_SCR_01_0
#define GPIO_M_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_01_0
#define GPIO_M_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12034)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_01_0_SCR                         GPIO_M_SCR_01_0
#define GPIO_M_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_M_SCR_01_0
#define GPIO_M_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12038

// Reserved address 0x1203c

// Register GPIO_M_ENABLE_CONFIG_02_0
#define GPIO_M_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12040)
#define GPIO_M_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_02_0_SCR                   GPIO_M_SCR_02_0
#define GPIO_M_ENABLE_CONFIG_02_0_SCRREG                        GPIO_M_SCR_02_0
#define GPIO_M_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_02_0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12044)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_M_SCR_02_0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_M_SCR_02_0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_02_0
#define GPIO_M_INPUT_02_0                       MK_ADDR_CONST(0x12048)
#define GPIO_M_INPUT_02_0_SECURE                        0x0
#define GPIO_M_INPUT_02_0_DUAL                  0x0
#define GPIO_M_INPUT_02_0_SCR                   GPIO_M_SCR_02_0
#define GPIO_M_INPUT_02_0_SCRREG                        GPIO_M_SCR_02_0
#define GPIO_M_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_02_0
#define GPIO_M_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1204c)
#define GPIO_M_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_02_0_SCR                  GPIO_M_SCR_02_0
#define GPIO_M_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_M_SCR_02_0
#define GPIO_M_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_02_0
#define GPIO_M_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12050)
#define GPIO_M_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_02_0_SCR                    GPIO_M_SCR_02_0
#define GPIO_M_OUTPUT_VALUE_02_0_SCRREG                         GPIO_M_SCR_02_0
#define GPIO_M_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_02_0
#define GPIO_M_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12054)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_02_0_SCR                         GPIO_M_SCR_02_0
#define GPIO_M_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_M_SCR_02_0
#define GPIO_M_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12058

// Reserved address 0x1205c

// Register GPIO_M_ENABLE_CONFIG_03_0
#define GPIO_M_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12060)
#define GPIO_M_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_03_0_SCR                   GPIO_M_SCR_03_0
#define GPIO_M_ENABLE_CONFIG_03_0_SCRREG                        GPIO_M_SCR_03_0
#define GPIO_M_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_03_0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12064)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_M_SCR_03_0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_M_SCR_03_0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_03_0
#define GPIO_M_INPUT_03_0                       MK_ADDR_CONST(0x12068)
#define GPIO_M_INPUT_03_0_SECURE                        0x0
#define GPIO_M_INPUT_03_0_DUAL                  0x0
#define GPIO_M_INPUT_03_0_SCR                   GPIO_M_SCR_03_0
#define GPIO_M_INPUT_03_0_SCRREG                        GPIO_M_SCR_03_0
#define GPIO_M_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_03_0
#define GPIO_M_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1206c)
#define GPIO_M_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_03_0_SCR                  GPIO_M_SCR_03_0
#define GPIO_M_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_M_SCR_03_0
#define GPIO_M_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_03_0
#define GPIO_M_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12070)
#define GPIO_M_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_03_0_SCR                    GPIO_M_SCR_03_0
#define GPIO_M_OUTPUT_VALUE_03_0_SCRREG                         GPIO_M_SCR_03_0
#define GPIO_M_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_03_0
#define GPIO_M_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12074)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_03_0_SCR                         GPIO_M_SCR_03_0
#define GPIO_M_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_M_SCR_03_0
#define GPIO_M_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12078

// Reserved address 0x1207c

// Register GPIO_M_ENABLE_CONFIG_04_0
#define GPIO_M_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12080)
#define GPIO_M_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_04_0_SCR                   GPIO_M_SCR_04_0
#define GPIO_M_ENABLE_CONFIG_04_0_SCRREG                        GPIO_M_SCR_04_0
#define GPIO_M_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_04_0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12084)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_M_SCR_04_0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_M_SCR_04_0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_04_0
#define GPIO_M_INPUT_04_0                       MK_ADDR_CONST(0x12088)
#define GPIO_M_INPUT_04_0_SECURE                        0x0
#define GPIO_M_INPUT_04_0_DUAL                  0x0
#define GPIO_M_INPUT_04_0_SCR                   GPIO_M_SCR_04_0
#define GPIO_M_INPUT_04_0_SCRREG                        GPIO_M_SCR_04_0
#define GPIO_M_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_04_0
#define GPIO_M_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1208c)
#define GPIO_M_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_04_0_SCR                  GPIO_M_SCR_04_0
#define GPIO_M_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_M_SCR_04_0
#define GPIO_M_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_04_0
#define GPIO_M_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12090)
#define GPIO_M_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_04_0_SCR                    GPIO_M_SCR_04_0
#define GPIO_M_OUTPUT_VALUE_04_0_SCRREG                         GPIO_M_SCR_04_0
#define GPIO_M_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_04_0
#define GPIO_M_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12094)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_04_0_SCR                         GPIO_M_SCR_04_0
#define GPIO_M_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_M_SCR_04_0
#define GPIO_M_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12098

// Reserved address 0x1209c

// Register GPIO_M_ENABLE_CONFIG_05_0
#define GPIO_M_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x120a0)
#define GPIO_M_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_05_0_SCR                   GPIO_M_SCR_05_0
#define GPIO_M_ENABLE_CONFIG_05_0_SCRREG                        GPIO_M_SCR_05_0
#define GPIO_M_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_05_0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x120a4)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_M_SCR_05_0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_M_SCR_05_0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_05_0
#define GPIO_M_INPUT_05_0                       MK_ADDR_CONST(0x120a8)
#define GPIO_M_INPUT_05_0_SECURE                        0x0
#define GPIO_M_INPUT_05_0_DUAL                  0x0
#define GPIO_M_INPUT_05_0_SCR                   GPIO_M_SCR_05_0
#define GPIO_M_INPUT_05_0_SCRREG                        GPIO_M_SCR_05_0
#define GPIO_M_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_05_0
#define GPIO_M_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x120ac)
#define GPIO_M_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_05_0_SCR                  GPIO_M_SCR_05_0
#define GPIO_M_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_M_SCR_05_0
#define GPIO_M_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_05_0
#define GPIO_M_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x120b0)
#define GPIO_M_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_05_0_SCR                    GPIO_M_SCR_05_0
#define GPIO_M_OUTPUT_VALUE_05_0_SCRREG                         GPIO_M_SCR_05_0
#define GPIO_M_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_05_0
#define GPIO_M_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x120b4)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_05_0_SCR                         GPIO_M_SCR_05_0
#define GPIO_M_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_M_SCR_05_0
#define GPIO_M_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x120b8

// Reserved address 0x120bc

// Register GPIO_M_ENABLE_CONFIG_06_0
#define GPIO_M_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x120c0)
#define GPIO_M_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_06_0_SCR                   GPIO_M_SCR_06_0
#define GPIO_M_ENABLE_CONFIG_06_0_SCRREG                        GPIO_M_SCR_06_0
#define GPIO_M_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_06_0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x120c4)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_M_SCR_06_0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_M_SCR_06_0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_06_0
#define GPIO_M_INPUT_06_0                       MK_ADDR_CONST(0x120c8)
#define GPIO_M_INPUT_06_0_SECURE                        0x0
#define GPIO_M_INPUT_06_0_DUAL                  0x0
#define GPIO_M_INPUT_06_0_SCR                   GPIO_M_SCR_06_0
#define GPIO_M_INPUT_06_0_SCRREG                        GPIO_M_SCR_06_0
#define GPIO_M_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_06_0
#define GPIO_M_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x120cc)
#define GPIO_M_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_06_0_SCR                  GPIO_M_SCR_06_0
#define GPIO_M_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_M_SCR_06_0
#define GPIO_M_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_06_0
#define GPIO_M_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x120d0)
#define GPIO_M_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_06_0_SCR                    GPIO_M_SCR_06_0
#define GPIO_M_OUTPUT_VALUE_06_0_SCRREG                         GPIO_M_SCR_06_0
#define GPIO_M_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_06_0
#define GPIO_M_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x120d4)
#define GPIO_M_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_06_0_SCR                         GPIO_M_SCR_06_0
#define GPIO_M_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_M_SCR_06_0
#define GPIO_M_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x120d8

// Reserved address 0x120dc

// Register GPIO_M_ENABLE_CONFIG_07_0
#define GPIO_M_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x120e0)
#define GPIO_M_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_M_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_M_ENABLE_CONFIG_07_0_SCR                   GPIO_M_SCR_07_0
#define GPIO_M_ENABLE_CONFIG_07_0_SCRREG                        GPIO_M_SCR_07_0
#define GPIO_M_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_M_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_M_DEBOUNCE_THRESHOLD_07_0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x120e4)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_M_SCR_07_0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_M_SCR_07_0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_INPUT_07_0
#define GPIO_M_INPUT_07_0                       MK_ADDR_CONST(0x120e8)
#define GPIO_M_INPUT_07_0_SECURE                        0x0
#define GPIO_M_INPUT_07_0_DUAL                  0x0
#define GPIO_M_INPUT_07_0_SCR                   GPIO_M_SCR_07_0
#define GPIO_M_INPUT_07_0_SCRREG                        GPIO_M_SCR_07_0
#define GPIO_M_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_M_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_M_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_M_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_M_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_M_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_M_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_M_OUTPUT_CONTROL_07_0
#define GPIO_M_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x120ec)
#define GPIO_M_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_M_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_M_OUTPUT_CONTROL_07_0_SCR                  GPIO_M_SCR_07_0
#define GPIO_M_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_M_SCR_07_0
#define GPIO_M_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_M_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_M_OUTPUT_VALUE_07_0
#define GPIO_M_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x120f0)
#define GPIO_M_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_M_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_M_OUTPUT_VALUE_07_0_SCR                    GPIO_M_SCR_07_0
#define GPIO_M_OUTPUT_VALUE_07_0_SCRREG                         GPIO_M_SCR_07_0
#define GPIO_M_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_M_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_CLEAR_07_0
#define GPIO_M_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x120f4)
#define GPIO_M_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_M_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_M_INTERRUPT_CLEAR_07_0_SCR                         GPIO_M_SCR_07_0
#define GPIO_M_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_M_SCR_07_0
#define GPIO_M_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_M_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x120f8

// Reserved address 0x120fc

// Register GPIO_M_INTERRUPT_STATUS_G0_0
#define GPIO_M_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12100)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_M_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G1_0
#define GPIO_M_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12104)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_M_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G2_0
#define GPIO_M_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12108)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_M_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G3_0
#define GPIO_M_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1210c)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_M_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G4_0
#define GPIO_M_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12110)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_M_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G5_0
#define GPIO_M_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12114)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_M_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G6_0
#define GPIO_M_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12118)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_M_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_M_INTERRUPT_STATUS_G7_0
#define GPIO_M_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1211c)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_M_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_M_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_M_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_M_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_M_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x12120

// Reserved address 0x12124

// Reserved address 0x12128

// Reserved address 0x1212c

// Reserved address 0x12130

// Reserved address 0x12134

// Reserved address 0x12138

// Reserved address 0x1213c

// Reserved address 0x12140

// Reserved address 0x12144

// Reserved address 0x12148

// Reserved address 0x1214c

// Reserved address 0x12150

// Reserved address 0x12154

// Reserved address 0x12158

// Reserved address 0x1215c

// Reserved address 0x12160

// Reserved address 0x12164

// Reserved address 0x12168

// Reserved address 0x1216c

// Reserved address 0x12170

// Reserved address 0x12174

// Reserved address 0x12178

// Reserved address 0x1217c

// Reserved address 0x12180

// Reserved address 0x12184

// Reserved address 0x12188

// Reserved address 0x1218c

// Reserved address 0x12190

// Reserved address 0x12194

// Reserved address 0x12198

// Reserved address 0x1219c

// Reserved address 0x121a0

// Reserved address 0x121a4

// Reserved address 0x121a8

// Reserved address 0x121ac

// Reserved address 0x121b0

// Reserved address 0x121b4

// Reserved address 0x121b8

// Reserved address 0x121bc

// Reserved address 0x121c0

// Reserved address 0x121c4

// Reserved address 0x121c8

// Reserved address 0x121cc

// Reserved address 0x121d0

// Reserved address 0x121d4

// Reserved address 0x121d8

// Reserved address 0x121dc

// Reserved address 0x121e0

// Reserved address 0x121e4

// Reserved address 0x121e8

// Reserved address 0x121ec

// Reserved address 0x121f0

// Reserved address 0x121f4

// Reserved address 0x121f8

// Reserved address 0x121fc

// Register GPIO_N_ENABLE_CONFIG_00_0
#define GPIO_N_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12200)
#define GPIO_N_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_00_0_SCR                   GPIO_N_SCR_00_0
#define GPIO_N_ENABLE_CONFIG_00_0_SCRREG                        GPIO_N_SCR_00_0
#define GPIO_N_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_00_0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12204)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_N_SCR_00_0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_N_SCR_00_0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_00_0
#define GPIO_N_INPUT_00_0                       MK_ADDR_CONST(0x12208)
#define GPIO_N_INPUT_00_0_SECURE                        0x0
#define GPIO_N_INPUT_00_0_DUAL                  0x0
#define GPIO_N_INPUT_00_0_SCR                   GPIO_N_SCR_00_0
#define GPIO_N_INPUT_00_0_SCRREG                        GPIO_N_SCR_00_0
#define GPIO_N_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_00_0
#define GPIO_N_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1220c)
#define GPIO_N_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_00_0_SCR                  GPIO_N_SCR_00_0
#define GPIO_N_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_N_SCR_00_0
#define GPIO_N_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_00_0
#define GPIO_N_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12210)
#define GPIO_N_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_00_0_SCR                    GPIO_N_SCR_00_0
#define GPIO_N_OUTPUT_VALUE_00_0_SCRREG                         GPIO_N_SCR_00_0
#define GPIO_N_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_00_0
#define GPIO_N_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12214)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_00_0_SCR                         GPIO_N_SCR_00_0
#define GPIO_N_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_N_SCR_00_0
#define GPIO_N_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12218

// Reserved address 0x1221c

// Register GPIO_N_ENABLE_CONFIG_01_0
#define GPIO_N_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12220)
#define GPIO_N_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_01_0_SCR                   GPIO_N_SCR_01_0
#define GPIO_N_ENABLE_CONFIG_01_0_SCRREG                        GPIO_N_SCR_01_0
#define GPIO_N_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_01_0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12224)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_N_SCR_01_0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_N_SCR_01_0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_01_0
#define GPIO_N_INPUT_01_0                       MK_ADDR_CONST(0x12228)
#define GPIO_N_INPUT_01_0_SECURE                        0x0
#define GPIO_N_INPUT_01_0_DUAL                  0x0
#define GPIO_N_INPUT_01_0_SCR                   GPIO_N_SCR_01_0
#define GPIO_N_INPUT_01_0_SCRREG                        GPIO_N_SCR_01_0
#define GPIO_N_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_01_0
#define GPIO_N_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1222c)
#define GPIO_N_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_01_0_SCR                  GPIO_N_SCR_01_0
#define GPIO_N_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_N_SCR_01_0
#define GPIO_N_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_01_0
#define GPIO_N_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12230)
#define GPIO_N_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_01_0_SCR                    GPIO_N_SCR_01_0
#define GPIO_N_OUTPUT_VALUE_01_0_SCRREG                         GPIO_N_SCR_01_0
#define GPIO_N_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_01_0
#define GPIO_N_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12234)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_01_0_SCR                         GPIO_N_SCR_01_0
#define GPIO_N_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_N_SCR_01_0
#define GPIO_N_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12238

// Reserved address 0x1223c

// Register GPIO_N_ENABLE_CONFIG_02_0
#define GPIO_N_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12240)
#define GPIO_N_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_02_0_SCR                   GPIO_N_SCR_02_0
#define GPIO_N_ENABLE_CONFIG_02_0_SCRREG                        GPIO_N_SCR_02_0
#define GPIO_N_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_02_0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12244)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_N_SCR_02_0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_N_SCR_02_0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_02_0
#define GPIO_N_INPUT_02_0                       MK_ADDR_CONST(0x12248)
#define GPIO_N_INPUT_02_0_SECURE                        0x0
#define GPIO_N_INPUT_02_0_DUAL                  0x0
#define GPIO_N_INPUT_02_0_SCR                   GPIO_N_SCR_02_0
#define GPIO_N_INPUT_02_0_SCRREG                        GPIO_N_SCR_02_0
#define GPIO_N_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_02_0
#define GPIO_N_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1224c)
#define GPIO_N_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_02_0_SCR                  GPIO_N_SCR_02_0
#define GPIO_N_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_N_SCR_02_0
#define GPIO_N_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_02_0
#define GPIO_N_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12250)
#define GPIO_N_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_02_0_SCR                    GPIO_N_SCR_02_0
#define GPIO_N_OUTPUT_VALUE_02_0_SCRREG                         GPIO_N_SCR_02_0
#define GPIO_N_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_02_0
#define GPIO_N_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12254)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_02_0_SCR                         GPIO_N_SCR_02_0
#define GPIO_N_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_N_SCR_02_0
#define GPIO_N_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12258

// Reserved address 0x1225c

// Register GPIO_N_ENABLE_CONFIG_03_0
#define GPIO_N_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12260)
#define GPIO_N_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_03_0_SCR                   GPIO_N_SCR_03_0
#define GPIO_N_ENABLE_CONFIG_03_0_SCRREG                        GPIO_N_SCR_03_0
#define GPIO_N_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_03_0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12264)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_N_SCR_03_0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_N_SCR_03_0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_03_0
#define GPIO_N_INPUT_03_0                       MK_ADDR_CONST(0x12268)
#define GPIO_N_INPUT_03_0_SECURE                        0x0
#define GPIO_N_INPUT_03_0_DUAL                  0x0
#define GPIO_N_INPUT_03_0_SCR                   GPIO_N_SCR_03_0
#define GPIO_N_INPUT_03_0_SCRREG                        GPIO_N_SCR_03_0
#define GPIO_N_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_03_0
#define GPIO_N_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1226c)
#define GPIO_N_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_03_0_SCR                  GPIO_N_SCR_03_0
#define GPIO_N_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_N_SCR_03_0
#define GPIO_N_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_03_0
#define GPIO_N_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12270)
#define GPIO_N_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_03_0_SCR                    GPIO_N_SCR_03_0
#define GPIO_N_OUTPUT_VALUE_03_0_SCRREG                         GPIO_N_SCR_03_0
#define GPIO_N_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_03_0
#define GPIO_N_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12274)
#define GPIO_N_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_03_0_SCR                         GPIO_N_SCR_03_0
#define GPIO_N_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_N_SCR_03_0
#define GPIO_N_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12278

// Reserved address 0x1227c

// Register GPIO_N_ENABLE_CONFIG_04_0
#define GPIO_N_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12280)
#define GPIO_N_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_04_0_SCR                   GPIO_N_SCR_04_0
#define GPIO_N_ENABLE_CONFIG_04_0_SCRREG                        GPIO_N_SCR_04_0
#define GPIO_N_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_04_0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12284)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_N_SCR_04_0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_N_SCR_04_0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_04_0
#define GPIO_N_INPUT_04_0                       MK_ADDR_CONST(0x12288)
#define GPIO_N_INPUT_04_0_SECURE                        0x0
#define GPIO_N_INPUT_04_0_DUAL                  0x0
#define GPIO_N_INPUT_04_0_SCR                   GPIO_N_SCR_04_0
#define GPIO_N_INPUT_04_0_SCRREG                        GPIO_N_SCR_04_0
#define GPIO_N_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_04_0
#define GPIO_N_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1228c)
#define GPIO_N_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_04_0_SCR                  GPIO_N_SCR_04_0
#define GPIO_N_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_N_SCR_04_0
#define GPIO_N_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_04_0
#define GPIO_N_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12290)
#define GPIO_N_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_04_0_SCR                    GPIO_N_SCR_04_0
#define GPIO_N_OUTPUT_VALUE_04_0_SCRREG                         GPIO_N_SCR_04_0
#define GPIO_N_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_04_0
#define GPIO_N_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12294)
#define GPIO_N_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_04_0_SCR                         GPIO_N_SCR_04_0
#define GPIO_N_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_N_SCR_04_0
#define GPIO_N_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12298

// Reserved address 0x1229c

// Register GPIO_N_ENABLE_CONFIG_05_0
#define GPIO_N_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x122a0)
#define GPIO_N_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_05_0_SCR                   GPIO_N_SCR_05_0
#define GPIO_N_ENABLE_CONFIG_05_0_SCRREG                        GPIO_N_SCR_05_0
#define GPIO_N_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_05_0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x122a4)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_N_SCR_05_0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_N_SCR_05_0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_05_0
#define GPIO_N_INPUT_05_0                       MK_ADDR_CONST(0x122a8)
#define GPIO_N_INPUT_05_0_SECURE                        0x0
#define GPIO_N_INPUT_05_0_DUAL                  0x0
#define GPIO_N_INPUT_05_0_SCR                   GPIO_N_SCR_05_0
#define GPIO_N_INPUT_05_0_SCRREG                        GPIO_N_SCR_05_0
#define GPIO_N_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_05_0
#define GPIO_N_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x122ac)
#define GPIO_N_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_05_0_SCR                  GPIO_N_SCR_05_0
#define GPIO_N_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_N_SCR_05_0
#define GPIO_N_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_05_0
#define GPIO_N_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x122b0)
#define GPIO_N_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_05_0_SCR                    GPIO_N_SCR_05_0
#define GPIO_N_OUTPUT_VALUE_05_0_SCRREG                         GPIO_N_SCR_05_0
#define GPIO_N_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_05_0
#define GPIO_N_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x122b4)
#define GPIO_N_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_05_0_SCR                         GPIO_N_SCR_05_0
#define GPIO_N_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_N_SCR_05_0
#define GPIO_N_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x122b8

// Reserved address 0x122bc

// Register GPIO_N_ENABLE_CONFIG_06_0
#define GPIO_N_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x122c0)
#define GPIO_N_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_06_0_SCR                   GPIO_N_SCR_06_0
#define GPIO_N_ENABLE_CONFIG_06_0_SCRREG                        GPIO_N_SCR_06_0
#define GPIO_N_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_06_0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x122c4)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_N_SCR_06_0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_N_SCR_06_0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_06_0
#define GPIO_N_INPUT_06_0                       MK_ADDR_CONST(0x122c8)
#define GPIO_N_INPUT_06_0_SECURE                        0x0
#define GPIO_N_INPUT_06_0_DUAL                  0x0
#define GPIO_N_INPUT_06_0_SCR                   GPIO_N_SCR_06_0
#define GPIO_N_INPUT_06_0_SCRREG                        GPIO_N_SCR_06_0
#define GPIO_N_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_06_0
#define GPIO_N_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x122cc)
#define GPIO_N_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_06_0_SCR                  GPIO_N_SCR_06_0
#define GPIO_N_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_N_SCR_06_0
#define GPIO_N_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_06_0
#define GPIO_N_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x122d0)
#define GPIO_N_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_06_0_SCR                    GPIO_N_SCR_06_0
#define GPIO_N_OUTPUT_VALUE_06_0_SCRREG                         GPIO_N_SCR_06_0
#define GPIO_N_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_06_0
#define GPIO_N_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x122d4)
#define GPIO_N_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_06_0_SCR                         GPIO_N_SCR_06_0
#define GPIO_N_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_N_SCR_06_0
#define GPIO_N_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x122d8

// Reserved address 0x122dc

// Register GPIO_N_ENABLE_CONFIG_07_0
#define GPIO_N_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x122e0)
#define GPIO_N_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_N_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_N_ENABLE_CONFIG_07_0_SCR                   GPIO_N_SCR_07_0
#define GPIO_N_ENABLE_CONFIG_07_0_SCRREG                        GPIO_N_SCR_07_0
#define GPIO_N_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_N_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_N_DEBOUNCE_THRESHOLD_07_0
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x122e4)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_N_SCR_07_0
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_N_SCR_07_0
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_INPUT_07_0
#define GPIO_N_INPUT_07_0                       MK_ADDR_CONST(0x122e8)
#define GPIO_N_INPUT_07_0_SECURE                        0x0
#define GPIO_N_INPUT_07_0_DUAL                  0x0
#define GPIO_N_INPUT_07_0_SCR                   GPIO_N_SCR_07_0
#define GPIO_N_INPUT_07_0_SCRREG                        GPIO_N_SCR_07_0
#define GPIO_N_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_N_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_N_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_N_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_N_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_N_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_N_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_N_OUTPUT_CONTROL_07_0
#define GPIO_N_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x122ec)
#define GPIO_N_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_N_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_N_OUTPUT_CONTROL_07_0_SCR                  GPIO_N_SCR_07_0
#define GPIO_N_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_N_SCR_07_0
#define GPIO_N_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_N_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_N_OUTPUT_VALUE_07_0
#define GPIO_N_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x122f0)
#define GPIO_N_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_N_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_N_OUTPUT_VALUE_07_0_SCR                    GPIO_N_SCR_07_0
#define GPIO_N_OUTPUT_VALUE_07_0_SCRREG                         GPIO_N_SCR_07_0
#define GPIO_N_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_N_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_CLEAR_07_0
#define GPIO_N_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x122f4)
#define GPIO_N_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_N_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_N_INTERRUPT_CLEAR_07_0_SCR                         GPIO_N_SCR_07_0
#define GPIO_N_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_N_SCR_07_0
#define GPIO_N_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_N_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x122f8

// Reserved address 0x122fc

// Register GPIO_N_INTERRUPT_STATUS_G0_0
#define GPIO_N_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12300)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_N_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G1_0
#define GPIO_N_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12304)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_N_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G2_0
#define GPIO_N_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12308)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_N_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G3_0
#define GPIO_N_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1230c)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_N_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G4_0
#define GPIO_N_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12310)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_N_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G5_0
#define GPIO_N_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12314)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_N_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G6_0
#define GPIO_N_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12318)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_N_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_N_INTERRUPT_STATUS_G7_0
#define GPIO_N_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1231c)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_N_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_N_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_N_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_N_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_N_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x12320

// Reserved address 0x12324

// Reserved address 0x12328

// Reserved address 0x1232c

// Reserved address 0x12330

// Reserved address 0x12334

// Reserved address 0x12338

// Reserved address 0x1233c

// Reserved address 0x12340

// Reserved address 0x12344

// Reserved address 0x12348

// Reserved address 0x1234c

// Reserved address 0x12350

// Reserved address 0x12354

// Reserved address 0x12358

// Reserved address 0x1235c

// Reserved address 0x12360

// Reserved address 0x12364

// Reserved address 0x12368

// Reserved address 0x1236c

// Reserved address 0x12370

// Reserved address 0x12374

// Reserved address 0x12378

// Reserved address 0x1237c

// Reserved address 0x12380

// Reserved address 0x12384

// Reserved address 0x12388

// Reserved address 0x1238c

// Reserved address 0x12390

// Reserved address 0x12394

// Reserved address 0x12398

// Reserved address 0x1239c

// Reserved address 0x123a0

// Reserved address 0x123a4

// Reserved address 0x123a8

// Reserved address 0x123ac

// Reserved address 0x123b0

// Reserved address 0x123b4

// Reserved address 0x123b8

// Reserved address 0x123bc

// Reserved address 0x123c0

// Reserved address 0x123c4

// Reserved address 0x123c8

// Reserved address 0x123cc

// Reserved address 0x123d0

// Reserved address 0x123d4

// Reserved address 0x123d8

// Reserved address 0x123dc

// Reserved address 0x123e0

// Reserved address 0x123e4

// Reserved address 0x123e8

// Reserved address 0x123ec

// Reserved address 0x123f0

// Reserved address 0x123f4

// Reserved address 0x123f8

// Reserved address 0x123fc

// Register GPIO_P_ENABLE_CONFIG_00_0
#define GPIO_P_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12400)
#define GPIO_P_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_00_0_SCR                   GPIO_P_SCR_00_0
#define GPIO_P_ENABLE_CONFIG_00_0_SCRREG                        GPIO_P_SCR_00_0
#define GPIO_P_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_00_0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12404)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_P_SCR_00_0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_P_SCR_00_0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_00_0
#define GPIO_P_INPUT_00_0                       MK_ADDR_CONST(0x12408)
#define GPIO_P_INPUT_00_0_SECURE                        0x0
#define GPIO_P_INPUT_00_0_DUAL                  0x0
#define GPIO_P_INPUT_00_0_SCR                   GPIO_P_SCR_00_0
#define GPIO_P_INPUT_00_0_SCRREG                        GPIO_P_SCR_00_0
#define GPIO_P_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_00_0
#define GPIO_P_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1240c)
#define GPIO_P_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_00_0_SCR                  GPIO_P_SCR_00_0
#define GPIO_P_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_P_SCR_00_0
#define GPIO_P_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_00_0
#define GPIO_P_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12410)
#define GPIO_P_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_00_0_SCR                    GPIO_P_SCR_00_0
#define GPIO_P_OUTPUT_VALUE_00_0_SCRREG                         GPIO_P_SCR_00_0
#define GPIO_P_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_00_0
#define GPIO_P_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12414)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_00_0_SCR                         GPIO_P_SCR_00_0
#define GPIO_P_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_P_SCR_00_0
#define GPIO_P_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12418

// Reserved address 0x1241c

// Register GPIO_P_ENABLE_CONFIG_01_0
#define GPIO_P_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12420)
#define GPIO_P_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_01_0_SCR                   GPIO_P_SCR_01_0
#define GPIO_P_ENABLE_CONFIG_01_0_SCRREG                        GPIO_P_SCR_01_0
#define GPIO_P_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_01_0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12424)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_P_SCR_01_0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_P_SCR_01_0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_01_0
#define GPIO_P_INPUT_01_0                       MK_ADDR_CONST(0x12428)
#define GPIO_P_INPUT_01_0_SECURE                        0x0
#define GPIO_P_INPUT_01_0_DUAL                  0x0
#define GPIO_P_INPUT_01_0_SCR                   GPIO_P_SCR_01_0
#define GPIO_P_INPUT_01_0_SCRREG                        GPIO_P_SCR_01_0
#define GPIO_P_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_01_0
#define GPIO_P_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1242c)
#define GPIO_P_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_01_0_SCR                  GPIO_P_SCR_01_0
#define GPIO_P_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_P_SCR_01_0
#define GPIO_P_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_01_0
#define GPIO_P_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12430)
#define GPIO_P_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_01_0_SCR                    GPIO_P_SCR_01_0
#define GPIO_P_OUTPUT_VALUE_01_0_SCRREG                         GPIO_P_SCR_01_0
#define GPIO_P_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_01_0
#define GPIO_P_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12434)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_01_0_SCR                         GPIO_P_SCR_01_0
#define GPIO_P_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_P_SCR_01_0
#define GPIO_P_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12438

// Reserved address 0x1243c

// Register GPIO_P_ENABLE_CONFIG_02_0
#define GPIO_P_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12440)
#define GPIO_P_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_02_0_SCR                   GPIO_P_SCR_02_0
#define GPIO_P_ENABLE_CONFIG_02_0_SCRREG                        GPIO_P_SCR_02_0
#define GPIO_P_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_02_0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12444)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_P_SCR_02_0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_P_SCR_02_0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_02_0
#define GPIO_P_INPUT_02_0                       MK_ADDR_CONST(0x12448)
#define GPIO_P_INPUT_02_0_SECURE                        0x0
#define GPIO_P_INPUT_02_0_DUAL                  0x0
#define GPIO_P_INPUT_02_0_SCR                   GPIO_P_SCR_02_0
#define GPIO_P_INPUT_02_0_SCRREG                        GPIO_P_SCR_02_0
#define GPIO_P_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_02_0
#define GPIO_P_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1244c)
#define GPIO_P_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_02_0_SCR                  GPIO_P_SCR_02_0
#define GPIO_P_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_P_SCR_02_0
#define GPIO_P_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_02_0
#define GPIO_P_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12450)
#define GPIO_P_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_02_0_SCR                    GPIO_P_SCR_02_0
#define GPIO_P_OUTPUT_VALUE_02_0_SCRREG                         GPIO_P_SCR_02_0
#define GPIO_P_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_02_0
#define GPIO_P_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12454)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_02_0_SCR                         GPIO_P_SCR_02_0
#define GPIO_P_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_P_SCR_02_0
#define GPIO_P_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12458

// Reserved address 0x1245c

// Register GPIO_P_ENABLE_CONFIG_03_0
#define GPIO_P_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12460)
#define GPIO_P_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_03_0_SCR                   GPIO_P_SCR_03_0
#define GPIO_P_ENABLE_CONFIG_03_0_SCRREG                        GPIO_P_SCR_03_0
#define GPIO_P_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_03_0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12464)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_P_SCR_03_0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_P_SCR_03_0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_03_0
#define GPIO_P_INPUT_03_0                       MK_ADDR_CONST(0x12468)
#define GPIO_P_INPUT_03_0_SECURE                        0x0
#define GPIO_P_INPUT_03_0_DUAL                  0x0
#define GPIO_P_INPUT_03_0_SCR                   GPIO_P_SCR_03_0
#define GPIO_P_INPUT_03_0_SCRREG                        GPIO_P_SCR_03_0
#define GPIO_P_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_03_0
#define GPIO_P_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1246c)
#define GPIO_P_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_03_0_SCR                  GPIO_P_SCR_03_0
#define GPIO_P_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_P_SCR_03_0
#define GPIO_P_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_03_0
#define GPIO_P_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12470)
#define GPIO_P_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_03_0_SCR                    GPIO_P_SCR_03_0
#define GPIO_P_OUTPUT_VALUE_03_0_SCRREG                         GPIO_P_SCR_03_0
#define GPIO_P_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_03_0
#define GPIO_P_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12474)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_03_0_SCR                         GPIO_P_SCR_03_0
#define GPIO_P_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_P_SCR_03_0
#define GPIO_P_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12478

// Reserved address 0x1247c

// Register GPIO_P_ENABLE_CONFIG_04_0
#define GPIO_P_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12480)
#define GPIO_P_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_04_0_SCR                   GPIO_P_SCR_04_0
#define GPIO_P_ENABLE_CONFIG_04_0_SCRREG                        GPIO_P_SCR_04_0
#define GPIO_P_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_04_0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12484)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_P_SCR_04_0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_P_SCR_04_0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_04_0
#define GPIO_P_INPUT_04_0                       MK_ADDR_CONST(0x12488)
#define GPIO_P_INPUT_04_0_SECURE                        0x0
#define GPIO_P_INPUT_04_0_DUAL                  0x0
#define GPIO_P_INPUT_04_0_SCR                   GPIO_P_SCR_04_0
#define GPIO_P_INPUT_04_0_SCRREG                        GPIO_P_SCR_04_0
#define GPIO_P_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_04_0
#define GPIO_P_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1248c)
#define GPIO_P_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_04_0_SCR                  GPIO_P_SCR_04_0
#define GPIO_P_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_P_SCR_04_0
#define GPIO_P_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_04_0
#define GPIO_P_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12490)
#define GPIO_P_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_04_0_SCR                    GPIO_P_SCR_04_0
#define GPIO_P_OUTPUT_VALUE_04_0_SCRREG                         GPIO_P_SCR_04_0
#define GPIO_P_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_04_0
#define GPIO_P_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12494)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_04_0_SCR                         GPIO_P_SCR_04_0
#define GPIO_P_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_P_SCR_04_0
#define GPIO_P_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12498

// Reserved address 0x1249c

// Register GPIO_P_ENABLE_CONFIG_05_0
#define GPIO_P_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x124a0)
#define GPIO_P_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_05_0_SCR                   GPIO_P_SCR_05_0
#define GPIO_P_ENABLE_CONFIG_05_0_SCRREG                        GPIO_P_SCR_05_0
#define GPIO_P_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_05_0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x124a4)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_P_SCR_05_0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_P_SCR_05_0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_05_0
#define GPIO_P_INPUT_05_0                       MK_ADDR_CONST(0x124a8)
#define GPIO_P_INPUT_05_0_SECURE                        0x0
#define GPIO_P_INPUT_05_0_DUAL                  0x0
#define GPIO_P_INPUT_05_0_SCR                   GPIO_P_SCR_05_0
#define GPIO_P_INPUT_05_0_SCRREG                        GPIO_P_SCR_05_0
#define GPIO_P_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_05_0
#define GPIO_P_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x124ac)
#define GPIO_P_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_05_0_SCR                  GPIO_P_SCR_05_0
#define GPIO_P_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_P_SCR_05_0
#define GPIO_P_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_05_0
#define GPIO_P_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x124b0)
#define GPIO_P_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_05_0_SCR                    GPIO_P_SCR_05_0
#define GPIO_P_OUTPUT_VALUE_05_0_SCRREG                         GPIO_P_SCR_05_0
#define GPIO_P_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_05_0
#define GPIO_P_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x124b4)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_05_0_SCR                         GPIO_P_SCR_05_0
#define GPIO_P_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_P_SCR_05_0
#define GPIO_P_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x124b8

// Reserved address 0x124bc

// Register GPIO_P_ENABLE_CONFIG_06_0
#define GPIO_P_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x124c0)
#define GPIO_P_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_06_0_SCR                   GPIO_P_SCR_06_0
#define GPIO_P_ENABLE_CONFIG_06_0_SCRREG                        GPIO_P_SCR_06_0
#define GPIO_P_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_06_0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x124c4)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_P_SCR_06_0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_P_SCR_06_0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_06_0
#define GPIO_P_INPUT_06_0                       MK_ADDR_CONST(0x124c8)
#define GPIO_P_INPUT_06_0_SECURE                        0x0
#define GPIO_P_INPUT_06_0_DUAL                  0x0
#define GPIO_P_INPUT_06_0_SCR                   GPIO_P_SCR_06_0
#define GPIO_P_INPUT_06_0_SCRREG                        GPIO_P_SCR_06_0
#define GPIO_P_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_06_0
#define GPIO_P_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x124cc)
#define GPIO_P_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_06_0_SCR                  GPIO_P_SCR_06_0
#define GPIO_P_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_P_SCR_06_0
#define GPIO_P_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_06_0
#define GPIO_P_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x124d0)
#define GPIO_P_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_06_0_SCR                    GPIO_P_SCR_06_0
#define GPIO_P_OUTPUT_VALUE_06_0_SCRREG                         GPIO_P_SCR_06_0
#define GPIO_P_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_06_0
#define GPIO_P_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x124d4)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_06_0_SCR                         GPIO_P_SCR_06_0
#define GPIO_P_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_P_SCR_06_0
#define GPIO_P_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x124d8

// Reserved address 0x124dc

// Register GPIO_P_ENABLE_CONFIG_07_0
#define GPIO_P_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x124e0)
#define GPIO_P_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_P_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_P_ENABLE_CONFIG_07_0_SCR                   GPIO_P_SCR_07_0
#define GPIO_P_ENABLE_CONFIG_07_0_SCRREG                        GPIO_P_SCR_07_0
#define GPIO_P_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_P_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_P_DEBOUNCE_THRESHOLD_07_0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x124e4)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_P_SCR_07_0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_P_SCR_07_0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_INPUT_07_0
#define GPIO_P_INPUT_07_0                       MK_ADDR_CONST(0x124e8)
#define GPIO_P_INPUT_07_0_SECURE                        0x0
#define GPIO_P_INPUT_07_0_DUAL                  0x0
#define GPIO_P_INPUT_07_0_SCR                   GPIO_P_SCR_07_0
#define GPIO_P_INPUT_07_0_SCRREG                        GPIO_P_SCR_07_0
#define GPIO_P_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_P_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_P_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_P_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_P_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_P_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_P_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_P_OUTPUT_CONTROL_07_0
#define GPIO_P_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x124ec)
#define GPIO_P_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_P_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_P_OUTPUT_CONTROL_07_0_SCR                  GPIO_P_SCR_07_0
#define GPIO_P_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_P_SCR_07_0
#define GPIO_P_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_P_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_P_OUTPUT_VALUE_07_0
#define GPIO_P_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x124f0)
#define GPIO_P_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_P_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_P_OUTPUT_VALUE_07_0_SCR                    GPIO_P_SCR_07_0
#define GPIO_P_OUTPUT_VALUE_07_0_SCRREG                         GPIO_P_SCR_07_0
#define GPIO_P_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_P_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_CLEAR_07_0
#define GPIO_P_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x124f4)
#define GPIO_P_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_P_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_P_INTERRUPT_CLEAR_07_0_SCR                         GPIO_P_SCR_07_0
#define GPIO_P_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_P_SCR_07_0
#define GPIO_P_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_P_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x124f8

// Reserved address 0x124fc

// Register GPIO_P_INTERRUPT_STATUS_G0_0
#define GPIO_P_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12500)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_P_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G1_0
#define GPIO_P_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12504)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_P_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G2_0
#define GPIO_P_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12508)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_P_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G3_0
#define GPIO_P_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1250c)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_P_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G4_0
#define GPIO_P_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12510)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_P_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G5_0
#define GPIO_P_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12514)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_P_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G6_0
#define GPIO_P_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12518)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_P_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_P_INTERRUPT_STATUS_G7_0
#define GPIO_P_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1251c)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_P_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_P_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_P_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_P_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_P_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x12520

// Reserved address 0x12524

// Reserved address 0x12528

// Reserved address 0x1252c

// Reserved address 0x12530

// Reserved address 0x12534

// Reserved address 0x12538

// Reserved address 0x1253c

// Reserved address 0x12540

// Reserved address 0x12544

// Reserved address 0x12548

// Reserved address 0x1254c

// Reserved address 0x12550

// Reserved address 0x12554

// Reserved address 0x12558

// Reserved address 0x1255c

// Reserved address 0x12560

// Reserved address 0x12564

// Reserved address 0x12568

// Reserved address 0x1256c

// Reserved address 0x12570

// Reserved address 0x12574

// Reserved address 0x12578

// Reserved address 0x1257c

// Reserved address 0x12580

// Reserved address 0x12584

// Reserved address 0x12588

// Reserved address 0x1258c

// Reserved address 0x12590

// Reserved address 0x12594

// Reserved address 0x12598

// Reserved address 0x1259c

// Reserved address 0x125a0

// Reserved address 0x125a4

// Reserved address 0x125a8

// Reserved address 0x125ac

// Reserved address 0x125b0

// Reserved address 0x125b4

// Reserved address 0x125b8

// Reserved address 0x125bc

// Reserved address 0x125c0

// Reserved address 0x125c4

// Reserved address 0x125c8

// Reserved address 0x125cc

// Reserved address 0x125d0

// Reserved address 0x125d4

// Reserved address 0x125d8

// Reserved address 0x125dc

// Reserved address 0x125e0

// Reserved address 0x125e4

// Reserved address 0x125e8

// Reserved address 0x125ec

// Reserved address 0x125f0

// Reserved address 0x125f4

// Reserved address 0x125f8

// Reserved address 0x125fc

// Register GPIO_Q_ENABLE_CONFIG_00_0
#define GPIO_Q_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12600)
#define GPIO_Q_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_SCR                   GPIO_Q_SCR_00_0
#define GPIO_Q_ENABLE_CONFIG_00_0_SCRREG                        GPIO_Q_SCR_00_0
#define GPIO_Q_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_00_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12604)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Q_SCR_00_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_Q_SCR_00_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_00_0
#define GPIO_Q_INPUT_00_0                       MK_ADDR_CONST(0x12608)
#define GPIO_Q_INPUT_00_0_SECURE                        0x0
#define GPIO_Q_INPUT_00_0_DUAL                  0x0
#define GPIO_Q_INPUT_00_0_SCR                   GPIO_Q_SCR_00_0
#define GPIO_Q_INPUT_00_0_SCRREG                        GPIO_Q_SCR_00_0
#define GPIO_Q_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_00_0
#define GPIO_Q_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1260c)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_00_0_SCR                  GPIO_Q_SCR_00_0
#define GPIO_Q_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_Q_SCR_00_0
#define GPIO_Q_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_00_0
#define GPIO_Q_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12610)
#define GPIO_Q_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_00_0_SCR                    GPIO_Q_SCR_00_0
#define GPIO_Q_OUTPUT_VALUE_00_0_SCRREG                         GPIO_Q_SCR_00_0
#define GPIO_Q_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_00_0
#define GPIO_Q_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12614)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Q_SCR_00_0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_Q_SCR_00_0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12618

// Reserved address 0x1261c

// Register GPIO_Q_ENABLE_CONFIG_01_0
#define GPIO_Q_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12620)
#define GPIO_Q_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_SCR                   GPIO_Q_SCR_01_0
#define GPIO_Q_ENABLE_CONFIG_01_0_SCRREG                        GPIO_Q_SCR_01_0
#define GPIO_Q_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_01_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12624)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Q_SCR_01_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_Q_SCR_01_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_01_0
#define GPIO_Q_INPUT_01_0                       MK_ADDR_CONST(0x12628)
#define GPIO_Q_INPUT_01_0_SECURE                        0x0
#define GPIO_Q_INPUT_01_0_DUAL                  0x0
#define GPIO_Q_INPUT_01_0_SCR                   GPIO_Q_SCR_01_0
#define GPIO_Q_INPUT_01_0_SCRREG                        GPIO_Q_SCR_01_0
#define GPIO_Q_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_01_0
#define GPIO_Q_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1262c)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_01_0_SCR                  GPIO_Q_SCR_01_0
#define GPIO_Q_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_Q_SCR_01_0
#define GPIO_Q_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_01_0
#define GPIO_Q_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12630)
#define GPIO_Q_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_01_0_SCR                    GPIO_Q_SCR_01_0
#define GPIO_Q_OUTPUT_VALUE_01_0_SCRREG                         GPIO_Q_SCR_01_0
#define GPIO_Q_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_01_0
#define GPIO_Q_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12634)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Q_SCR_01_0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_Q_SCR_01_0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12638

// Reserved address 0x1263c

// Register GPIO_Q_ENABLE_CONFIG_02_0
#define GPIO_Q_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12640)
#define GPIO_Q_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_SCR                   GPIO_Q_SCR_02_0
#define GPIO_Q_ENABLE_CONFIG_02_0_SCRREG                        GPIO_Q_SCR_02_0
#define GPIO_Q_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_02_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12644)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Q_SCR_02_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_Q_SCR_02_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_02_0
#define GPIO_Q_INPUT_02_0                       MK_ADDR_CONST(0x12648)
#define GPIO_Q_INPUT_02_0_SECURE                        0x0
#define GPIO_Q_INPUT_02_0_DUAL                  0x0
#define GPIO_Q_INPUT_02_0_SCR                   GPIO_Q_SCR_02_0
#define GPIO_Q_INPUT_02_0_SCRREG                        GPIO_Q_SCR_02_0
#define GPIO_Q_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_02_0
#define GPIO_Q_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1264c)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_02_0_SCR                  GPIO_Q_SCR_02_0
#define GPIO_Q_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_Q_SCR_02_0
#define GPIO_Q_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_02_0
#define GPIO_Q_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12650)
#define GPIO_Q_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_02_0_SCR                    GPIO_Q_SCR_02_0
#define GPIO_Q_OUTPUT_VALUE_02_0_SCRREG                         GPIO_Q_SCR_02_0
#define GPIO_Q_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_02_0
#define GPIO_Q_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12654)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Q_SCR_02_0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_Q_SCR_02_0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12658

// Reserved address 0x1265c

// Register GPIO_Q_ENABLE_CONFIG_03_0
#define GPIO_Q_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12660)
#define GPIO_Q_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_SCR                   GPIO_Q_SCR_03_0
#define GPIO_Q_ENABLE_CONFIG_03_0_SCRREG                        GPIO_Q_SCR_03_0
#define GPIO_Q_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_03_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12664)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Q_SCR_03_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_Q_SCR_03_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_03_0
#define GPIO_Q_INPUT_03_0                       MK_ADDR_CONST(0x12668)
#define GPIO_Q_INPUT_03_0_SECURE                        0x0
#define GPIO_Q_INPUT_03_0_DUAL                  0x0
#define GPIO_Q_INPUT_03_0_SCR                   GPIO_Q_SCR_03_0
#define GPIO_Q_INPUT_03_0_SCRREG                        GPIO_Q_SCR_03_0
#define GPIO_Q_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_03_0
#define GPIO_Q_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1266c)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_03_0_SCR                  GPIO_Q_SCR_03_0
#define GPIO_Q_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_Q_SCR_03_0
#define GPIO_Q_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_03_0
#define GPIO_Q_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12670)
#define GPIO_Q_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_03_0_SCR                    GPIO_Q_SCR_03_0
#define GPIO_Q_OUTPUT_VALUE_03_0_SCRREG                         GPIO_Q_SCR_03_0
#define GPIO_Q_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_03_0
#define GPIO_Q_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12674)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Q_SCR_03_0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_Q_SCR_03_0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12678

// Reserved address 0x1267c

// Register GPIO_Q_ENABLE_CONFIG_04_0
#define GPIO_Q_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12680)
#define GPIO_Q_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_SCR                   GPIO_Q_SCR_04_0
#define GPIO_Q_ENABLE_CONFIG_04_0_SCRREG                        GPIO_Q_SCR_04_0
#define GPIO_Q_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_04_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12684)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Q_SCR_04_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_Q_SCR_04_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_04_0
#define GPIO_Q_INPUT_04_0                       MK_ADDR_CONST(0x12688)
#define GPIO_Q_INPUT_04_0_SECURE                        0x0
#define GPIO_Q_INPUT_04_0_DUAL                  0x0
#define GPIO_Q_INPUT_04_0_SCR                   GPIO_Q_SCR_04_0
#define GPIO_Q_INPUT_04_0_SCRREG                        GPIO_Q_SCR_04_0
#define GPIO_Q_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_04_0
#define GPIO_Q_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1268c)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_04_0_SCR                  GPIO_Q_SCR_04_0
#define GPIO_Q_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_Q_SCR_04_0
#define GPIO_Q_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_04_0
#define GPIO_Q_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12690)
#define GPIO_Q_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_04_0_SCR                    GPIO_Q_SCR_04_0
#define GPIO_Q_OUTPUT_VALUE_04_0_SCRREG                         GPIO_Q_SCR_04_0
#define GPIO_Q_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_04_0
#define GPIO_Q_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12694)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Q_SCR_04_0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_Q_SCR_04_0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12698

// Reserved address 0x1269c

// Register GPIO_Q_ENABLE_CONFIG_05_0
#define GPIO_Q_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x126a0)
#define GPIO_Q_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_SCR                   GPIO_Q_SCR_05_0
#define GPIO_Q_ENABLE_CONFIG_05_0_SCRREG                        GPIO_Q_SCR_05_0
#define GPIO_Q_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_05_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x126a4)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Q_SCR_05_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_Q_SCR_05_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_05_0
#define GPIO_Q_INPUT_05_0                       MK_ADDR_CONST(0x126a8)
#define GPIO_Q_INPUT_05_0_SECURE                        0x0
#define GPIO_Q_INPUT_05_0_DUAL                  0x0
#define GPIO_Q_INPUT_05_0_SCR                   GPIO_Q_SCR_05_0
#define GPIO_Q_INPUT_05_0_SCRREG                        GPIO_Q_SCR_05_0
#define GPIO_Q_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_05_0
#define GPIO_Q_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x126ac)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_05_0_SCR                  GPIO_Q_SCR_05_0
#define GPIO_Q_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_Q_SCR_05_0
#define GPIO_Q_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_05_0
#define GPIO_Q_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x126b0)
#define GPIO_Q_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_05_0_SCR                    GPIO_Q_SCR_05_0
#define GPIO_Q_OUTPUT_VALUE_05_0_SCRREG                         GPIO_Q_SCR_05_0
#define GPIO_Q_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_05_0
#define GPIO_Q_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x126b4)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Q_SCR_05_0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_Q_SCR_05_0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x126b8

// Reserved address 0x126bc

// Register GPIO_Q_ENABLE_CONFIG_06_0
#define GPIO_Q_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x126c0)
#define GPIO_Q_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_SCR                   GPIO_Q_SCR_06_0
#define GPIO_Q_ENABLE_CONFIG_06_0_SCRREG                        GPIO_Q_SCR_06_0
#define GPIO_Q_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_06_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x126c4)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Q_SCR_06_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_Q_SCR_06_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_06_0
#define GPIO_Q_INPUT_06_0                       MK_ADDR_CONST(0x126c8)
#define GPIO_Q_INPUT_06_0_SECURE                        0x0
#define GPIO_Q_INPUT_06_0_DUAL                  0x0
#define GPIO_Q_INPUT_06_0_SCR                   GPIO_Q_SCR_06_0
#define GPIO_Q_INPUT_06_0_SCRREG                        GPIO_Q_SCR_06_0
#define GPIO_Q_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_06_0
#define GPIO_Q_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x126cc)
#define GPIO_Q_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_06_0_SCR                  GPIO_Q_SCR_06_0
#define GPIO_Q_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_Q_SCR_06_0
#define GPIO_Q_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_06_0
#define GPIO_Q_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x126d0)
#define GPIO_Q_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_06_0_SCR                    GPIO_Q_SCR_06_0
#define GPIO_Q_OUTPUT_VALUE_06_0_SCRREG                         GPIO_Q_SCR_06_0
#define GPIO_Q_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_06_0
#define GPIO_Q_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x126d4)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Q_SCR_06_0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_Q_SCR_06_0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x126d8

// Reserved address 0x126dc

// Register GPIO_Q_ENABLE_CONFIG_07_0
#define GPIO_Q_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x126e0)
#define GPIO_Q_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_SCR                   GPIO_Q_SCR_07_0
#define GPIO_Q_ENABLE_CONFIG_07_0_SCRREG                        GPIO_Q_SCR_07_0
#define GPIO_Q_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_Q_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_Q_DEBOUNCE_THRESHOLD_07_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x126e4)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Q_SCR_07_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_Q_SCR_07_0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_INPUT_07_0
#define GPIO_Q_INPUT_07_0                       MK_ADDR_CONST(0x126e8)
#define GPIO_Q_INPUT_07_0_SECURE                        0x0
#define GPIO_Q_INPUT_07_0_DUAL                  0x0
#define GPIO_Q_INPUT_07_0_SCR                   GPIO_Q_SCR_07_0
#define GPIO_Q_INPUT_07_0_SCRREG                        GPIO_Q_SCR_07_0
#define GPIO_Q_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_Q_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_Q_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_Q_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_Q_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_Q_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_Q_OUTPUT_CONTROL_07_0
#define GPIO_Q_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x126ec)
#define GPIO_Q_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_Q_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_Q_OUTPUT_CONTROL_07_0_SCR                  GPIO_Q_SCR_07_0
#define GPIO_Q_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_Q_SCR_07_0
#define GPIO_Q_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_Q_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_Q_OUTPUT_VALUE_07_0
#define GPIO_Q_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x126f0)
#define GPIO_Q_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_Q_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_Q_OUTPUT_VALUE_07_0_SCR                    GPIO_Q_SCR_07_0
#define GPIO_Q_OUTPUT_VALUE_07_0_SCRREG                         GPIO_Q_SCR_07_0
#define GPIO_Q_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_Q_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_CLEAR_07_0
#define GPIO_Q_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x126f4)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Q_SCR_07_0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_Q_SCR_07_0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_Q_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x126f8

// Reserved address 0x126fc

// Register GPIO_Q_INTERRUPT_STATUS_G0_0
#define GPIO_Q_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12700)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G1_0
#define GPIO_Q_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12704)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G2_0
#define GPIO_Q_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12708)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G3_0
#define GPIO_Q_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1270c)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G4_0
#define GPIO_Q_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12710)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G5_0
#define GPIO_Q_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12714)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G6_0
#define GPIO_Q_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12718)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_Q_INTERRUPT_STATUS_G7_0
#define GPIO_Q_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1271c)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_Q_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x12720

// Reserved address 0x12724

// Reserved address 0x12728

// Reserved address 0x1272c

// Reserved address 0x12730

// Reserved address 0x12734

// Reserved address 0x12738

// Reserved address 0x1273c

// Reserved address 0x12740

// Reserved address 0x12744

// Reserved address 0x12748

// Reserved address 0x1274c

// Reserved address 0x12750

// Reserved address 0x12754

// Reserved address 0x12758

// Reserved address 0x1275c

// Reserved address 0x12760

// Reserved address 0x12764

// Reserved address 0x12768

// Reserved address 0x1276c

// Reserved address 0x12770

// Reserved address 0x12774

// Reserved address 0x12778

// Reserved address 0x1277c

// Reserved address 0x12780

// Reserved address 0x12784

// Reserved address 0x12788

// Reserved address 0x1278c

// Reserved address 0x12790

// Reserved address 0x12794

// Reserved address 0x12798

// Reserved address 0x1279c

// Reserved address 0x127a0

// Reserved address 0x127a4

// Reserved address 0x127a8

// Reserved address 0x127ac

// Reserved address 0x127b0

// Reserved address 0x127b4

// Reserved address 0x127b8

// Reserved address 0x127bc

// Reserved address 0x127c0

// Reserved address 0x127c4

// Reserved address 0x127c8

// Reserved address 0x127cc

// Reserved address 0x127d0

// Reserved address 0x127d4

// Reserved address 0x127d8

// Reserved address 0x127dc

// Reserved address 0x127e0

// Reserved address 0x127e4

// Reserved address 0x127e8

// Reserved address 0x127ec

// Reserved address 0x127f0

// Reserved address 0x127f4

// Reserved address 0x127f8

// Reserved address 0x127fc

// Register GPIO_R_ENABLE_CONFIG_00_0
#define GPIO_R_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12800)
#define GPIO_R_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_00_0_SCR                   GPIO_R_SCR_00_0
#define GPIO_R_ENABLE_CONFIG_00_0_SCRREG                        GPIO_R_SCR_00_0
#define GPIO_R_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_00_0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12804)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_R_SCR_00_0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_R_SCR_00_0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_00_0
#define GPIO_R_INPUT_00_0                       MK_ADDR_CONST(0x12808)
#define GPIO_R_INPUT_00_0_SECURE                        0x0
#define GPIO_R_INPUT_00_0_DUAL                  0x0
#define GPIO_R_INPUT_00_0_SCR                   GPIO_R_SCR_00_0
#define GPIO_R_INPUT_00_0_SCRREG                        GPIO_R_SCR_00_0
#define GPIO_R_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_00_0
#define GPIO_R_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1280c)
#define GPIO_R_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_00_0_SCR                  GPIO_R_SCR_00_0
#define GPIO_R_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_R_SCR_00_0
#define GPIO_R_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_00_0
#define GPIO_R_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12810)
#define GPIO_R_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_00_0_SCR                    GPIO_R_SCR_00_0
#define GPIO_R_OUTPUT_VALUE_00_0_SCRREG                         GPIO_R_SCR_00_0
#define GPIO_R_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_00_0
#define GPIO_R_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12814)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_00_0_SCR                         GPIO_R_SCR_00_0
#define GPIO_R_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_R_SCR_00_0
#define GPIO_R_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12818

// Reserved address 0x1281c

// Register GPIO_R_ENABLE_CONFIG_01_0
#define GPIO_R_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12820)
#define GPIO_R_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_01_0_SCR                   GPIO_R_SCR_01_0
#define GPIO_R_ENABLE_CONFIG_01_0_SCRREG                        GPIO_R_SCR_01_0
#define GPIO_R_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_01_0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12824)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_R_SCR_01_0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_R_SCR_01_0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_01_0
#define GPIO_R_INPUT_01_0                       MK_ADDR_CONST(0x12828)
#define GPIO_R_INPUT_01_0_SECURE                        0x0
#define GPIO_R_INPUT_01_0_DUAL                  0x0
#define GPIO_R_INPUT_01_0_SCR                   GPIO_R_SCR_01_0
#define GPIO_R_INPUT_01_0_SCRREG                        GPIO_R_SCR_01_0
#define GPIO_R_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_01_0
#define GPIO_R_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1282c)
#define GPIO_R_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_01_0_SCR                  GPIO_R_SCR_01_0
#define GPIO_R_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_R_SCR_01_0
#define GPIO_R_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_01_0
#define GPIO_R_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12830)
#define GPIO_R_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_01_0_SCR                    GPIO_R_SCR_01_0
#define GPIO_R_OUTPUT_VALUE_01_0_SCRREG                         GPIO_R_SCR_01_0
#define GPIO_R_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_01_0
#define GPIO_R_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12834)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_01_0_SCR                         GPIO_R_SCR_01_0
#define GPIO_R_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_R_SCR_01_0
#define GPIO_R_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12838

// Reserved address 0x1283c

// Register GPIO_R_ENABLE_CONFIG_02_0
#define GPIO_R_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12840)
#define GPIO_R_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_02_0_SCR                   GPIO_R_SCR_02_0
#define GPIO_R_ENABLE_CONFIG_02_0_SCRREG                        GPIO_R_SCR_02_0
#define GPIO_R_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_02_0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12844)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_R_SCR_02_0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_R_SCR_02_0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_02_0
#define GPIO_R_INPUT_02_0                       MK_ADDR_CONST(0x12848)
#define GPIO_R_INPUT_02_0_SECURE                        0x0
#define GPIO_R_INPUT_02_0_DUAL                  0x0
#define GPIO_R_INPUT_02_0_SCR                   GPIO_R_SCR_02_0
#define GPIO_R_INPUT_02_0_SCRREG                        GPIO_R_SCR_02_0
#define GPIO_R_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_02_0
#define GPIO_R_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1284c)
#define GPIO_R_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_02_0_SCR                  GPIO_R_SCR_02_0
#define GPIO_R_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_R_SCR_02_0
#define GPIO_R_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_02_0
#define GPIO_R_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12850)
#define GPIO_R_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_02_0_SCR                    GPIO_R_SCR_02_0
#define GPIO_R_OUTPUT_VALUE_02_0_SCRREG                         GPIO_R_SCR_02_0
#define GPIO_R_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_02_0
#define GPIO_R_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12854)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_02_0_SCR                         GPIO_R_SCR_02_0
#define GPIO_R_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_R_SCR_02_0
#define GPIO_R_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12858

// Reserved address 0x1285c

// Register GPIO_R_ENABLE_CONFIG_03_0
#define GPIO_R_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12860)
#define GPIO_R_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_03_0_SCR                   GPIO_R_SCR_03_0
#define GPIO_R_ENABLE_CONFIG_03_0_SCRREG                        GPIO_R_SCR_03_0
#define GPIO_R_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_03_0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12864)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_R_SCR_03_0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_R_SCR_03_0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_03_0
#define GPIO_R_INPUT_03_0                       MK_ADDR_CONST(0x12868)
#define GPIO_R_INPUT_03_0_SECURE                        0x0
#define GPIO_R_INPUT_03_0_DUAL                  0x0
#define GPIO_R_INPUT_03_0_SCR                   GPIO_R_SCR_03_0
#define GPIO_R_INPUT_03_0_SCRREG                        GPIO_R_SCR_03_0
#define GPIO_R_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_03_0
#define GPIO_R_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1286c)
#define GPIO_R_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_03_0_SCR                  GPIO_R_SCR_03_0
#define GPIO_R_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_R_SCR_03_0
#define GPIO_R_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_03_0
#define GPIO_R_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12870)
#define GPIO_R_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_03_0_SCR                    GPIO_R_SCR_03_0
#define GPIO_R_OUTPUT_VALUE_03_0_SCRREG                         GPIO_R_SCR_03_0
#define GPIO_R_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_03_0
#define GPIO_R_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12874)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_03_0_SCR                         GPIO_R_SCR_03_0
#define GPIO_R_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_R_SCR_03_0
#define GPIO_R_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12878

// Reserved address 0x1287c

// Register GPIO_R_ENABLE_CONFIG_04_0
#define GPIO_R_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12880)
#define GPIO_R_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_04_0_SCR                   GPIO_R_SCR_04_0
#define GPIO_R_ENABLE_CONFIG_04_0_SCRREG                        GPIO_R_SCR_04_0
#define GPIO_R_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_04_0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12884)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_R_SCR_04_0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_R_SCR_04_0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_04_0
#define GPIO_R_INPUT_04_0                       MK_ADDR_CONST(0x12888)
#define GPIO_R_INPUT_04_0_SECURE                        0x0
#define GPIO_R_INPUT_04_0_DUAL                  0x0
#define GPIO_R_INPUT_04_0_SCR                   GPIO_R_SCR_04_0
#define GPIO_R_INPUT_04_0_SCRREG                        GPIO_R_SCR_04_0
#define GPIO_R_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_04_0
#define GPIO_R_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1288c)
#define GPIO_R_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_04_0_SCR                  GPIO_R_SCR_04_0
#define GPIO_R_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_R_SCR_04_0
#define GPIO_R_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_04_0
#define GPIO_R_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12890)
#define GPIO_R_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_04_0_SCR                    GPIO_R_SCR_04_0
#define GPIO_R_OUTPUT_VALUE_04_0_SCRREG                         GPIO_R_SCR_04_0
#define GPIO_R_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_04_0
#define GPIO_R_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12894)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_04_0_SCR                         GPIO_R_SCR_04_0
#define GPIO_R_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_R_SCR_04_0
#define GPIO_R_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x12898

// Reserved address 0x1289c

// Register GPIO_R_ENABLE_CONFIG_05_0
#define GPIO_R_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x128a0)
#define GPIO_R_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_R_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_R_ENABLE_CONFIG_05_0_SCR                   GPIO_R_SCR_05_0
#define GPIO_R_ENABLE_CONFIG_05_0_SCRREG                        GPIO_R_SCR_05_0
#define GPIO_R_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_R_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_R_DEBOUNCE_THRESHOLD_05_0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x128a4)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_R_SCR_05_0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_R_SCR_05_0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_INPUT_05_0
#define GPIO_R_INPUT_05_0                       MK_ADDR_CONST(0x128a8)
#define GPIO_R_INPUT_05_0_SECURE                        0x0
#define GPIO_R_INPUT_05_0_DUAL                  0x0
#define GPIO_R_INPUT_05_0_SCR                   GPIO_R_SCR_05_0
#define GPIO_R_INPUT_05_0_SCRREG                        GPIO_R_SCR_05_0
#define GPIO_R_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_R_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_R_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_R_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_R_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_R_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_R_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_R_OUTPUT_CONTROL_05_0
#define GPIO_R_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x128ac)
#define GPIO_R_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_R_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_R_OUTPUT_CONTROL_05_0_SCR                  GPIO_R_SCR_05_0
#define GPIO_R_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_R_SCR_05_0
#define GPIO_R_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_R_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_R_OUTPUT_VALUE_05_0
#define GPIO_R_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x128b0)
#define GPIO_R_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_R_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_R_OUTPUT_VALUE_05_0_SCR                    GPIO_R_SCR_05_0
#define GPIO_R_OUTPUT_VALUE_05_0_SCRREG                         GPIO_R_SCR_05_0
#define GPIO_R_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_R_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_CLEAR_05_0
#define GPIO_R_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x128b4)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_R_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_R_INTERRUPT_CLEAR_05_0_SCR                         GPIO_R_SCR_05_0
#define GPIO_R_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_R_SCR_05_0
#define GPIO_R_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_R_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x128b8

// Reserved address 0x128bc

// Reserved address 0x128c0

// Reserved address 0x128c4

// Reserved address 0x128c8

// Reserved address 0x128cc

// Reserved address 0x128d0

// Reserved address 0x128d4

// Reserved address 0x128d8

// Reserved address 0x128dc

// Reserved address 0x128e0

// Reserved address 0x128e4

// Reserved address 0x128e8

// Reserved address 0x128ec

// Reserved address 0x128f0

// Reserved address 0x128f4

// Reserved address 0x128f8

// Reserved address 0x128fc

// Register GPIO_R_INTERRUPT_STATUS_G0_0
#define GPIO_R_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12900)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_R_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G1_0
#define GPIO_R_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12904)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_R_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G2_0
#define GPIO_R_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12908)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_R_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G3_0
#define GPIO_R_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1290c)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_R_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G4_0
#define GPIO_R_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12910)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_R_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G5_0
#define GPIO_R_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12914)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_R_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G6_0
#define GPIO_R_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12918)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_R_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_R_INTERRUPT_STATUS_G7_0
#define GPIO_R_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1291c)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_R_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_R_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_R_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_R_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_R_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x12920

// Reserved address 0x12924

// Reserved address 0x12928

// Reserved address 0x1292c

// Reserved address 0x12930

// Reserved address 0x12934

// Reserved address 0x12938

// Reserved address 0x1293c

// Reserved address 0x12940

// Reserved address 0x12944

// Reserved address 0x12948

// Reserved address 0x1294c

// Reserved address 0x12950

// Reserved address 0x12954

// Reserved address 0x12958

// Reserved address 0x1295c

// Reserved address 0x12960

// Reserved address 0x12964

// Reserved address 0x12968

// Reserved address 0x1296c

// Reserved address 0x12970

// Reserved address 0x12974

// Reserved address 0x12978

// Reserved address 0x1297c

// Reserved address 0x12980

// Reserved address 0x12984

// Reserved address 0x12988

// Reserved address 0x1298c

// Reserved address 0x12990

// Reserved address 0x12994

// Reserved address 0x12998

// Reserved address 0x1299c

// Reserved address 0x129a0

// Reserved address 0x129a4

// Reserved address 0x129a8

// Reserved address 0x129ac

// Reserved address 0x129b0

// Reserved address 0x129b4

// Reserved address 0x129b8

// Reserved address 0x129bc

// Reserved address 0x129c0

// Reserved address 0x129c4

// Reserved address 0x129c8

// Reserved address 0x129cc

// Reserved address 0x129d0

// Reserved address 0x129d4

// Reserved address 0x129d8

// Reserved address 0x129dc

// Reserved address 0x129e0

// Reserved address 0x129e4

// Reserved address 0x129e8

// Reserved address 0x129ec

// Reserved address 0x129f0

// Reserved address 0x129f4

// Reserved address 0x129f8

// Reserved address 0x129fc

// Register GPIO_K_ENABLE_CONFIG_00_0
#define GPIO_K_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x13000)
#define GPIO_K_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_00_0_SCR                   GPIO_K_SCR_00_0
#define GPIO_K_ENABLE_CONFIG_00_0_SCRREG                        GPIO_K_SCR_00_0
#define GPIO_K_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_00_0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x13004)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_K_SCR_00_0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_K_SCR_00_0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_00_0
#define GPIO_K_INPUT_00_0                       MK_ADDR_CONST(0x13008)
#define GPIO_K_INPUT_00_0_SECURE                        0x0
#define GPIO_K_INPUT_00_0_DUAL                  0x0
#define GPIO_K_INPUT_00_0_SCR                   GPIO_K_SCR_00_0
#define GPIO_K_INPUT_00_0_SCRREG                        GPIO_K_SCR_00_0
#define GPIO_K_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_00_0
#define GPIO_K_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1300c)
#define GPIO_K_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_00_0_SCR                  GPIO_K_SCR_00_0
#define GPIO_K_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_K_SCR_00_0
#define GPIO_K_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_00_0
#define GPIO_K_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x13010)
#define GPIO_K_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_00_0_SCR                    GPIO_K_SCR_00_0
#define GPIO_K_OUTPUT_VALUE_00_0_SCRREG                         GPIO_K_SCR_00_0
#define GPIO_K_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_00_0
#define GPIO_K_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x13014)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_00_0_SCR                         GPIO_K_SCR_00_0
#define GPIO_K_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_K_SCR_00_0
#define GPIO_K_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13018

// Reserved address 0x1301c

// Register GPIO_K_ENABLE_CONFIG_01_0
#define GPIO_K_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x13020)
#define GPIO_K_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_01_0_SCR                   GPIO_K_SCR_01_0
#define GPIO_K_ENABLE_CONFIG_01_0_SCRREG                        GPIO_K_SCR_01_0
#define GPIO_K_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_01_0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x13024)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_K_SCR_01_0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_K_SCR_01_0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_01_0
#define GPIO_K_INPUT_01_0                       MK_ADDR_CONST(0x13028)
#define GPIO_K_INPUT_01_0_SECURE                        0x0
#define GPIO_K_INPUT_01_0_DUAL                  0x0
#define GPIO_K_INPUT_01_0_SCR                   GPIO_K_SCR_01_0
#define GPIO_K_INPUT_01_0_SCRREG                        GPIO_K_SCR_01_0
#define GPIO_K_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_01_0
#define GPIO_K_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1302c)
#define GPIO_K_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_01_0_SCR                  GPIO_K_SCR_01_0
#define GPIO_K_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_K_SCR_01_0
#define GPIO_K_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_01_0
#define GPIO_K_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x13030)
#define GPIO_K_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_01_0_SCR                    GPIO_K_SCR_01_0
#define GPIO_K_OUTPUT_VALUE_01_0_SCRREG                         GPIO_K_SCR_01_0
#define GPIO_K_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_01_0
#define GPIO_K_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x13034)
#define GPIO_K_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_01_0_SCR                         GPIO_K_SCR_01_0
#define GPIO_K_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_K_SCR_01_0
#define GPIO_K_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13038

// Reserved address 0x1303c

// Register GPIO_K_ENABLE_CONFIG_02_0
#define GPIO_K_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x13040)
#define GPIO_K_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_02_0_SCR                   GPIO_K_SCR_02_0
#define GPIO_K_ENABLE_CONFIG_02_0_SCRREG                        GPIO_K_SCR_02_0
#define GPIO_K_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_02_0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x13044)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_K_SCR_02_0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_K_SCR_02_0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_02_0
#define GPIO_K_INPUT_02_0                       MK_ADDR_CONST(0x13048)
#define GPIO_K_INPUT_02_0_SECURE                        0x0
#define GPIO_K_INPUT_02_0_DUAL                  0x0
#define GPIO_K_INPUT_02_0_SCR                   GPIO_K_SCR_02_0
#define GPIO_K_INPUT_02_0_SCRREG                        GPIO_K_SCR_02_0
#define GPIO_K_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_02_0
#define GPIO_K_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1304c)
#define GPIO_K_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_02_0_SCR                  GPIO_K_SCR_02_0
#define GPIO_K_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_K_SCR_02_0
#define GPIO_K_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_02_0
#define GPIO_K_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x13050)
#define GPIO_K_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_02_0_SCR                    GPIO_K_SCR_02_0
#define GPIO_K_OUTPUT_VALUE_02_0_SCRREG                         GPIO_K_SCR_02_0
#define GPIO_K_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_02_0
#define GPIO_K_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x13054)
#define GPIO_K_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_02_0_SCR                         GPIO_K_SCR_02_0
#define GPIO_K_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_K_SCR_02_0
#define GPIO_K_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13058

// Reserved address 0x1305c

// Register GPIO_K_ENABLE_CONFIG_03_0
#define GPIO_K_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x13060)
#define GPIO_K_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_03_0_SCR                   GPIO_K_SCR_03_0
#define GPIO_K_ENABLE_CONFIG_03_0_SCRREG                        GPIO_K_SCR_03_0
#define GPIO_K_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_03_0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x13064)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_K_SCR_03_0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_K_SCR_03_0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_03_0
#define GPIO_K_INPUT_03_0                       MK_ADDR_CONST(0x13068)
#define GPIO_K_INPUT_03_0_SECURE                        0x0
#define GPIO_K_INPUT_03_0_DUAL                  0x0
#define GPIO_K_INPUT_03_0_SCR                   GPIO_K_SCR_03_0
#define GPIO_K_INPUT_03_0_SCRREG                        GPIO_K_SCR_03_0
#define GPIO_K_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_03_0
#define GPIO_K_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1306c)
#define GPIO_K_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_03_0_SCR                  GPIO_K_SCR_03_0
#define GPIO_K_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_K_SCR_03_0
#define GPIO_K_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_03_0
#define GPIO_K_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x13070)
#define GPIO_K_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_03_0_SCR                    GPIO_K_SCR_03_0
#define GPIO_K_OUTPUT_VALUE_03_0_SCRREG                         GPIO_K_SCR_03_0
#define GPIO_K_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_03_0
#define GPIO_K_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x13074)
#define GPIO_K_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_03_0_SCR                         GPIO_K_SCR_03_0
#define GPIO_K_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_K_SCR_03_0
#define GPIO_K_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13078

// Reserved address 0x1307c

// Register GPIO_K_ENABLE_CONFIG_04_0
#define GPIO_K_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x13080)
#define GPIO_K_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_04_0_SCR                   GPIO_K_SCR_04_0
#define GPIO_K_ENABLE_CONFIG_04_0_SCRREG                        GPIO_K_SCR_04_0
#define GPIO_K_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_04_0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x13084)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_K_SCR_04_0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_K_SCR_04_0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_04_0
#define GPIO_K_INPUT_04_0                       MK_ADDR_CONST(0x13088)
#define GPIO_K_INPUT_04_0_SECURE                        0x0
#define GPIO_K_INPUT_04_0_DUAL                  0x0
#define GPIO_K_INPUT_04_0_SCR                   GPIO_K_SCR_04_0
#define GPIO_K_INPUT_04_0_SCRREG                        GPIO_K_SCR_04_0
#define GPIO_K_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_04_0
#define GPIO_K_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1308c)
#define GPIO_K_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_04_0_SCR                  GPIO_K_SCR_04_0
#define GPIO_K_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_K_SCR_04_0
#define GPIO_K_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_04_0
#define GPIO_K_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x13090)
#define GPIO_K_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_04_0_SCR                    GPIO_K_SCR_04_0
#define GPIO_K_OUTPUT_VALUE_04_0_SCRREG                         GPIO_K_SCR_04_0
#define GPIO_K_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_04_0
#define GPIO_K_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x13094)
#define GPIO_K_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_04_0_SCR                         GPIO_K_SCR_04_0
#define GPIO_K_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_K_SCR_04_0
#define GPIO_K_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13098

// Reserved address 0x1309c

// Register GPIO_K_ENABLE_CONFIG_05_0
#define GPIO_K_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x130a0)
#define GPIO_K_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_05_0_SCR                   GPIO_K_SCR_05_0
#define GPIO_K_ENABLE_CONFIG_05_0_SCRREG                        GPIO_K_SCR_05_0
#define GPIO_K_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_05_0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x130a4)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_K_SCR_05_0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_K_SCR_05_0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_05_0
#define GPIO_K_INPUT_05_0                       MK_ADDR_CONST(0x130a8)
#define GPIO_K_INPUT_05_0_SECURE                        0x0
#define GPIO_K_INPUT_05_0_DUAL                  0x0
#define GPIO_K_INPUT_05_0_SCR                   GPIO_K_SCR_05_0
#define GPIO_K_INPUT_05_0_SCRREG                        GPIO_K_SCR_05_0
#define GPIO_K_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_05_0
#define GPIO_K_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x130ac)
#define GPIO_K_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_05_0_SCR                  GPIO_K_SCR_05_0
#define GPIO_K_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_K_SCR_05_0
#define GPIO_K_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_05_0
#define GPIO_K_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x130b0)
#define GPIO_K_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_05_0_SCR                    GPIO_K_SCR_05_0
#define GPIO_K_OUTPUT_VALUE_05_0_SCRREG                         GPIO_K_SCR_05_0
#define GPIO_K_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_05_0
#define GPIO_K_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x130b4)
#define GPIO_K_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_05_0_SCR                         GPIO_K_SCR_05_0
#define GPIO_K_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_K_SCR_05_0
#define GPIO_K_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x130b8

// Reserved address 0x130bc

// Register GPIO_K_ENABLE_CONFIG_06_0
#define GPIO_K_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x130c0)
#define GPIO_K_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_06_0_SCR                   GPIO_K_SCR_06_0
#define GPIO_K_ENABLE_CONFIG_06_0_SCRREG                        GPIO_K_SCR_06_0
#define GPIO_K_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_06_0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x130c4)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_K_SCR_06_0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_K_SCR_06_0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_06_0
#define GPIO_K_INPUT_06_0                       MK_ADDR_CONST(0x130c8)
#define GPIO_K_INPUT_06_0_SECURE                        0x0
#define GPIO_K_INPUT_06_0_DUAL                  0x0
#define GPIO_K_INPUT_06_0_SCR                   GPIO_K_SCR_06_0
#define GPIO_K_INPUT_06_0_SCRREG                        GPIO_K_SCR_06_0
#define GPIO_K_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_06_0
#define GPIO_K_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x130cc)
#define GPIO_K_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_06_0_SCR                  GPIO_K_SCR_06_0
#define GPIO_K_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_K_SCR_06_0
#define GPIO_K_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_06_0
#define GPIO_K_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x130d0)
#define GPIO_K_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_06_0_SCR                    GPIO_K_SCR_06_0
#define GPIO_K_OUTPUT_VALUE_06_0_SCRREG                         GPIO_K_SCR_06_0
#define GPIO_K_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_06_0
#define GPIO_K_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x130d4)
#define GPIO_K_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_06_0_SCR                         GPIO_K_SCR_06_0
#define GPIO_K_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_K_SCR_06_0
#define GPIO_K_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x130d8

// Reserved address 0x130dc

// Register GPIO_K_ENABLE_CONFIG_07_0
#define GPIO_K_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x130e0)
#define GPIO_K_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_K_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_K_ENABLE_CONFIG_07_0_SCR                   GPIO_K_SCR_07_0
#define GPIO_K_ENABLE_CONFIG_07_0_SCRREG                        GPIO_K_SCR_07_0
#define GPIO_K_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_K_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_K_DEBOUNCE_THRESHOLD_07_0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x130e4)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_K_SCR_07_0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_K_SCR_07_0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_INPUT_07_0
#define GPIO_K_INPUT_07_0                       MK_ADDR_CONST(0x130e8)
#define GPIO_K_INPUT_07_0_SECURE                        0x0
#define GPIO_K_INPUT_07_0_DUAL                  0x0
#define GPIO_K_INPUT_07_0_SCR                   GPIO_K_SCR_07_0
#define GPIO_K_INPUT_07_0_SCRREG                        GPIO_K_SCR_07_0
#define GPIO_K_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_K_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_K_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_K_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_K_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_K_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_K_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_K_OUTPUT_CONTROL_07_0
#define GPIO_K_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x130ec)
#define GPIO_K_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_K_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_K_OUTPUT_CONTROL_07_0_SCR                  GPIO_K_SCR_07_0
#define GPIO_K_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_K_SCR_07_0
#define GPIO_K_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_K_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_K_OUTPUT_VALUE_07_0
#define GPIO_K_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x130f0)
#define GPIO_K_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_K_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_K_OUTPUT_VALUE_07_0_SCR                    GPIO_K_SCR_07_0
#define GPIO_K_OUTPUT_VALUE_07_0_SCRREG                         GPIO_K_SCR_07_0
#define GPIO_K_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_K_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_CLEAR_07_0
#define GPIO_K_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x130f4)
#define GPIO_K_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_K_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_K_INTERRUPT_CLEAR_07_0_SCR                         GPIO_K_SCR_07_0
#define GPIO_K_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_K_SCR_07_0
#define GPIO_K_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_K_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x130f8

// Reserved address 0x130fc

// Register GPIO_K_INTERRUPT_STATUS_G0_0
#define GPIO_K_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x13100)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_K_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G1_0
#define GPIO_K_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x13104)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_K_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G2_0
#define GPIO_K_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x13108)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_K_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G3_0
#define GPIO_K_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1310c)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_K_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G4_0
#define GPIO_K_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x13110)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_K_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G5_0
#define GPIO_K_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x13114)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_K_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G6_0
#define GPIO_K_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x13118)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_K_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_K_INTERRUPT_STATUS_G7_0
#define GPIO_K_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1311c)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_K_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_K_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_K_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_K_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_K_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x13120

// Reserved address 0x13124

// Reserved address 0x13128

// Reserved address 0x1312c

// Reserved address 0x13130

// Reserved address 0x13134

// Reserved address 0x13138

// Reserved address 0x1313c

// Reserved address 0x13140

// Reserved address 0x13144

// Reserved address 0x13148

// Reserved address 0x1314c

// Reserved address 0x13150

// Reserved address 0x13154

// Reserved address 0x13158

// Reserved address 0x1315c

// Reserved address 0x13160

// Reserved address 0x13164

// Reserved address 0x13168

// Reserved address 0x1316c

// Reserved address 0x13170

// Reserved address 0x13174

// Reserved address 0x13178

// Reserved address 0x1317c

// Reserved address 0x13180

// Reserved address 0x13184

// Reserved address 0x13188

// Reserved address 0x1318c

// Reserved address 0x13190

// Reserved address 0x13194

// Reserved address 0x13198

// Reserved address 0x1319c

// Reserved address 0x131a0

// Reserved address 0x131a4

// Reserved address 0x131a8

// Reserved address 0x131ac

// Reserved address 0x131b0

// Reserved address 0x131b4

// Reserved address 0x131b8

// Reserved address 0x131bc

// Reserved address 0x131c0

// Reserved address 0x131c4

// Reserved address 0x131c8

// Reserved address 0x131cc

// Reserved address 0x131d0

// Reserved address 0x131d4

// Reserved address 0x131d8

// Reserved address 0x131dc

// Reserved address 0x131e0

// Reserved address 0x131e4

// Reserved address 0x131e8

// Reserved address 0x131ec

// Reserved address 0x131f0

// Reserved address 0x131f4

// Reserved address 0x131f8

// Reserved address 0x131fc

// Register GPIO_L_ENABLE_CONFIG_00_0
#define GPIO_L_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x13200)
#define GPIO_L_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_L_ENABLE_CONFIG_00_0_SCR                   GPIO_L_SCR_00_0
#define GPIO_L_ENABLE_CONFIG_00_0_SCRREG                        GPIO_L_SCR_00_0
#define GPIO_L_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_00_0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x13204)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_L_SCR_00_0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_L_SCR_00_0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_L_INPUT_00_0
#define GPIO_L_INPUT_00_0                       MK_ADDR_CONST(0x13208)
#define GPIO_L_INPUT_00_0_SECURE                        0x0
#define GPIO_L_INPUT_00_0_DUAL                  0x0
#define GPIO_L_INPUT_00_0_SCR                   GPIO_L_SCR_00_0
#define GPIO_L_INPUT_00_0_SCRREG                        GPIO_L_SCR_00_0
#define GPIO_L_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_L_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_L_OUTPUT_CONTROL_00_0
#define GPIO_L_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1320c)
#define GPIO_L_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_L_OUTPUT_CONTROL_00_0_SCR                  GPIO_L_SCR_00_0
#define GPIO_L_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_L_SCR_00_0
#define GPIO_L_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_00_0
#define GPIO_L_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x13210)
#define GPIO_L_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_L_OUTPUT_VALUE_00_0_SCR                    GPIO_L_SCR_00_0
#define GPIO_L_OUTPUT_VALUE_00_0_SCRREG                         GPIO_L_SCR_00_0
#define GPIO_L_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_CLEAR_00_0
#define GPIO_L_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x13214)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_L_INTERRUPT_CLEAR_00_0_SCR                         GPIO_L_SCR_00_0
#define GPIO_L_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_L_SCR_00_0
#define GPIO_L_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13218

// Reserved address 0x1321c

// Register GPIO_L_ENABLE_CONFIG_01_0
#define GPIO_L_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x13220)
#define GPIO_L_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_L_ENABLE_CONFIG_01_0_SCR                   GPIO_L_SCR_01_0
#define GPIO_L_ENABLE_CONFIG_01_0_SCRREG                        GPIO_L_SCR_01_0
#define GPIO_L_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_01_0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x13224)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_L_SCR_01_0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_L_SCR_01_0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_L_INPUT_01_0
#define GPIO_L_INPUT_01_0                       MK_ADDR_CONST(0x13228)
#define GPIO_L_INPUT_01_0_SECURE                        0x0
#define GPIO_L_INPUT_01_0_DUAL                  0x0
#define GPIO_L_INPUT_01_0_SCR                   GPIO_L_SCR_01_0
#define GPIO_L_INPUT_01_0_SCRREG                        GPIO_L_SCR_01_0
#define GPIO_L_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_L_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_L_OUTPUT_CONTROL_01_0
#define GPIO_L_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1322c)
#define GPIO_L_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_L_OUTPUT_CONTROL_01_0_SCR                  GPIO_L_SCR_01_0
#define GPIO_L_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_L_SCR_01_0
#define GPIO_L_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_01_0
#define GPIO_L_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x13230)
#define GPIO_L_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_L_OUTPUT_VALUE_01_0_SCR                    GPIO_L_SCR_01_0
#define GPIO_L_OUTPUT_VALUE_01_0_SCRREG                         GPIO_L_SCR_01_0
#define GPIO_L_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_CLEAR_01_0
#define GPIO_L_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x13234)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_L_INTERRUPT_CLEAR_01_0_SCR                         GPIO_L_SCR_01_0
#define GPIO_L_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_L_SCR_01_0
#define GPIO_L_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13238

// Reserved address 0x1323c

// Register GPIO_L_ENABLE_CONFIG_02_0
#define GPIO_L_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x13240)
#define GPIO_L_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_L_ENABLE_CONFIG_02_0_SCR                   GPIO_L_SCR_02_0
#define GPIO_L_ENABLE_CONFIG_02_0_SCRREG                        GPIO_L_SCR_02_0
#define GPIO_L_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_02_0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x13244)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_L_SCR_02_0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_L_SCR_02_0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_L_INPUT_02_0
#define GPIO_L_INPUT_02_0                       MK_ADDR_CONST(0x13248)
#define GPIO_L_INPUT_02_0_SECURE                        0x0
#define GPIO_L_INPUT_02_0_DUAL                  0x0
#define GPIO_L_INPUT_02_0_SCR                   GPIO_L_SCR_02_0
#define GPIO_L_INPUT_02_0_SCRREG                        GPIO_L_SCR_02_0
#define GPIO_L_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_L_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_L_OUTPUT_CONTROL_02_0
#define GPIO_L_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1324c)
#define GPIO_L_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_L_OUTPUT_CONTROL_02_0_SCR                  GPIO_L_SCR_02_0
#define GPIO_L_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_L_SCR_02_0
#define GPIO_L_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_02_0
#define GPIO_L_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x13250)
#define GPIO_L_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_L_OUTPUT_VALUE_02_0_SCR                    GPIO_L_SCR_02_0
#define GPIO_L_OUTPUT_VALUE_02_0_SCRREG                         GPIO_L_SCR_02_0
#define GPIO_L_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_CLEAR_02_0
#define GPIO_L_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x13254)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_L_INTERRUPT_CLEAR_02_0_SCR                         GPIO_L_SCR_02_0
#define GPIO_L_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_L_SCR_02_0
#define GPIO_L_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13258

// Reserved address 0x1325c

// Register GPIO_L_ENABLE_CONFIG_03_0
#define GPIO_L_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x13260)
#define GPIO_L_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_L_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_L_ENABLE_CONFIG_03_0_SCR                   GPIO_L_SCR_03_0
#define GPIO_L_ENABLE_CONFIG_03_0_SCRREG                        GPIO_L_SCR_03_0
#define GPIO_L_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_L_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_L_DEBOUNCE_THRESHOLD_03_0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x13264)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_L_SCR_03_0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_L_SCR_03_0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_L_INPUT_03_0
#define GPIO_L_INPUT_03_0                       MK_ADDR_CONST(0x13268)
#define GPIO_L_INPUT_03_0_SECURE                        0x0
#define GPIO_L_INPUT_03_0_DUAL                  0x0
#define GPIO_L_INPUT_03_0_SCR                   GPIO_L_SCR_03_0
#define GPIO_L_INPUT_03_0_SCRREG                        GPIO_L_SCR_03_0
#define GPIO_L_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_L_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_L_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_L_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_L_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_L_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_L_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_L_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_L_OUTPUT_CONTROL_03_0
#define GPIO_L_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1326c)
#define GPIO_L_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_L_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_L_OUTPUT_CONTROL_03_0_SCR                  GPIO_L_SCR_03_0
#define GPIO_L_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_L_SCR_03_0
#define GPIO_L_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_L_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_L_OUTPUT_VALUE_03_0
#define GPIO_L_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x13270)
#define GPIO_L_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_L_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_L_OUTPUT_VALUE_03_0_SCR                    GPIO_L_SCR_03_0
#define GPIO_L_OUTPUT_VALUE_03_0_SCRREG                         GPIO_L_SCR_03_0
#define GPIO_L_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_L_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_CLEAR_03_0
#define GPIO_L_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x13274)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_L_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_L_INTERRUPT_CLEAR_03_0_SCR                         GPIO_L_SCR_03_0
#define GPIO_L_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_L_SCR_03_0
#define GPIO_L_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_L_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x13278

// Reserved address 0x1327c

// Reserved address 0x13280

// Reserved address 0x13284

// Reserved address 0x13288

// Reserved address 0x1328c

// Reserved address 0x13290

// Reserved address 0x13294

// Reserved address 0x13298

// Reserved address 0x1329c

// Reserved address 0x132a0

// Reserved address 0x132a4

// Reserved address 0x132a8

// Reserved address 0x132ac

// Reserved address 0x132b0

// Reserved address 0x132b4

// Reserved address 0x132b8

// Reserved address 0x132bc

// Reserved address 0x132c0

// Reserved address 0x132c4

// Reserved address 0x132c8

// Reserved address 0x132cc

// Reserved address 0x132d0

// Reserved address 0x132d4

// Reserved address 0x132d8

// Reserved address 0x132dc

// Reserved address 0x132e0

// Reserved address 0x132e4

// Reserved address 0x132e8

// Reserved address 0x132ec

// Reserved address 0x132f0

// Reserved address 0x132f4

// Reserved address 0x132f8

// Reserved address 0x132fc

// Register GPIO_L_INTERRUPT_STATUS_G0_0
#define GPIO_L_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x13300)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_L_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G1_0
#define GPIO_L_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x13304)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_L_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G2_0
#define GPIO_L_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x13308)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_L_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G3_0
#define GPIO_L_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1330c)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_L_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G4_0
#define GPIO_L_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x13310)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_L_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G5_0
#define GPIO_L_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x13314)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_L_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G6_0
#define GPIO_L_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x13318)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_L_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_L_INTERRUPT_STATUS_G7_0
#define GPIO_L_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1331c)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_L_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_L_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_L_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_L_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_L_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x13320

// Reserved address 0x13324

// Reserved address 0x13328

// Reserved address 0x1332c

// Reserved address 0x13330

// Reserved address 0x13334

// Reserved address 0x13338

// Reserved address 0x1333c

// Reserved address 0x13340

// Reserved address 0x13344

// Reserved address 0x13348

// Reserved address 0x1334c

// Reserved address 0x13350

// Reserved address 0x13354

// Reserved address 0x13358

// Reserved address 0x1335c

// Reserved address 0x13360

// Reserved address 0x13364

// Reserved address 0x13368

// Reserved address 0x1336c

// Reserved address 0x13370

// Reserved address 0x13374

// Reserved address 0x13378

// Reserved address 0x1337c

// Reserved address 0x13380

// Reserved address 0x13384

// Reserved address 0x13388

// Reserved address 0x1338c

// Reserved address 0x13390

// Reserved address 0x13394

// Reserved address 0x13398

// Reserved address 0x1339c

// Reserved address 0x133a0

// Reserved address 0x133a4

// Reserved address 0x133a8

// Reserved address 0x133ac

// Reserved address 0x133b0

// Reserved address 0x133b4

// Reserved address 0x133b8

// Reserved address 0x133bc

// Reserved address 0x133c0

// Reserved address 0x133c4

// Reserved address 0x133c8

// Reserved address 0x133cc

// Reserved address 0x133d0

// Reserved address 0x133d4

// Reserved address 0x133d8

// Reserved address 0x133dc

// Reserved address 0x133e0

// Reserved address 0x133e4

// Reserved address 0x133e8

// Reserved address 0x133ec

// Reserved address 0x133f0

// Reserved address 0x133f4

// Reserved address 0x133f8

// Reserved address 0x133fc

// Register GPIO_AG_ENABLE_CONFIG_00_0
#define GPIO_AG_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x13400)
#define GPIO_AG_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_SCR                  GPIO_AG_SCR_00_0
#define GPIO_AG_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AG_SCR_00_0
#define GPIO_AG_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_AG_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AG_DEBOUNCE_THRESHOLD_00_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x13404)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AG_SCR_00_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AG_SCR_00_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_INPUT_00_0
#define GPIO_AG_INPUT_00_0                      MK_ADDR_CONST(0x13408)
#define GPIO_AG_INPUT_00_0_SECURE                       0x0
#define GPIO_AG_INPUT_00_0_DUAL                         0x0
#define GPIO_AG_INPUT_00_0_SCR                  GPIO_AG_SCR_00_0
#define GPIO_AG_INPUT_00_0_SCRREG                       GPIO_AG_SCR_00_0
#define GPIO_AG_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_AG_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_AG_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_AG_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AG_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_OUTPUT_CONTROL_00_0
#define GPIO_AG_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1340c)
#define GPIO_AG_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_AG_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_AG_OUTPUT_CONTROL_00_0_SCR                         GPIO_AG_SCR_00_0
#define GPIO_AG_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AG_SCR_00_0
#define GPIO_AG_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_AG_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AG_OUTPUT_VALUE_00_0
#define GPIO_AG_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x13410)
#define GPIO_AG_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_AG_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_AG_OUTPUT_VALUE_00_0_SCR                   GPIO_AG_SCR_00_0
#define GPIO_AG_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AG_SCR_00_0
#define GPIO_AG_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_AG_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_CLEAR_00_0
#define GPIO_AG_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x13414)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_AG_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AG_SCR_00_0
#define GPIO_AG_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AG_SCR_00_0
#define GPIO_AG_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_AG_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13418

// Reserved address 0x1341c

// Register GPIO_AG_ENABLE_CONFIG_01_0
#define GPIO_AG_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x13420)
#define GPIO_AG_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_SCR                  GPIO_AG_SCR_01_0
#define GPIO_AG_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AG_SCR_01_0
#define GPIO_AG_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_AG_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AG_DEBOUNCE_THRESHOLD_01_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x13424)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AG_SCR_01_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AG_SCR_01_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_INPUT_01_0
#define GPIO_AG_INPUT_01_0                      MK_ADDR_CONST(0x13428)
#define GPIO_AG_INPUT_01_0_SECURE                       0x0
#define GPIO_AG_INPUT_01_0_DUAL                         0x0
#define GPIO_AG_INPUT_01_0_SCR                  GPIO_AG_SCR_01_0
#define GPIO_AG_INPUT_01_0_SCRREG                       GPIO_AG_SCR_01_0
#define GPIO_AG_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_AG_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_AG_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_AG_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AG_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_OUTPUT_CONTROL_01_0
#define GPIO_AG_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1342c)
#define GPIO_AG_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_AG_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_AG_OUTPUT_CONTROL_01_0_SCR                         GPIO_AG_SCR_01_0
#define GPIO_AG_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AG_SCR_01_0
#define GPIO_AG_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_AG_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AG_OUTPUT_VALUE_01_0
#define GPIO_AG_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x13430)
#define GPIO_AG_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_AG_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_AG_OUTPUT_VALUE_01_0_SCR                   GPIO_AG_SCR_01_0
#define GPIO_AG_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AG_SCR_01_0
#define GPIO_AG_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_AG_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_CLEAR_01_0
#define GPIO_AG_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x13434)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_AG_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AG_SCR_01_0
#define GPIO_AG_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AG_SCR_01_0
#define GPIO_AG_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_AG_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13438

// Reserved address 0x1343c

// Register GPIO_AG_ENABLE_CONFIG_02_0
#define GPIO_AG_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x13440)
#define GPIO_AG_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_SCR                  GPIO_AG_SCR_02_0
#define GPIO_AG_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AG_SCR_02_0
#define GPIO_AG_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_AG_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AG_DEBOUNCE_THRESHOLD_02_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x13444)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AG_SCR_02_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AG_SCR_02_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_INPUT_02_0
#define GPIO_AG_INPUT_02_0                      MK_ADDR_CONST(0x13448)
#define GPIO_AG_INPUT_02_0_SECURE                       0x0
#define GPIO_AG_INPUT_02_0_DUAL                         0x0
#define GPIO_AG_INPUT_02_0_SCR                  GPIO_AG_SCR_02_0
#define GPIO_AG_INPUT_02_0_SCRREG                       GPIO_AG_SCR_02_0
#define GPIO_AG_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_AG_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_AG_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_AG_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AG_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_OUTPUT_CONTROL_02_0
#define GPIO_AG_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1344c)
#define GPIO_AG_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_AG_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_AG_OUTPUT_CONTROL_02_0_SCR                         GPIO_AG_SCR_02_0
#define GPIO_AG_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AG_SCR_02_0
#define GPIO_AG_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_AG_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AG_OUTPUT_VALUE_02_0
#define GPIO_AG_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x13450)
#define GPIO_AG_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_AG_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_AG_OUTPUT_VALUE_02_0_SCR                   GPIO_AG_SCR_02_0
#define GPIO_AG_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AG_SCR_02_0
#define GPIO_AG_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_AG_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_CLEAR_02_0
#define GPIO_AG_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x13454)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_AG_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AG_SCR_02_0
#define GPIO_AG_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AG_SCR_02_0
#define GPIO_AG_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_AG_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13458

// Reserved address 0x1345c

// Register GPIO_AG_ENABLE_CONFIG_03_0
#define GPIO_AG_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x13460)
#define GPIO_AG_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_DUAL                         0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_SCR                  GPIO_AG_SCR_03_0
#define GPIO_AG_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AG_SCR_03_0
#define GPIO_AG_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_AG_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AG_DEBOUNCE_THRESHOLD_03_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x13464)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AG_SCR_03_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AG_SCR_03_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_INPUT_03_0
#define GPIO_AG_INPUT_03_0                      MK_ADDR_CONST(0x13468)
#define GPIO_AG_INPUT_03_0_SECURE                       0x0
#define GPIO_AG_INPUT_03_0_DUAL                         0x0
#define GPIO_AG_INPUT_03_0_SCR                  GPIO_AG_SCR_03_0
#define GPIO_AG_INPUT_03_0_SCRREG                       GPIO_AG_SCR_03_0
#define GPIO_AG_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_AG_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_AG_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_AG_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AG_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_OUTPUT_CONTROL_03_0
#define GPIO_AG_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1346c)
#define GPIO_AG_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_AG_OUTPUT_CONTROL_03_0_DUAL                        0x0
#define GPIO_AG_OUTPUT_CONTROL_03_0_SCR                         GPIO_AG_SCR_03_0
#define GPIO_AG_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AG_SCR_03_0
#define GPIO_AG_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_AG_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AG_OUTPUT_VALUE_03_0
#define GPIO_AG_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x13470)
#define GPIO_AG_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_AG_OUTPUT_VALUE_03_0_DUAL                  0x0
#define GPIO_AG_OUTPUT_VALUE_03_0_SCR                   GPIO_AG_SCR_03_0
#define GPIO_AG_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AG_SCR_03_0
#define GPIO_AG_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_AG_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_CLEAR_03_0
#define GPIO_AG_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x13474)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_AG_INTERRUPT_CLEAR_03_0_DUAL                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AG_SCR_03_0
#define GPIO_AG_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AG_SCR_03_0
#define GPIO_AG_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_AG_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13478

// Reserved address 0x1347c

// Register GPIO_AG_ENABLE_CONFIG_04_0
#define GPIO_AG_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x13480)
#define GPIO_AG_ENABLE_CONFIG_04_0_SECURE                       0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_DUAL                         0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_SCR                  GPIO_AG_SCR_04_0
#define GPIO_AG_ENABLE_CONFIG_04_0_SCRREG                       GPIO_AG_SCR_04_0
#define GPIO_AG_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
#define GPIO_AG_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AG_DEBOUNCE_THRESHOLD_04_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x13484)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_AG_SCR_04_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_AG_SCR_04_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_INPUT_04_0
#define GPIO_AG_INPUT_04_0                      MK_ADDR_CONST(0x13488)
#define GPIO_AG_INPUT_04_0_SECURE                       0x0
#define GPIO_AG_INPUT_04_0_DUAL                         0x0
#define GPIO_AG_INPUT_04_0_SCR                  GPIO_AG_SCR_04_0
#define GPIO_AG_INPUT_04_0_SCRREG                       GPIO_AG_SCR_04_0
#define GPIO_AG_INPUT_04_0_WORD_COUNT                   0x1
#define GPIO_AG_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_AG_INPUT_04_0_GPIO_IN_RANGE                        0:0
#define GPIO_AG_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AG_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_OUTPUT_CONTROL_04_0
#define GPIO_AG_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x1348c)
#define GPIO_AG_OUTPUT_CONTROL_04_0_SECURE                      0x0
#define GPIO_AG_OUTPUT_CONTROL_04_0_DUAL                        0x0
#define GPIO_AG_OUTPUT_CONTROL_04_0_SCR                         GPIO_AG_SCR_04_0
#define GPIO_AG_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_AG_SCR_04_0
#define GPIO_AG_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
#define GPIO_AG_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AG_OUTPUT_VALUE_04_0
#define GPIO_AG_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x13490)
#define GPIO_AG_OUTPUT_VALUE_04_0_SECURE                        0x0
#define GPIO_AG_OUTPUT_VALUE_04_0_DUAL                  0x0
#define GPIO_AG_OUTPUT_VALUE_04_0_SCR                   GPIO_AG_SCR_04_0
#define GPIO_AG_OUTPUT_VALUE_04_0_SCRREG                        GPIO_AG_SCR_04_0
#define GPIO_AG_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
#define GPIO_AG_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_CLEAR_04_0
#define GPIO_AG_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x13494)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_SECURE                     0x0
#define GPIO_AG_INTERRUPT_CLEAR_04_0_DUAL                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_04_0_SCR                        GPIO_AG_SCR_04_0
#define GPIO_AG_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_AG_SCR_04_0
#define GPIO_AG_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
#define GPIO_AG_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13498

// Reserved address 0x1349c

// Register GPIO_AG_ENABLE_CONFIG_05_0
#define GPIO_AG_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x134a0)
#define GPIO_AG_ENABLE_CONFIG_05_0_SECURE                       0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_DUAL                         0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_SCR                  GPIO_AG_SCR_05_0
#define GPIO_AG_ENABLE_CONFIG_05_0_SCRREG                       GPIO_AG_SCR_05_0
#define GPIO_AG_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
#define GPIO_AG_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AG_DEBOUNCE_THRESHOLD_05_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x134a4)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_AG_SCR_05_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_AG_SCR_05_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_INPUT_05_0
#define GPIO_AG_INPUT_05_0                      MK_ADDR_CONST(0x134a8)
#define GPIO_AG_INPUT_05_0_SECURE                       0x0
#define GPIO_AG_INPUT_05_0_DUAL                         0x0
#define GPIO_AG_INPUT_05_0_SCR                  GPIO_AG_SCR_05_0
#define GPIO_AG_INPUT_05_0_SCRREG                       GPIO_AG_SCR_05_0
#define GPIO_AG_INPUT_05_0_WORD_COUNT                   0x1
#define GPIO_AG_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_AG_INPUT_05_0_GPIO_IN_RANGE                        0:0
#define GPIO_AG_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AG_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_OUTPUT_CONTROL_05_0
#define GPIO_AG_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x134ac)
#define GPIO_AG_OUTPUT_CONTROL_05_0_SECURE                      0x0
#define GPIO_AG_OUTPUT_CONTROL_05_0_DUAL                        0x0
#define GPIO_AG_OUTPUT_CONTROL_05_0_SCR                         GPIO_AG_SCR_05_0
#define GPIO_AG_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_AG_SCR_05_0
#define GPIO_AG_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
#define GPIO_AG_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AG_OUTPUT_VALUE_05_0
#define GPIO_AG_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x134b0)
#define GPIO_AG_OUTPUT_VALUE_05_0_SECURE                        0x0
#define GPIO_AG_OUTPUT_VALUE_05_0_DUAL                  0x0
#define GPIO_AG_OUTPUT_VALUE_05_0_SCR                   GPIO_AG_SCR_05_0
#define GPIO_AG_OUTPUT_VALUE_05_0_SCRREG                        GPIO_AG_SCR_05_0
#define GPIO_AG_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
#define GPIO_AG_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_CLEAR_05_0
#define GPIO_AG_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x134b4)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_SECURE                     0x0
#define GPIO_AG_INTERRUPT_CLEAR_05_0_DUAL                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_05_0_SCR                        GPIO_AG_SCR_05_0
#define GPIO_AG_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_AG_SCR_05_0
#define GPIO_AG_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
#define GPIO_AG_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x134b8

// Reserved address 0x134bc

// Register GPIO_AG_ENABLE_CONFIG_06_0
#define GPIO_AG_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x134c0)
#define GPIO_AG_ENABLE_CONFIG_06_0_SECURE                       0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_DUAL                         0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_SCR                  GPIO_AG_SCR_06_0
#define GPIO_AG_ENABLE_CONFIG_06_0_SCRREG                       GPIO_AG_SCR_06_0
#define GPIO_AG_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
#define GPIO_AG_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AG_DEBOUNCE_THRESHOLD_06_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x134c4)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_AG_SCR_06_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_AG_SCR_06_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_INPUT_06_0
#define GPIO_AG_INPUT_06_0                      MK_ADDR_CONST(0x134c8)
#define GPIO_AG_INPUT_06_0_SECURE                       0x0
#define GPIO_AG_INPUT_06_0_DUAL                         0x0
#define GPIO_AG_INPUT_06_0_SCR                  GPIO_AG_SCR_06_0
#define GPIO_AG_INPUT_06_0_SCRREG                       GPIO_AG_SCR_06_0
#define GPIO_AG_INPUT_06_0_WORD_COUNT                   0x1
#define GPIO_AG_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_AG_INPUT_06_0_GPIO_IN_RANGE                        0:0
#define GPIO_AG_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AG_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_OUTPUT_CONTROL_06_0
#define GPIO_AG_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x134cc)
#define GPIO_AG_OUTPUT_CONTROL_06_0_SECURE                      0x0
#define GPIO_AG_OUTPUT_CONTROL_06_0_DUAL                        0x0
#define GPIO_AG_OUTPUT_CONTROL_06_0_SCR                         GPIO_AG_SCR_06_0
#define GPIO_AG_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_AG_SCR_06_0
#define GPIO_AG_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
#define GPIO_AG_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AG_OUTPUT_VALUE_06_0
#define GPIO_AG_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x134d0)
#define GPIO_AG_OUTPUT_VALUE_06_0_SECURE                        0x0
#define GPIO_AG_OUTPUT_VALUE_06_0_DUAL                  0x0
#define GPIO_AG_OUTPUT_VALUE_06_0_SCR                   GPIO_AG_SCR_06_0
#define GPIO_AG_OUTPUT_VALUE_06_0_SCRREG                        GPIO_AG_SCR_06_0
#define GPIO_AG_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
#define GPIO_AG_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_CLEAR_06_0
#define GPIO_AG_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x134d4)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_SECURE                     0x0
#define GPIO_AG_INTERRUPT_CLEAR_06_0_DUAL                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_06_0_SCR                        GPIO_AG_SCR_06_0
#define GPIO_AG_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_AG_SCR_06_0
#define GPIO_AG_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
#define GPIO_AG_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x134d8

// Reserved address 0x134dc

// Register GPIO_AG_ENABLE_CONFIG_07_0
#define GPIO_AG_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x134e0)
#define GPIO_AG_ENABLE_CONFIG_07_0_SECURE                       0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_DUAL                         0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_SCR                  GPIO_AG_SCR_07_0
#define GPIO_AG_ENABLE_CONFIG_07_0_SCRREG                       GPIO_AG_SCR_07_0
#define GPIO_AG_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
#define GPIO_AG_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AG_DEBOUNCE_THRESHOLD_07_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x134e4)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_AG_SCR_07_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_AG_SCR_07_0
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_INPUT_07_0
#define GPIO_AG_INPUT_07_0                      MK_ADDR_CONST(0x134e8)
#define GPIO_AG_INPUT_07_0_SECURE                       0x0
#define GPIO_AG_INPUT_07_0_DUAL                         0x0
#define GPIO_AG_INPUT_07_0_SCR                  GPIO_AG_SCR_07_0
#define GPIO_AG_INPUT_07_0_SCRREG                       GPIO_AG_SCR_07_0
#define GPIO_AG_INPUT_07_0_WORD_COUNT                   0x1
#define GPIO_AG_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_AG_INPUT_07_0_GPIO_IN_RANGE                        0:0
#define GPIO_AG_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AG_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AG_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AG_OUTPUT_CONTROL_07_0
#define GPIO_AG_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x134ec)
#define GPIO_AG_OUTPUT_CONTROL_07_0_SECURE                      0x0
#define GPIO_AG_OUTPUT_CONTROL_07_0_DUAL                        0x0
#define GPIO_AG_OUTPUT_CONTROL_07_0_SCR                         GPIO_AG_SCR_07_0
#define GPIO_AG_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_AG_SCR_07_0
#define GPIO_AG_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
#define GPIO_AG_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AG_OUTPUT_VALUE_07_0
#define GPIO_AG_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x134f0)
#define GPIO_AG_OUTPUT_VALUE_07_0_SECURE                        0x0
#define GPIO_AG_OUTPUT_VALUE_07_0_DUAL                  0x0
#define GPIO_AG_OUTPUT_VALUE_07_0_SCR                   GPIO_AG_SCR_07_0
#define GPIO_AG_OUTPUT_VALUE_07_0_SCRREG                        GPIO_AG_SCR_07_0
#define GPIO_AG_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
#define GPIO_AG_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_CLEAR_07_0
#define GPIO_AG_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x134f4)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_SECURE                     0x0
#define GPIO_AG_INTERRUPT_CLEAR_07_0_DUAL                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_07_0_SCR                        GPIO_AG_SCR_07_0
#define GPIO_AG_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_AG_SCR_07_0
#define GPIO_AG_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
#define GPIO_AG_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x134f8

// Reserved address 0x134fc

// Register GPIO_AG_INTERRUPT_STATUS_G0_0
#define GPIO_AG_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x13500)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_AG_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_AG_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_AG_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_AG_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_AG_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_STATUS_G1_0
#define GPIO_AG_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x13504)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_AG_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_AG_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_AG_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_AG_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_AG_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_STATUS_G2_0
#define GPIO_AG_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x13508)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_AG_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_AG_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_AG_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_AG_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_AG_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_STATUS_G3_0
#define GPIO_AG_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1350c)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_AG_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_AG_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_AG_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_AG_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_AG_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_STATUS_G4_0
#define GPIO_AG_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x13510)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_AG_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_AG_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_AG_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_AG_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_AG_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_STATUS_G5_0
#define GPIO_AG_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x13514)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_AG_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_AG_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_AG_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_AG_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_AG_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_STATUS_G6_0
#define GPIO_AG_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x13518)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_AG_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_AG_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_AG_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_AG_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_AG_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AG_INTERRUPT_STATUS_G7_0
#define GPIO_AG_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1351c)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_AG_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_AG_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_AG_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_AG_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_AG_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x13520

// Reserved address 0x13524

// Reserved address 0x13528

// Reserved address 0x1352c

// Reserved address 0x13530

// Reserved address 0x13534

// Reserved address 0x13538

// Reserved address 0x1353c

// Reserved address 0x13540

// Reserved address 0x13544

// Reserved address 0x13548

// Reserved address 0x1354c

// Reserved address 0x13550

// Reserved address 0x13554

// Reserved address 0x13558

// Reserved address 0x1355c

// Reserved address 0x13560

// Reserved address 0x13564

// Reserved address 0x13568

// Reserved address 0x1356c

// Reserved address 0x13570

// Reserved address 0x13574

// Reserved address 0x13578

// Reserved address 0x1357c

// Reserved address 0x13580

// Reserved address 0x13584

// Reserved address 0x13588

// Reserved address 0x1358c

// Reserved address 0x13590

// Reserved address 0x13594

// Reserved address 0x13598

// Reserved address 0x1359c

// Reserved address 0x135a0

// Reserved address 0x135a4

// Reserved address 0x135a8

// Reserved address 0x135ac

// Reserved address 0x135b0

// Reserved address 0x135b4

// Reserved address 0x135b8

// Reserved address 0x135bc

// Reserved address 0x135c0

// Reserved address 0x135c4

// Reserved address 0x135c8

// Reserved address 0x135cc

// Reserved address 0x135d0

// Reserved address 0x135d4

// Reserved address 0x135d8

// Reserved address 0x135dc

// Reserved address 0x135e0

// Reserved address 0x135e4

// Reserved address 0x135e8

// Reserved address 0x135ec

// Reserved address 0x135f0

// Reserved address 0x135f4

// Reserved address 0x135f8

// Reserved address 0x135fc

// Register GPIO_AE_ENABLE_CONFIG_00_0
#define GPIO_AE_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x13600)
#define GPIO_AE_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_SCR                  GPIO_AE_SCR_00_0
#define GPIO_AE_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AE_SCR_00_0
#define GPIO_AE_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_AE_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AE_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AE_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AE_DEBOUNCE_THRESHOLD_00_0
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x13604)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AE_SCR_00_0
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AE_SCR_00_0
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AE_INPUT_00_0
#define GPIO_AE_INPUT_00_0                      MK_ADDR_CONST(0x13608)
#define GPIO_AE_INPUT_00_0_SECURE                       0x0
#define GPIO_AE_INPUT_00_0_DUAL                         0x0
#define GPIO_AE_INPUT_00_0_SCR                  GPIO_AE_SCR_00_0
#define GPIO_AE_INPUT_00_0_SCRREG                       GPIO_AE_SCR_00_0
#define GPIO_AE_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_AE_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AE_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AE_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_AE_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_AE_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AE_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AE_OUTPUT_CONTROL_00_0
#define GPIO_AE_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1360c)
#define GPIO_AE_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_AE_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_AE_OUTPUT_CONTROL_00_0_SCR                         GPIO_AE_SCR_00_0
#define GPIO_AE_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AE_SCR_00_0
#define GPIO_AE_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_AE_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AE_OUTPUT_VALUE_00_0
#define GPIO_AE_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x13610)
#define GPIO_AE_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_AE_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_AE_OUTPUT_VALUE_00_0_SCR                   GPIO_AE_SCR_00_0
#define GPIO_AE_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AE_SCR_00_0
#define GPIO_AE_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_AE_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_CLEAR_00_0
#define GPIO_AE_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x13614)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_AE_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_AE_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AE_SCR_00_0
#define GPIO_AE_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AE_SCR_00_0
#define GPIO_AE_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_AE_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13618

// Reserved address 0x1361c

// Register GPIO_AE_ENABLE_CONFIG_01_0
#define GPIO_AE_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x13620)
#define GPIO_AE_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_SCR                  GPIO_AE_SCR_01_0
#define GPIO_AE_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AE_SCR_01_0
#define GPIO_AE_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_AE_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AE_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AE_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AE_DEBOUNCE_THRESHOLD_01_0
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x13624)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AE_SCR_01_0
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AE_SCR_01_0
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AE_INPUT_01_0
#define GPIO_AE_INPUT_01_0                      MK_ADDR_CONST(0x13628)
#define GPIO_AE_INPUT_01_0_SECURE                       0x0
#define GPIO_AE_INPUT_01_0_DUAL                         0x0
#define GPIO_AE_INPUT_01_0_SCR                  GPIO_AE_SCR_01_0
#define GPIO_AE_INPUT_01_0_SCRREG                       GPIO_AE_SCR_01_0
#define GPIO_AE_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_AE_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AE_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AE_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_AE_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_AE_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AE_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AE_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AE_OUTPUT_CONTROL_01_0
#define GPIO_AE_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1362c)
#define GPIO_AE_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_AE_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_AE_OUTPUT_CONTROL_01_0_SCR                         GPIO_AE_SCR_01_0
#define GPIO_AE_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AE_SCR_01_0
#define GPIO_AE_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_AE_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AE_OUTPUT_VALUE_01_0
#define GPIO_AE_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x13630)
#define GPIO_AE_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_AE_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_AE_OUTPUT_VALUE_01_0_SCR                   GPIO_AE_SCR_01_0
#define GPIO_AE_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AE_SCR_01_0
#define GPIO_AE_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_AE_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_CLEAR_01_0
#define GPIO_AE_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x13634)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_AE_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_AE_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AE_SCR_01_0
#define GPIO_AE_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AE_SCR_01_0
#define GPIO_AE_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_AE_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13638

// Reserved address 0x1363c

// Reserved address 0x13640

// Reserved address 0x13644

// Reserved address 0x13648

// Reserved address 0x1364c

// Reserved address 0x13650

// Reserved address 0x13654

// Reserved address 0x13658

// Reserved address 0x1365c

// Reserved address 0x13660

// Reserved address 0x13664

// Reserved address 0x13668

// Reserved address 0x1366c

// Reserved address 0x13670

// Reserved address 0x13674

// Reserved address 0x13678

// Reserved address 0x1367c

// Reserved address 0x13680

// Reserved address 0x13684

// Reserved address 0x13688

// Reserved address 0x1368c

// Reserved address 0x13690

// Reserved address 0x13694

// Reserved address 0x13698

// Reserved address 0x1369c

// Reserved address 0x136a0

// Reserved address 0x136a4

// Reserved address 0x136a8

// Reserved address 0x136ac

// Reserved address 0x136b0

// Reserved address 0x136b4

// Reserved address 0x136b8

// Reserved address 0x136bc

// Reserved address 0x136c0

// Reserved address 0x136c4

// Reserved address 0x136c8

// Reserved address 0x136cc

// Reserved address 0x136d0

// Reserved address 0x136d4

// Reserved address 0x136d8

// Reserved address 0x136dc

// Reserved address 0x136e0

// Reserved address 0x136e4

// Reserved address 0x136e8

// Reserved address 0x136ec

// Reserved address 0x136f0

// Reserved address 0x136f4

// Reserved address 0x136f8

// Reserved address 0x136fc

// Register GPIO_AE_INTERRUPT_STATUS_G0_0
#define GPIO_AE_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x13700)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_AE_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_AE_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_AE_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_AE_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_AE_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_STATUS_G1_0
#define GPIO_AE_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x13704)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_AE_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_AE_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_AE_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_AE_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_AE_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_STATUS_G2_0
#define GPIO_AE_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x13708)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_AE_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_AE_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_AE_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_AE_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_AE_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_STATUS_G3_0
#define GPIO_AE_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1370c)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_AE_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_AE_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_AE_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_AE_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_AE_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_STATUS_G4_0
#define GPIO_AE_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x13710)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_AE_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_AE_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_AE_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_AE_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_AE_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_STATUS_G5_0
#define GPIO_AE_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x13714)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_AE_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_AE_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_AE_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_AE_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_AE_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_STATUS_G6_0
#define GPIO_AE_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x13718)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_AE_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_AE_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_AE_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_AE_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_AE_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AE_INTERRUPT_STATUS_G7_0
#define GPIO_AE_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1371c)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_AE_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_AE_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_AE_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_AE_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_AE_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x13720

// Reserved address 0x13724

// Reserved address 0x13728

// Reserved address 0x1372c

// Reserved address 0x13730

// Reserved address 0x13734

// Reserved address 0x13738

// Reserved address 0x1373c

// Reserved address 0x13740

// Reserved address 0x13744

// Reserved address 0x13748

// Reserved address 0x1374c

// Reserved address 0x13750

// Reserved address 0x13754

// Reserved address 0x13758

// Reserved address 0x1375c

// Reserved address 0x13760

// Reserved address 0x13764

// Reserved address 0x13768

// Reserved address 0x1376c

// Reserved address 0x13770

// Reserved address 0x13774

// Reserved address 0x13778

// Reserved address 0x1377c

// Reserved address 0x13780

// Reserved address 0x13784

// Reserved address 0x13788

// Reserved address 0x1378c

// Reserved address 0x13790

// Reserved address 0x13794

// Reserved address 0x13798

// Reserved address 0x1379c

// Reserved address 0x137a0

// Reserved address 0x137a4

// Reserved address 0x137a8

// Reserved address 0x137ac

// Reserved address 0x137b0

// Reserved address 0x137b4

// Reserved address 0x137b8

// Reserved address 0x137bc

// Reserved address 0x137c0

// Reserved address 0x137c4

// Reserved address 0x137c8

// Reserved address 0x137cc

// Reserved address 0x137d0

// Reserved address 0x137d4

// Reserved address 0x137d8

// Reserved address 0x137dc

// Reserved address 0x137e0

// Reserved address 0x137e4

// Reserved address 0x137e8

// Reserved address 0x137ec

// Reserved address 0x137f0

// Reserved address 0x137f4

// Reserved address 0x137f8

// Reserved address 0x137fc

// Register GPIO_AF_ENABLE_CONFIG_00_0
#define GPIO_AF_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x13800)
#define GPIO_AF_ENABLE_CONFIG_00_0_SECURE                       0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_DUAL                         0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_SCR                  GPIO_AF_SCR_00_0
#define GPIO_AF_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AF_SCR_00_0
#define GPIO_AF_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
#define GPIO_AF_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AF_DEBOUNCE_THRESHOLD_00_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x13804)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AF_SCR_00_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AF_SCR_00_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AF_INPUT_00_0
#define GPIO_AF_INPUT_00_0                      MK_ADDR_CONST(0x13808)
#define GPIO_AF_INPUT_00_0_SECURE                       0x0
#define GPIO_AF_INPUT_00_0_DUAL                         0x0
#define GPIO_AF_INPUT_00_0_SCR                  GPIO_AF_SCR_00_0
#define GPIO_AF_INPUT_00_0_SCRREG                       GPIO_AF_SCR_00_0
#define GPIO_AF_INPUT_00_0_WORD_COUNT                   0x1
#define GPIO_AF_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AF_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_AF_INPUT_00_0_GPIO_IN_RANGE                        0:0
#define GPIO_AF_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AF_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AF_OUTPUT_CONTROL_00_0
#define GPIO_AF_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1380c)
#define GPIO_AF_OUTPUT_CONTROL_00_0_SECURE                      0x0
#define GPIO_AF_OUTPUT_CONTROL_00_0_DUAL                        0x0
#define GPIO_AF_OUTPUT_CONTROL_00_0_SCR                         GPIO_AF_SCR_00_0
#define GPIO_AF_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AF_SCR_00_0
#define GPIO_AF_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
#define GPIO_AF_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AF_OUTPUT_VALUE_00_0
#define GPIO_AF_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x13810)
#define GPIO_AF_OUTPUT_VALUE_00_0_SECURE                        0x0
#define GPIO_AF_OUTPUT_VALUE_00_0_DUAL                  0x0
#define GPIO_AF_OUTPUT_VALUE_00_0_SCR                   GPIO_AF_SCR_00_0
#define GPIO_AF_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AF_SCR_00_0
#define GPIO_AF_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
#define GPIO_AF_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_CLEAR_00_0
#define GPIO_AF_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x13814)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_SECURE                     0x0
#define GPIO_AF_INTERRUPT_CLEAR_00_0_DUAL                       0x0
#define GPIO_AF_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AF_SCR_00_0
#define GPIO_AF_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AF_SCR_00_0
#define GPIO_AF_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
#define GPIO_AF_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13818

// Reserved address 0x1381c

// Register GPIO_AF_ENABLE_CONFIG_01_0
#define GPIO_AF_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x13820)
#define GPIO_AF_ENABLE_CONFIG_01_0_SECURE                       0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_DUAL                         0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_SCR                  GPIO_AF_SCR_01_0
#define GPIO_AF_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AF_SCR_01_0
#define GPIO_AF_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
#define GPIO_AF_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AF_DEBOUNCE_THRESHOLD_01_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x13824)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AF_SCR_01_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AF_SCR_01_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AF_INPUT_01_0
#define GPIO_AF_INPUT_01_0                      MK_ADDR_CONST(0x13828)
#define GPIO_AF_INPUT_01_0_SECURE                       0x0
#define GPIO_AF_INPUT_01_0_DUAL                         0x0
#define GPIO_AF_INPUT_01_0_SCR                  GPIO_AF_SCR_01_0
#define GPIO_AF_INPUT_01_0_SCRREG                       GPIO_AF_SCR_01_0
#define GPIO_AF_INPUT_01_0_WORD_COUNT                   0x1
#define GPIO_AF_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AF_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_AF_INPUT_01_0_GPIO_IN_RANGE                        0:0
#define GPIO_AF_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AF_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AF_OUTPUT_CONTROL_01_0
#define GPIO_AF_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1382c)
#define GPIO_AF_OUTPUT_CONTROL_01_0_SECURE                      0x0
#define GPIO_AF_OUTPUT_CONTROL_01_0_DUAL                        0x0
#define GPIO_AF_OUTPUT_CONTROL_01_0_SCR                         GPIO_AF_SCR_01_0
#define GPIO_AF_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AF_SCR_01_0
#define GPIO_AF_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
#define GPIO_AF_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AF_OUTPUT_VALUE_01_0
#define GPIO_AF_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x13830)
#define GPIO_AF_OUTPUT_VALUE_01_0_SECURE                        0x0
#define GPIO_AF_OUTPUT_VALUE_01_0_DUAL                  0x0
#define GPIO_AF_OUTPUT_VALUE_01_0_SCR                   GPIO_AF_SCR_01_0
#define GPIO_AF_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AF_SCR_01_0
#define GPIO_AF_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
#define GPIO_AF_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_CLEAR_01_0
#define GPIO_AF_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x13834)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_SECURE                     0x0
#define GPIO_AF_INTERRUPT_CLEAR_01_0_DUAL                       0x0
#define GPIO_AF_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AF_SCR_01_0
#define GPIO_AF_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AF_SCR_01_0
#define GPIO_AF_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
#define GPIO_AF_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13838

// Reserved address 0x1383c

// Register GPIO_AF_ENABLE_CONFIG_02_0
#define GPIO_AF_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x13840)
#define GPIO_AF_ENABLE_CONFIG_02_0_SECURE                       0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_DUAL                         0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_SCR                  GPIO_AF_SCR_02_0
#define GPIO_AF_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AF_SCR_02_0
#define GPIO_AF_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
#define GPIO_AF_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AF_DEBOUNCE_THRESHOLD_02_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x13844)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AF_SCR_02_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AF_SCR_02_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AF_INPUT_02_0
#define GPIO_AF_INPUT_02_0                      MK_ADDR_CONST(0x13848)
#define GPIO_AF_INPUT_02_0_SECURE                       0x0
#define GPIO_AF_INPUT_02_0_DUAL                         0x0
#define GPIO_AF_INPUT_02_0_SCR                  GPIO_AF_SCR_02_0
#define GPIO_AF_INPUT_02_0_SCRREG                       GPIO_AF_SCR_02_0
#define GPIO_AF_INPUT_02_0_WORD_COUNT                   0x1
#define GPIO_AF_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AF_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_AF_INPUT_02_0_GPIO_IN_RANGE                        0:0
#define GPIO_AF_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AF_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AF_OUTPUT_CONTROL_02_0
#define GPIO_AF_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1384c)
#define GPIO_AF_OUTPUT_CONTROL_02_0_SECURE                      0x0
#define GPIO_AF_OUTPUT_CONTROL_02_0_DUAL                        0x0
#define GPIO_AF_OUTPUT_CONTROL_02_0_SCR                         GPIO_AF_SCR_02_0
#define GPIO_AF_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AF_SCR_02_0
#define GPIO_AF_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
#define GPIO_AF_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AF_OUTPUT_VALUE_02_0
#define GPIO_AF_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x13850)
#define GPIO_AF_OUTPUT_VALUE_02_0_SECURE                        0x0
#define GPIO_AF_OUTPUT_VALUE_02_0_DUAL                  0x0
#define GPIO_AF_OUTPUT_VALUE_02_0_SCR                   GPIO_AF_SCR_02_0
#define GPIO_AF_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AF_SCR_02_0
#define GPIO_AF_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
#define GPIO_AF_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_CLEAR_02_0
#define GPIO_AF_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x13854)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_SECURE                     0x0
#define GPIO_AF_INTERRUPT_CLEAR_02_0_DUAL                       0x0
#define GPIO_AF_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AF_SCR_02_0
#define GPIO_AF_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AF_SCR_02_0
#define GPIO_AF_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
#define GPIO_AF_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13858

// Reserved address 0x1385c

// Register GPIO_AF_ENABLE_CONFIG_03_0
#define GPIO_AF_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x13860)
#define GPIO_AF_ENABLE_CONFIG_03_0_SECURE                       0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_DUAL                         0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_SCR                  GPIO_AF_SCR_03_0
#define GPIO_AF_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AF_SCR_03_0
#define GPIO_AF_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
#define GPIO_AF_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)

#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)


// Register GPIO_AF_DEBOUNCE_THRESHOLD_03_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x13864)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AF_SCR_03_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AF_SCR_03_0
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AF_INPUT_03_0
#define GPIO_AF_INPUT_03_0                      MK_ADDR_CONST(0x13868)
#define GPIO_AF_INPUT_03_0_SECURE                       0x0
#define GPIO_AF_INPUT_03_0_DUAL                         0x0
#define GPIO_AF_INPUT_03_0_SCR                  GPIO_AF_SCR_03_0
#define GPIO_AF_INPUT_03_0_SCRREG                       GPIO_AF_SCR_03_0
#define GPIO_AF_INPUT_03_0_WORD_COUNT                   0x1
#define GPIO_AF_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AF_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_AF_INPUT_03_0_GPIO_IN_RANGE                        0:0
#define GPIO_AF_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
#define GPIO_AF_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_AF_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_AF_OUTPUT_CONTROL_03_0
#define GPIO_AF_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1386c)
#define GPIO_AF_OUTPUT_CONTROL_03_0_SECURE                      0x0
#define GPIO_AF_OUTPUT_CONTROL_03_0_DUAL                        0x0
#define GPIO_AF_OUTPUT_CONTROL_03_0_SCR                         GPIO_AF_SCR_03_0
#define GPIO_AF_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AF_SCR_03_0
#define GPIO_AF_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
#define GPIO_AF_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)


// Register GPIO_AF_OUTPUT_VALUE_03_0
#define GPIO_AF_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x13870)
#define GPIO_AF_OUTPUT_VALUE_03_0_SECURE                        0x0
#define GPIO_AF_OUTPUT_VALUE_03_0_DUAL                  0x0
#define GPIO_AF_OUTPUT_VALUE_03_0_SCR                   GPIO_AF_SCR_03_0
#define GPIO_AF_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AF_SCR_03_0
#define GPIO_AF_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
#define GPIO_AF_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_CLEAR_03_0
#define GPIO_AF_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x13874)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_SECURE                     0x0
#define GPIO_AF_INTERRUPT_CLEAR_03_0_DUAL                       0x0
#define GPIO_AF_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AF_SCR_03_0
#define GPIO_AF_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AF_SCR_03_0
#define GPIO_AF_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
#define GPIO_AF_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)


// Reserved address 0x13878

// Reserved address 0x1387c

// Reserved address 0x13880

// Reserved address 0x13884

// Reserved address 0x13888

// Reserved address 0x1388c

// Reserved address 0x13890

// Reserved address 0x13894

// Reserved address 0x13898

// Reserved address 0x1389c

// Reserved address 0x138a0

// Reserved address 0x138a4

// Reserved address 0x138a8

// Reserved address 0x138ac

// Reserved address 0x138b0

// Reserved address 0x138b4

// Reserved address 0x138b8

// Reserved address 0x138bc

// Reserved address 0x138c0

// Reserved address 0x138c4

// Reserved address 0x138c8

// Reserved address 0x138cc

// Reserved address 0x138d0

// Reserved address 0x138d4

// Reserved address 0x138d8

// Reserved address 0x138dc

// Reserved address 0x138e0

// Reserved address 0x138e4

// Reserved address 0x138e8

// Reserved address 0x138ec

// Reserved address 0x138f0

// Reserved address 0x138f4

// Reserved address 0x138f8

// Reserved address 0x138fc

// Register GPIO_AF_INTERRUPT_STATUS_G0_0
#define GPIO_AF_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x13900)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_SECURE                    0x0
#define GPIO_AF_INTERRUPT_STATUS_G0_0_DUAL                      0x0
#define GPIO_AF_INTERRUPT_STATUS_G0_0_SCR                       0
#define GPIO_AF_INTERRUPT_STATUS_G0_0_SCRREG                    0
#define GPIO_AF_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
#define GPIO_AF_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_STATUS_G1_0
#define GPIO_AF_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x13904)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_SECURE                    0x0
#define GPIO_AF_INTERRUPT_STATUS_G1_0_DUAL                      0x0
#define GPIO_AF_INTERRUPT_STATUS_G1_0_SCR                       0
#define GPIO_AF_INTERRUPT_STATUS_G1_0_SCRREG                    0
#define GPIO_AF_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
#define GPIO_AF_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_STATUS_G2_0
#define GPIO_AF_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x13908)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_SECURE                    0x0
#define GPIO_AF_INTERRUPT_STATUS_G2_0_DUAL                      0x0
#define GPIO_AF_INTERRUPT_STATUS_G2_0_SCR                       0
#define GPIO_AF_INTERRUPT_STATUS_G2_0_SCRREG                    0
#define GPIO_AF_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
#define GPIO_AF_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_STATUS_G3_0
#define GPIO_AF_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1390c)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_SECURE                    0x0
#define GPIO_AF_INTERRUPT_STATUS_G3_0_DUAL                      0x0
#define GPIO_AF_INTERRUPT_STATUS_G3_0_SCR                       0
#define GPIO_AF_INTERRUPT_STATUS_G3_0_SCRREG                    0
#define GPIO_AF_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
#define GPIO_AF_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_STATUS_G4_0
#define GPIO_AF_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x13910)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_SECURE                    0x0
#define GPIO_AF_INTERRUPT_STATUS_G4_0_DUAL                      0x0
#define GPIO_AF_INTERRUPT_STATUS_G4_0_SCR                       0
#define GPIO_AF_INTERRUPT_STATUS_G4_0_SCRREG                    0
#define GPIO_AF_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
#define GPIO_AF_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_STATUS_G5_0
#define GPIO_AF_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x13914)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_SECURE                    0x0
#define GPIO_AF_INTERRUPT_STATUS_G5_0_DUAL                      0x0
#define GPIO_AF_INTERRUPT_STATUS_G5_0_SCR                       0
#define GPIO_AF_INTERRUPT_STATUS_G5_0_SCRREG                    0
#define GPIO_AF_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
#define GPIO_AF_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_STATUS_G6_0
#define GPIO_AF_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x13918)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_SECURE                    0x0
#define GPIO_AF_INTERRUPT_STATUS_G6_0_DUAL                      0x0
#define GPIO_AF_INTERRUPT_STATUS_G6_0_SCR                       0
#define GPIO_AF_INTERRUPT_STATUS_G6_0_SCRREG                    0
#define GPIO_AF_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
#define GPIO_AF_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Register GPIO_AF_INTERRUPT_STATUS_G7_0
#define GPIO_AF_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1391c)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_SECURE                    0x0
#define GPIO_AF_INTERRUPT_STATUS_G7_0_DUAL                      0x0
#define GPIO_AF_INTERRUPT_STATUS_G7_0_SCR                       0
#define GPIO_AF_INTERRUPT_STATUS_G7_0_SCRREG                    0
#define GPIO_AF_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
#define GPIO_AF_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)


// Reserved address 0x13920

// Reserved address 0x13924

// Reserved address 0x13928

// Reserved address 0x1392c

// Reserved address 0x13930

// Reserved address 0x13934

// Reserved address 0x13938

// Reserved address 0x1393c

// Reserved address 0x13940

// Reserved address 0x13944

// Reserved address 0x13948

// Reserved address 0x1394c

// Reserved address 0x13950

// Reserved address 0x13954

// Reserved address 0x13958

// Reserved address 0x1395c

// Reserved address 0x13960

// Reserved address 0x13964

// Reserved address 0x13968

// Reserved address 0x1396c

// Reserved address 0x13970

// Reserved address 0x13974

// Reserved address 0x13978

// Reserved address 0x1397c

// Reserved address 0x13980

// Reserved address 0x13984

// Reserved address 0x13988

// Reserved address 0x1398c

// Reserved address 0x13990

// Reserved address 0x13994

// Reserved address 0x13998

// Reserved address 0x1399c

// Reserved address 0x139a0

// Reserved address 0x139a4

// Reserved address 0x139a8

// Reserved address 0x139ac

// Reserved address 0x139b0

// Reserved address 0x139b4

// Reserved address 0x139b8

// Reserved address 0x139bc

// Reserved address 0x139c0

// Reserved address 0x139c4

// Reserved address 0x139c8

// Reserved address 0x139cc

// Reserved address 0x139d0

// Reserved address 0x139d4

// Reserved address 0x139d8

// Reserved address 0x139dc

// Reserved address 0x139e0

// Reserved address 0x139e4

// Reserved address 0x139e8

// Reserved address 0x139ec

// Reserved address 0x139f0

// Reserved address 0x139f4

// Reserved address 0x139f8

// Reserved address 0x139fc

// Register GPIO_G_ENABLE_CONFIG_00_0
#define GPIO_G_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x14000)
#define GPIO_G_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_00_0_SCR                   GPIO_G_SCR_00_0
#define GPIO_G_ENABLE_CONFIG_00_0_SCRREG                        GPIO_G_SCR_00_0
#define GPIO_G_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_00_0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x14004)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_G_SCR_00_0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_G_SCR_00_0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_00_0
#define GPIO_G_INPUT_00_0                       MK_ADDR_CONST(0x14008)
#define GPIO_G_INPUT_00_0_SECURE                        0x0
#define GPIO_G_INPUT_00_0_DUAL                  0x0
#define GPIO_G_INPUT_00_0_SCR                   GPIO_G_SCR_00_0
#define GPIO_G_INPUT_00_0_SCRREG                        GPIO_G_SCR_00_0
#define GPIO_G_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_00_0
#define GPIO_G_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1400c)
#define GPIO_G_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_00_0_SCR                  GPIO_G_SCR_00_0
#define GPIO_G_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_G_SCR_00_0
#define GPIO_G_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_00_0
#define GPIO_G_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x14010)
#define GPIO_G_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_00_0_SCR                    GPIO_G_SCR_00_0
#define GPIO_G_OUTPUT_VALUE_00_0_SCRREG                         GPIO_G_SCR_00_0
#define GPIO_G_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_00_0
#define GPIO_G_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x14014)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_00_0_SCR                         GPIO_G_SCR_00_0
#define GPIO_G_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_G_SCR_00_0
#define GPIO_G_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14018

// Reserved address 0x1401c

// Register GPIO_G_ENABLE_CONFIG_01_0
#define GPIO_G_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x14020)
#define GPIO_G_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_01_0_SCR                   GPIO_G_SCR_01_0
#define GPIO_G_ENABLE_CONFIG_01_0_SCRREG                        GPIO_G_SCR_01_0
#define GPIO_G_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_01_0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x14024)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_G_SCR_01_0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_G_SCR_01_0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_01_0
#define GPIO_G_INPUT_01_0                       MK_ADDR_CONST(0x14028)
#define GPIO_G_INPUT_01_0_SECURE                        0x0
#define GPIO_G_INPUT_01_0_DUAL                  0x0
#define GPIO_G_INPUT_01_0_SCR                   GPIO_G_SCR_01_0
#define GPIO_G_INPUT_01_0_SCRREG                        GPIO_G_SCR_01_0
#define GPIO_G_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_01_0
#define GPIO_G_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1402c)
#define GPIO_G_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_01_0_SCR                  GPIO_G_SCR_01_0
#define GPIO_G_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_G_SCR_01_0
#define GPIO_G_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_01_0
#define GPIO_G_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x14030)
#define GPIO_G_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_01_0_SCR                    GPIO_G_SCR_01_0
#define GPIO_G_OUTPUT_VALUE_01_0_SCRREG                         GPIO_G_SCR_01_0
#define GPIO_G_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_01_0
#define GPIO_G_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x14034)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_01_0_SCR                         GPIO_G_SCR_01_0
#define GPIO_G_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_G_SCR_01_0
#define GPIO_G_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14038

// Reserved address 0x1403c

// Register GPIO_G_ENABLE_CONFIG_02_0
#define GPIO_G_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x14040)
#define GPIO_G_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_02_0_SCR                   GPIO_G_SCR_02_0
#define GPIO_G_ENABLE_CONFIG_02_0_SCRREG                        GPIO_G_SCR_02_0
#define GPIO_G_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_02_0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x14044)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_G_SCR_02_0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_G_SCR_02_0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_02_0
#define GPIO_G_INPUT_02_0                       MK_ADDR_CONST(0x14048)
#define GPIO_G_INPUT_02_0_SECURE                        0x0
#define GPIO_G_INPUT_02_0_DUAL                  0x0
#define GPIO_G_INPUT_02_0_SCR                   GPIO_G_SCR_02_0
#define GPIO_G_INPUT_02_0_SCRREG                        GPIO_G_SCR_02_0
#define GPIO_G_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_02_0
#define GPIO_G_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1404c)
#define GPIO_G_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_02_0_SCR                  GPIO_G_SCR_02_0
#define GPIO_G_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_G_SCR_02_0
#define GPIO_G_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_02_0
#define GPIO_G_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x14050)
#define GPIO_G_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_02_0_SCR                    GPIO_G_SCR_02_0
#define GPIO_G_OUTPUT_VALUE_02_0_SCRREG                         GPIO_G_SCR_02_0
#define GPIO_G_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_02_0
#define GPIO_G_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x14054)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_02_0_SCR                         GPIO_G_SCR_02_0
#define GPIO_G_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_G_SCR_02_0
#define GPIO_G_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14058

// Reserved address 0x1405c

// Register GPIO_G_ENABLE_CONFIG_03_0
#define GPIO_G_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x14060)
#define GPIO_G_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_03_0_SCR                   GPIO_G_SCR_03_0
#define GPIO_G_ENABLE_CONFIG_03_0_SCRREG                        GPIO_G_SCR_03_0
#define GPIO_G_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_03_0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x14064)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_G_SCR_03_0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_G_SCR_03_0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_03_0
#define GPIO_G_INPUT_03_0                       MK_ADDR_CONST(0x14068)
#define GPIO_G_INPUT_03_0_SECURE                        0x0
#define GPIO_G_INPUT_03_0_DUAL                  0x0
#define GPIO_G_INPUT_03_0_SCR                   GPIO_G_SCR_03_0
#define GPIO_G_INPUT_03_0_SCRREG                        GPIO_G_SCR_03_0
#define GPIO_G_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_03_0
#define GPIO_G_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1406c)
#define GPIO_G_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_03_0_SCR                  GPIO_G_SCR_03_0
#define GPIO_G_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_G_SCR_03_0
#define GPIO_G_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_03_0
#define GPIO_G_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x14070)
#define GPIO_G_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_03_0_SCR                    GPIO_G_SCR_03_0
#define GPIO_G_OUTPUT_VALUE_03_0_SCRREG                         GPIO_G_SCR_03_0
#define GPIO_G_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_03_0
#define GPIO_G_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x14074)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_03_0_SCR                         GPIO_G_SCR_03_0
#define GPIO_G_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_G_SCR_03_0
#define GPIO_G_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14078

// Reserved address 0x1407c

// Register GPIO_G_ENABLE_CONFIG_04_0
#define GPIO_G_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x14080)
#define GPIO_G_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_04_0_SCR                   GPIO_G_SCR_04_0
#define GPIO_G_ENABLE_CONFIG_04_0_SCRREG                        GPIO_G_SCR_04_0
#define GPIO_G_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_04_0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x14084)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_G_SCR_04_0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_G_SCR_04_0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_04_0
#define GPIO_G_INPUT_04_0                       MK_ADDR_CONST(0x14088)
#define GPIO_G_INPUT_04_0_SECURE                        0x0
#define GPIO_G_INPUT_04_0_DUAL                  0x0
#define GPIO_G_INPUT_04_0_SCR                   GPIO_G_SCR_04_0
#define GPIO_G_INPUT_04_0_SCRREG                        GPIO_G_SCR_04_0
#define GPIO_G_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_04_0
#define GPIO_G_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1408c)
#define GPIO_G_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_04_0_SCR                  GPIO_G_SCR_04_0
#define GPIO_G_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_G_SCR_04_0
#define GPIO_G_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_04_0
#define GPIO_G_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x14090)
#define GPIO_G_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_04_0_SCR                    GPIO_G_SCR_04_0
#define GPIO_G_OUTPUT_VALUE_04_0_SCRREG                         GPIO_G_SCR_04_0
#define GPIO_G_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_04_0
#define GPIO_G_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x14094)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_04_0_SCR                         GPIO_G_SCR_04_0
#define GPIO_G_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_G_SCR_04_0
#define GPIO_G_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14098

// Reserved address 0x1409c

// Register GPIO_G_ENABLE_CONFIG_05_0
#define GPIO_G_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x140a0)
#define GPIO_G_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_05_0_SCR                   GPIO_G_SCR_05_0
#define GPIO_G_ENABLE_CONFIG_05_0_SCRREG                        GPIO_G_SCR_05_0
#define GPIO_G_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_05_0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x140a4)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_G_SCR_05_0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_G_SCR_05_0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_05_0
#define GPIO_G_INPUT_05_0                       MK_ADDR_CONST(0x140a8)
#define GPIO_G_INPUT_05_0_SECURE                        0x0
#define GPIO_G_INPUT_05_0_DUAL                  0x0
#define GPIO_G_INPUT_05_0_SCR                   GPIO_G_SCR_05_0
#define GPIO_G_INPUT_05_0_SCRREG                        GPIO_G_SCR_05_0
#define GPIO_G_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_05_0
#define GPIO_G_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x140ac)
#define GPIO_G_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_05_0_SCR                  GPIO_G_SCR_05_0
#define GPIO_G_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_G_SCR_05_0
#define GPIO_G_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_05_0
#define GPIO_G_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x140b0)
#define GPIO_G_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_05_0_SCR                    GPIO_G_SCR_05_0
#define GPIO_G_OUTPUT_VALUE_05_0_SCRREG                         GPIO_G_SCR_05_0
#define GPIO_G_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_05_0
#define GPIO_G_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x140b4)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_05_0_SCR                         GPIO_G_SCR_05_0
#define GPIO_G_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_G_SCR_05_0
#define GPIO_G_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x140b8

// Reserved address 0x140bc

// Register GPIO_G_ENABLE_CONFIG_06_0
#define GPIO_G_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x140c0)
#define GPIO_G_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_06_0_SCR                   GPIO_G_SCR_06_0
#define GPIO_G_ENABLE_CONFIG_06_0_SCRREG                        GPIO_G_SCR_06_0
#define GPIO_G_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_06_0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x140c4)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_G_SCR_06_0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_G_SCR_06_0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_06_0
#define GPIO_G_INPUT_06_0                       MK_ADDR_CONST(0x140c8)
#define GPIO_G_INPUT_06_0_SECURE                        0x0
#define GPIO_G_INPUT_06_0_DUAL                  0x0
#define GPIO_G_INPUT_06_0_SCR                   GPIO_G_SCR_06_0
#define GPIO_G_INPUT_06_0_SCRREG                        GPIO_G_SCR_06_0
#define GPIO_G_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_06_0
#define GPIO_G_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x140cc)
#define GPIO_G_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_06_0_SCR                  GPIO_G_SCR_06_0
#define GPIO_G_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_G_SCR_06_0
#define GPIO_G_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_06_0
#define GPIO_G_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x140d0)
#define GPIO_G_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_06_0_SCR                    GPIO_G_SCR_06_0
#define GPIO_G_OUTPUT_VALUE_06_0_SCRREG                         GPIO_G_SCR_06_0
#define GPIO_G_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_06_0
#define GPIO_G_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x140d4)
#define GPIO_G_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_06_0_SCR                         GPIO_G_SCR_06_0
#define GPIO_G_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_G_SCR_06_0
#define GPIO_G_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x140d8

// Reserved address 0x140dc

// Register GPIO_G_ENABLE_CONFIG_07_0
#define GPIO_G_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x140e0)
#define GPIO_G_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_G_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_G_ENABLE_CONFIG_07_0_SCR                   GPIO_G_SCR_07_0
#define GPIO_G_ENABLE_CONFIG_07_0_SCRREG                        GPIO_G_SCR_07_0
#define GPIO_G_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_G_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_G_DEBOUNCE_THRESHOLD_07_0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x140e4)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_G_SCR_07_0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_G_SCR_07_0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_INPUT_07_0
#define GPIO_G_INPUT_07_0                       MK_ADDR_CONST(0x140e8)
#define GPIO_G_INPUT_07_0_SECURE                        0x0
#define GPIO_G_INPUT_07_0_DUAL                  0x0
#define GPIO_G_INPUT_07_0_SCR                   GPIO_G_SCR_07_0
#define GPIO_G_INPUT_07_0_SCRREG                        GPIO_G_SCR_07_0
#define GPIO_G_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_G_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_G_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_G_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_G_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_G_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_G_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_G_OUTPUT_CONTROL_07_0
#define GPIO_G_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x140ec)
#define GPIO_G_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_G_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_G_OUTPUT_CONTROL_07_0_SCR                  GPIO_G_SCR_07_0
#define GPIO_G_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_G_SCR_07_0
#define GPIO_G_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_G_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_G_OUTPUT_VALUE_07_0
#define GPIO_G_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x140f0)
#define GPIO_G_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_G_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_G_OUTPUT_VALUE_07_0_SCR                    GPIO_G_SCR_07_0
#define GPIO_G_OUTPUT_VALUE_07_0_SCRREG                         GPIO_G_SCR_07_0
#define GPIO_G_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_G_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_CLEAR_07_0
#define GPIO_G_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x140f4)
#define GPIO_G_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_G_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_G_INTERRUPT_CLEAR_07_0_SCR                         GPIO_G_SCR_07_0
#define GPIO_G_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_G_SCR_07_0
#define GPIO_G_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_G_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x140f8

// Reserved address 0x140fc

// Register GPIO_G_INTERRUPT_STATUS_G0_0
#define GPIO_G_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x14100)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_G_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G1_0
#define GPIO_G_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x14104)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_G_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G2_0
#define GPIO_G_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x14108)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_G_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G3_0
#define GPIO_G_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1410c)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_G_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G4_0
#define GPIO_G_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x14110)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_G_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G5_0
#define GPIO_G_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x14114)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_G_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G6_0
#define GPIO_G_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x14118)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_G_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_G_INTERRUPT_STATUS_G7_0
#define GPIO_G_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1411c)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_G_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_G_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_G_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_G_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_G_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x14120

// Reserved address 0x14124

// Reserved address 0x14128

// Reserved address 0x1412c

// Reserved address 0x14130

// Reserved address 0x14134

// Reserved address 0x14138

// Reserved address 0x1413c

// Reserved address 0x14140

// Reserved address 0x14144

// Reserved address 0x14148

// Reserved address 0x1414c

// Reserved address 0x14150

// Reserved address 0x14154

// Reserved address 0x14158

// Reserved address 0x1415c

// Reserved address 0x14160

// Reserved address 0x14164

// Reserved address 0x14168

// Reserved address 0x1416c

// Reserved address 0x14170

// Reserved address 0x14174

// Reserved address 0x14178

// Reserved address 0x1417c

// Reserved address 0x14180

// Reserved address 0x14184

// Reserved address 0x14188

// Reserved address 0x1418c

// Reserved address 0x14190

// Reserved address 0x14194

// Reserved address 0x14198

// Reserved address 0x1419c

// Reserved address 0x141a0

// Reserved address 0x141a4

// Reserved address 0x141a8

// Reserved address 0x141ac

// Reserved address 0x141b0

// Reserved address 0x141b4

// Reserved address 0x141b8

// Reserved address 0x141bc

// Reserved address 0x141c0

// Reserved address 0x141c4

// Reserved address 0x141c8

// Reserved address 0x141cc

// Reserved address 0x141d0

// Reserved address 0x141d4

// Reserved address 0x141d8

// Reserved address 0x141dc

// Reserved address 0x141e0

// Reserved address 0x141e4

// Reserved address 0x141e8

// Reserved address 0x141ec

// Reserved address 0x141f0

// Reserved address 0x141f4

// Reserved address 0x141f8

// Reserved address 0x141fc

// Register GPIO_H_ENABLE_CONFIG_00_0
#define GPIO_H_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x14200)
#define GPIO_H_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_00_0_SCR                   GPIO_H_SCR_00_0
#define GPIO_H_ENABLE_CONFIG_00_0_SCRREG                        GPIO_H_SCR_00_0
#define GPIO_H_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_00_0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x14204)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_H_SCR_00_0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_H_SCR_00_0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_00_0
#define GPIO_H_INPUT_00_0                       MK_ADDR_CONST(0x14208)
#define GPIO_H_INPUT_00_0_SECURE                        0x0
#define GPIO_H_INPUT_00_0_DUAL                  0x0
#define GPIO_H_INPUT_00_0_SCR                   GPIO_H_SCR_00_0
#define GPIO_H_INPUT_00_0_SCRREG                        GPIO_H_SCR_00_0
#define GPIO_H_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_00_0
#define GPIO_H_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1420c)
#define GPIO_H_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_00_0_SCR                  GPIO_H_SCR_00_0
#define GPIO_H_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_H_SCR_00_0
#define GPIO_H_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_00_0
#define GPIO_H_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x14210)
#define GPIO_H_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_00_0_SCR                    GPIO_H_SCR_00_0
#define GPIO_H_OUTPUT_VALUE_00_0_SCRREG                         GPIO_H_SCR_00_0
#define GPIO_H_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_00_0
#define GPIO_H_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x14214)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_00_0_SCR                         GPIO_H_SCR_00_0
#define GPIO_H_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_H_SCR_00_0
#define GPIO_H_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14218

// Reserved address 0x1421c

// Register GPIO_H_ENABLE_CONFIG_01_0
#define GPIO_H_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x14220)
#define GPIO_H_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_01_0_SCR                   GPIO_H_SCR_01_0
#define GPIO_H_ENABLE_CONFIG_01_0_SCRREG                        GPIO_H_SCR_01_0
#define GPIO_H_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_01_0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x14224)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_H_SCR_01_0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_H_SCR_01_0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_01_0
#define GPIO_H_INPUT_01_0                       MK_ADDR_CONST(0x14228)
#define GPIO_H_INPUT_01_0_SECURE                        0x0
#define GPIO_H_INPUT_01_0_DUAL                  0x0
#define GPIO_H_INPUT_01_0_SCR                   GPIO_H_SCR_01_0
#define GPIO_H_INPUT_01_0_SCRREG                        GPIO_H_SCR_01_0
#define GPIO_H_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_01_0
#define GPIO_H_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1422c)
#define GPIO_H_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_01_0_SCR                  GPIO_H_SCR_01_0
#define GPIO_H_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_H_SCR_01_0
#define GPIO_H_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_01_0
#define GPIO_H_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x14230)
#define GPIO_H_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_01_0_SCR                    GPIO_H_SCR_01_0
#define GPIO_H_OUTPUT_VALUE_01_0_SCRREG                         GPIO_H_SCR_01_0
#define GPIO_H_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_01_0
#define GPIO_H_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x14234)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_01_0_SCR                         GPIO_H_SCR_01_0
#define GPIO_H_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_H_SCR_01_0
#define GPIO_H_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14238

// Reserved address 0x1423c

// Register GPIO_H_ENABLE_CONFIG_02_0
#define GPIO_H_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x14240)
#define GPIO_H_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_02_0_SCR                   GPIO_H_SCR_02_0
#define GPIO_H_ENABLE_CONFIG_02_0_SCRREG                        GPIO_H_SCR_02_0
#define GPIO_H_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_02_0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x14244)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_H_SCR_02_0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_H_SCR_02_0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_02_0
#define GPIO_H_INPUT_02_0                       MK_ADDR_CONST(0x14248)
#define GPIO_H_INPUT_02_0_SECURE                        0x0
#define GPIO_H_INPUT_02_0_DUAL                  0x0
#define GPIO_H_INPUT_02_0_SCR                   GPIO_H_SCR_02_0
#define GPIO_H_INPUT_02_0_SCRREG                        GPIO_H_SCR_02_0
#define GPIO_H_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_02_0
#define GPIO_H_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1424c)
#define GPIO_H_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_02_0_SCR                  GPIO_H_SCR_02_0
#define GPIO_H_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_H_SCR_02_0
#define GPIO_H_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_02_0
#define GPIO_H_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x14250)
#define GPIO_H_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_02_0_SCR                    GPIO_H_SCR_02_0
#define GPIO_H_OUTPUT_VALUE_02_0_SCRREG                         GPIO_H_SCR_02_0
#define GPIO_H_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_02_0
#define GPIO_H_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x14254)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_02_0_SCR                         GPIO_H_SCR_02_0
#define GPIO_H_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_H_SCR_02_0
#define GPIO_H_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14258

// Reserved address 0x1425c

// Register GPIO_H_ENABLE_CONFIG_03_0
#define GPIO_H_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x14260)
#define GPIO_H_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_03_0_SCR                   GPIO_H_SCR_03_0
#define GPIO_H_ENABLE_CONFIG_03_0_SCRREG                        GPIO_H_SCR_03_0
#define GPIO_H_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_03_0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x14264)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_H_SCR_03_0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_H_SCR_03_0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_03_0
#define GPIO_H_INPUT_03_0                       MK_ADDR_CONST(0x14268)
#define GPIO_H_INPUT_03_0_SECURE                        0x0
#define GPIO_H_INPUT_03_0_DUAL                  0x0
#define GPIO_H_INPUT_03_0_SCR                   GPIO_H_SCR_03_0
#define GPIO_H_INPUT_03_0_SCRREG                        GPIO_H_SCR_03_0
#define GPIO_H_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_03_0
#define GPIO_H_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1426c)
#define GPIO_H_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_03_0_SCR                  GPIO_H_SCR_03_0
#define GPIO_H_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_H_SCR_03_0
#define GPIO_H_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_03_0
#define GPIO_H_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x14270)
#define GPIO_H_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_03_0_SCR                    GPIO_H_SCR_03_0
#define GPIO_H_OUTPUT_VALUE_03_0_SCRREG                         GPIO_H_SCR_03_0
#define GPIO_H_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_03_0
#define GPIO_H_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x14274)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_03_0_SCR                         GPIO_H_SCR_03_0
#define GPIO_H_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_H_SCR_03_0
#define GPIO_H_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14278

// Reserved address 0x1427c

// Register GPIO_H_ENABLE_CONFIG_04_0
#define GPIO_H_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x14280)
#define GPIO_H_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_04_0_SCR                   GPIO_H_SCR_04_0
#define GPIO_H_ENABLE_CONFIG_04_0_SCRREG                        GPIO_H_SCR_04_0
#define GPIO_H_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_04_0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x14284)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_H_SCR_04_0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_H_SCR_04_0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_04_0
#define GPIO_H_INPUT_04_0                       MK_ADDR_CONST(0x14288)
#define GPIO_H_INPUT_04_0_SECURE                        0x0
#define GPIO_H_INPUT_04_0_DUAL                  0x0
#define GPIO_H_INPUT_04_0_SCR                   GPIO_H_SCR_04_0
#define GPIO_H_INPUT_04_0_SCRREG                        GPIO_H_SCR_04_0
#define GPIO_H_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_04_0
#define GPIO_H_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1428c)
#define GPIO_H_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_04_0_SCR                  GPIO_H_SCR_04_0
#define GPIO_H_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_H_SCR_04_0
#define GPIO_H_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_04_0
#define GPIO_H_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x14290)
#define GPIO_H_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_04_0_SCR                    GPIO_H_SCR_04_0
#define GPIO_H_OUTPUT_VALUE_04_0_SCRREG                         GPIO_H_SCR_04_0
#define GPIO_H_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_04_0
#define GPIO_H_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x14294)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_04_0_SCR                         GPIO_H_SCR_04_0
#define GPIO_H_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_H_SCR_04_0
#define GPIO_H_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14298

// Reserved address 0x1429c

// Register GPIO_H_ENABLE_CONFIG_05_0
#define GPIO_H_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x142a0)
#define GPIO_H_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_05_0_SCR                   GPIO_H_SCR_05_0
#define GPIO_H_ENABLE_CONFIG_05_0_SCRREG                        GPIO_H_SCR_05_0
#define GPIO_H_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_05_0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x142a4)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_H_SCR_05_0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_H_SCR_05_0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_05_0
#define GPIO_H_INPUT_05_0                       MK_ADDR_CONST(0x142a8)
#define GPIO_H_INPUT_05_0_SECURE                        0x0
#define GPIO_H_INPUT_05_0_DUAL                  0x0
#define GPIO_H_INPUT_05_0_SCR                   GPIO_H_SCR_05_0
#define GPIO_H_INPUT_05_0_SCRREG                        GPIO_H_SCR_05_0
#define GPIO_H_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_05_0
#define GPIO_H_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x142ac)
#define GPIO_H_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_05_0_SCR                  GPIO_H_SCR_05_0
#define GPIO_H_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_H_SCR_05_0
#define GPIO_H_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_05_0
#define GPIO_H_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x142b0)
#define GPIO_H_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_05_0_SCR                    GPIO_H_SCR_05_0
#define GPIO_H_OUTPUT_VALUE_05_0_SCRREG                         GPIO_H_SCR_05_0
#define GPIO_H_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_05_0
#define GPIO_H_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x142b4)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_05_0_SCR                         GPIO_H_SCR_05_0
#define GPIO_H_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_H_SCR_05_0
#define GPIO_H_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x142b8

// Reserved address 0x142bc

// Register GPIO_H_ENABLE_CONFIG_06_0
#define GPIO_H_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x142c0)
#define GPIO_H_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_06_0_SCR                   GPIO_H_SCR_06_0
#define GPIO_H_ENABLE_CONFIG_06_0_SCRREG                        GPIO_H_SCR_06_0
#define GPIO_H_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_06_0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x142c4)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_H_SCR_06_0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_H_SCR_06_0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_06_0
#define GPIO_H_INPUT_06_0                       MK_ADDR_CONST(0x142c8)
#define GPIO_H_INPUT_06_0_SECURE                        0x0
#define GPIO_H_INPUT_06_0_DUAL                  0x0
#define GPIO_H_INPUT_06_0_SCR                   GPIO_H_SCR_06_0
#define GPIO_H_INPUT_06_0_SCRREG                        GPIO_H_SCR_06_0
#define GPIO_H_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_06_0
#define GPIO_H_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x142cc)
#define GPIO_H_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_06_0_SCR                  GPIO_H_SCR_06_0
#define GPIO_H_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_H_SCR_06_0
#define GPIO_H_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_06_0
#define GPIO_H_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x142d0)
#define GPIO_H_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_06_0_SCR                    GPIO_H_SCR_06_0
#define GPIO_H_OUTPUT_VALUE_06_0_SCRREG                         GPIO_H_SCR_06_0
#define GPIO_H_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_06_0
#define GPIO_H_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x142d4)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_06_0_SCR                         GPIO_H_SCR_06_0
#define GPIO_H_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_H_SCR_06_0
#define GPIO_H_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x142d8

// Reserved address 0x142dc

// Register GPIO_H_ENABLE_CONFIG_07_0
#define GPIO_H_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x142e0)
#define GPIO_H_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_H_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_H_ENABLE_CONFIG_07_0_SCR                   GPIO_H_SCR_07_0
#define GPIO_H_ENABLE_CONFIG_07_0_SCRREG                        GPIO_H_SCR_07_0
#define GPIO_H_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_H_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_H_DEBOUNCE_THRESHOLD_07_0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x142e4)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_H_SCR_07_0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_H_SCR_07_0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_INPUT_07_0
#define GPIO_H_INPUT_07_0                       MK_ADDR_CONST(0x142e8)
#define GPIO_H_INPUT_07_0_SECURE                        0x0
#define GPIO_H_INPUT_07_0_DUAL                  0x0
#define GPIO_H_INPUT_07_0_SCR                   GPIO_H_SCR_07_0
#define GPIO_H_INPUT_07_0_SCRREG                        GPIO_H_SCR_07_0
#define GPIO_H_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_H_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_H_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_H_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_H_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_H_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_H_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_H_OUTPUT_CONTROL_07_0
#define GPIO_H_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x142ec)
#define GPIO_H_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_H_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_H_OUTPUT_CONTROL_07_0_SCR                  GPIO_H_SCR_07_0
#define GPIO_H_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_H_SCR_07_0
#define GPIO_H_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_H_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_H_OUTPUT_VALUE_07_0
#define GPIO_H_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x142f0)
#define GPIO_H_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_H_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_H_OUTPUT_VALUE_07_0_SCR                    GPIO_H_SCR_07_0
#define GPIO_H_OUTPUT_VALUE_07_0_SCRREG                         GPIO_H_SCR_07_0
#define GPIO_H_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_H_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_CLEAR_07_0
#define GPIO_H_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x142f4)
#define GPIO_H_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_H_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_H_INTERRUPT_CLEAR_07_0_SCR                         GPIO_H_SCR_07_0
#define GPIO_H_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_H_SCR_07_0
#define GPIO_H_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_H_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x142f8

// Reserved address 0x142fc

// Register GPIO_H_INTERRUPT_STATUS_G0_0
#define GPIO_H_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x14300)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_H_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G1_0
#define GPIO_H_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x14304)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_H_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G2_0
#define GPIO_H_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x14308)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_H_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G3_0
#define GPIO_H_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1430c)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_H_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G4_0
#define GPIO_H_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x14310)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_H_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G5_0
#define GPIO_H_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x14314)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_H_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G6_0
#define GPIO_H_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x14318)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_H_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_H_INTERRUPT_STATUS_G7_0
#define GPIO_H_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1431c)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_H_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_H_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_H_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_H_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_H_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x14320

// Reserved address 0x14324

// Reserved address 0x14328

// Reserved address 0x1432c

// Reserved address 0x14330

// Reserved address 0x14334

// Reserved address 0x14338

// Reserved address 0x1433c

// Reserved address 0x14340

// Reserved address 0x14344

// Reserved address 0x14348

// Reserved address 0x1434c

// Reserved address 0x14350

// Reserved address 0x14354

// Reserved address 0x14358

// Reserved address 0x1435c

// Reserved address 0x14360

// Reserved address 0x14364

// Reserved address 0x14368

// Reserved address 0x1436c

// Reserved address 0x14370

// Reserved address 0x14374

// Reserved address 0x14378

// Reserved address 0x1437c

// Reserved address 0x14380

// Reserved address 0x14384

// Reserved address 0x14388

// Reserved address 0x1438c

// Reserved address 0x14390

// Reserved address 0x14394

// Reserved address 0x14398

// Reserved address 0x1439c

// Reserved address 0x143a0

// Reserved address 0x143a4

// Reserved address 0x143a8

// Reserved address 0x143ac

// Reserved address 0x143b0

// Reserved address 0x143b4

// Reserved address 0x143b8

// Reserved address 0x143bc

// Reserved address 0x143c0

// Reserved address 0x143c4

// Reserved address 0x143c8

// Reserved address 0x143cc

// Reserved address 0x143d0

// Reserved address 0x143d4

// Reserved address 0x143d8

// Reserved address 0x143dc

// Reserved address 0x143e0

// Reserved address 0x143e4

// Reserved address 0x143e8

// Reserved address 0x143ec

// Reserved address 0x143f0

// Reserved address 0x143f4

// Reserved address 0x143f8

// Reserved address 0x143fc

// Register GPIO_I_ENABLE_CONFIG_00_0
#define GPIO_I_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x14400)
#define GPIO_I_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_00_0_SCR                   GPIO_I_SCR_00_0
#define GPIO_I_ENABLE_CONFIG_00_0_SCRREG                        GPIO_I_SCR_00_0
#define GPIO_I_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_00_0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x14404)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_I_SCR_00_0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_I_SCR_00_0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_00_0
#define GPIO_I_INPUT_00_0                       MK_ADDR_CONST(0x14408)
#define GPIO_I_INPUT_00_0_SECURE                        0x0
#define GPIO_I_INPUT_00_0_DUAL                  0x0
#define GPIO_I_INPUT_00_0_SCR                   GPIO_I_SCR_00_0
#define GPIO_I_INPUT_00_0_SCRREG                        GPIO_I_SCR_00_0
#define GPIO_I_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_00_0
#define GPIO_I_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1440c)
#define GPIO_I_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_00_0_SCR                  GPIO_I_SCR_00_0
#define GPIO_I_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_I_SCR_00_0
#define GPIO_I_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_00_0
#define GPIO_I_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x14410)
#define GPIO_I_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_00_0_SCR                    GPIO_I_SCR_00_0
#define GPIO_I_OUTPUT_VALUE_00_0_SCRREG                         GPIO_I_SCR_00_0
#define GPIO_I_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_00_0
#define GPIO_I_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x14414)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_00_0_SCR                         GPIO_I_SCR_00_0
#define GPIO_I_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_I_SCR_00_0
#define GPIO_I_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14418

// Reserved address 0x1441c

// Register GPIO_I_ENABLE_CONFIG_01_0
#define GPIO_I_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x14420)
#define GPIO_I_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_01_0_SCR                   GPIO_I_SCR_01_0
#define GPIO_I_ENABLE_CONFIG_01_0_SCRREG                        GPIO_I_SCR_01_0
#define GPIO_I_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_01_0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x14424)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_I_SCR_01_0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_I_SCR_01_0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_01_0
#define GPIO_I_INPUT_01_0                       MK_ADDR_CONST(0x14428)
#define GPIO_I_INPUT_01_0_SECURE                        0x0
#define GPIO_I_INPUT_01_0_DUAL                  0x0
#define GPIO_I_INPUT_01_0_SCR                   GPIO_I_SCR_01_0
#define GPIO_I_INPUT_01_0_SCRREG                        GPIO_I_SCR_01_0
#define GPIO_I_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_01_0
#define GPIO_I_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1442c)
#define GPIO_I_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_01_0_SCR                  GPIO_I_SCR_01_0
#define GPIO_I_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_I_SCR_01_0
#define GPIO_I_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_01_0
#define GPIO_I_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x14430)
#define GPIO_I_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_01_0_SCR                    GPIO_I_SCR_01_0
#define GPIO_I_OUTPUT_VALUE_01_0_SCRREG                         GPIO_I_SCR_01_0
#define GPIO_I_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_01_0
#define GPIO_I_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x14434)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_01_0_SCR                         GPIO_I_SCR_01_0
#define GPIO_I_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_I_SCR_01_0
#define GPIO_I_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14438

// Reserved address 0x1443c

// Register GPIO_I_ENABLE_CONFIG_02_0
#define GPIO_I_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x14440)
#define GPIO_I_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_02_0_SCR                   GPIO_I_SCR_02_0
#define GPIO_I_ENABLE_CONFIG_02_0_SCRREG                        GPIO_I_SCR_02_0
#define GPIO_I_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_02_0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x14444)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_I_SCR_02_0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_I_SCR_02_0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_02_0
#define GPIO_I_INPUT_02_0                       MK_ADDR_CONST(0x14448)
#define GPIO_I_INPUT_02_0_SECURE                        0x0
#define GPIO_I_INPUT_02_0_DUAL                  0x0
#define GPIO_I_INPUT_02_0_SCR                   GPIO_I_SCR_02_0
#define GPIO_I_INPUT_02_0_SCRREG                        GPIO_I_SCR_02_0
#define GPIO_I_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_02_0
#define GPIO_I_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1444c)
#define GPIO_I_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_02_0_SCR                  GPIO_I_SCR_02_0
#define GPIO_I_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_I_SCR_02_0
#define GPIO_I_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_02_0
#define GPIO_I_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x14450)
#define GPIO_I_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_02_0_SCR                    GPIO_I_SCR_02_0
#define GPIO_I_OUTPUT_VALUE_02_0_SCRREG                         GPIO_I_SCR_02_0
#define GPIO_I_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_02_0
#define GPIO_I_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x14454)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_02_0_SCR                         GPIO_I_SCR_02_0
#define GPIO_I_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_I_SCR_02_0
#define GPIO_I_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14458

// Reserved address 0x1445c

// Register GPIO_I_ENABLE_CONFIG_03_0
#define GPIO_I_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x14460)
#define GPIO_I_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_03_0_SCR                   GPIO_I_SCR_03_0
#define GPIO_I_ENABLE_CONFIG_03_0_SCRREG                        GPIO_I_SCR_03_0
#define GPIO_I_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_03_0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x14464)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_I_SCR_03_0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_I_SCR_03_0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_03_0
#define GPIO_I_INPUT_03_0                       MK_ADDR_CONST(0x14468)
#define GPIO_I_INPUT_03_0_SECURE                        0x0
#define GPIO_I_INPUT_03_0_DUAL                  0x0
#define GPIO_I_INPUT_03_0_SCR                   GPIO_I_SCR_03_0
#define GPIO_I_INPUT_03_0_SCRREG                        GPIO_I_SCR_03_0
#define GPIO_I_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_03_0
#define GPIO_I_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1446c)
#define GPIO_I_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_03_0_SCR                  GPIO_I_SCR_03_0
#define GPIO_I_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_I_SCR_03_0
#define GPIO_I_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_03_0
#define GPIO_I_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x14470)
#define GPIO_I_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_03_0_SCR                    GPIO_I_SCR_03_0
#define GPIO_I_OUTPUT_VALUE_03_0_SCRREG                         GPIO_I_SCR_03_0
#define GPIO_I_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_03_0
#define GPIO_I_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x14474)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_03_0_SCR                         GPIO_I_SCR_03_0
#define GPIO_I_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_I_SCR_03_0
#define GPIO_I_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14478

// Reserved address 0x1447c

// Register GPIO_I_ENABLE_CONFIG_04_0
#define GPIO_I_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x14480)
#define GPIO_I_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_04_0_SCR                   GPIO_I_SCR_04_0
#define GPIO_I_ENABLE_CONFIG_04_0_SCRREG                        GPIO_I_SCR_04_0
#define GPIO_I_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_04_0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x14484)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_I_SCR_04_0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_I_SCR_04_0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_04_0
#define GPIO_I_INPUT_04_0                       MK_ADDR_CONST(0x14488)
#define GPIO_I_INPUT_04_0_SECURE                        0x0
#define GPIO_I_INPUT_04_0_DUAL                  0x0
#define GPIO_I_INPUT_04_0_SCR                   GPIO_I_SCR_04_0
#define GPIO_I_INPUT_04_0_SCRREG                        GPIO_I_SCR_04_0
#define GPIO_I_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_04_0
#define GPIO_I_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1448c)
#define GPIO_I_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_04_0_SCR                  GPIO_I_SCR_04_0
#define GPIO_I_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_I_SCR_04_0
#define GPIO_I_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_04_0
#define GPIO_I_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x14490)
#define GPIO_I_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_04_0_SCR                    GPIO_I_SCR_04_0
#define GPIO_I_OUTPUT_VALUE_04_0_SCRREG                         GPIO_I_SCR_04_0
#define GPIO_I_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_04_0
#define GPIO_I_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x14494)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_04_0_SCR                         GPIO_I_SCR_04_0
#define GPIO_I_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_I_SCR_04_0
#define GPIO_I_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x14498

// Reserved address 0x1449c

// Register GPIO_I_ENABLE_CONFIG_05_0
#define GPIO_I_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x144a0)
#define GPIO_I_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_05_0_SCR                   GPIO_I_SCR_05_0
#define GPIO_I_ENABLE_CONFIG_05_0_SCRREG                        GPIO_I_SCR_05_0
#define GPIO_I_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_05_0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x144a4)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_I_SCR_05_0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_I_SCR_05_0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_05_0
#define GPIO_I_INPUT_05_0                       MK_ADDR_CONST(0x144a8)
#define GPIO_I_INPUT_05_0_SECURE                        0x0
#define GPIO_I_INPUT_05_0_DUAL                  0x0
#define GPIO_I_INPUT_05_0_SCR                   GPIO_I_SCR_05_0
#define GPIO_I_INPUT_05_0_SCRREG                        GPIO_I_SCR_05_0
#define GPIO_I_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_05_0
#define GPIO_I_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x144ac)
#define GPIO_I_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_05_0_SCR                  GPIO_I_SCR_05_0
#define GPIO_I_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_I_SCR_05_0
#define GPIO_I_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_05_0
#define GPIO_I_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x144b0)
#define GPIO_I_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_05_0_SCR                    GPIO_I_SCR_05_0
#define GPIO_I_OUTPUT_VALUE_05_0_SCRREG                         GPIO_I_SCR_05_0
#define GPIO_I_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_05_0
#define GPIO_I_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x144b4)
#define GPIO_I_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_05_0_SCR                         GPIO_I_SCR_05_0
#define GPIO_I_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_I_SCR_05_0
#define GPIO_I_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x144b8

// Reserved address 0x144bc

// Register GPIO_I_ENABLE_CONFIG_06_0
#define GPIO_I_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x144c0)
#define GPIO_I_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_I_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_I_ENABLE_CONFIG_06_0_SCR                   GPIO_I_SCR_06_0
#define GPIO_I_ENABLE_CONFIG_06_0_SCRREG                        GPIO_I_SCR_06_0
#define GPIO_I_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_I_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_I_DEBOUNCE_THRESHOLD_06_0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x144c4)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_I_SCR_06_0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_I_SCR_06_0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_INPUT_06_0
#define GPIO_I_INPUT_06_0                       MK_ADDR_CONST(0x144c8)
#define GPIO_I_INPUT_06_0_SECURE                        0x0
#define GPIO_I_INPUT_06_0_DUAL                  0x0
#define GPIO_I_INPUT_06_0_SCR                   GPIO_I_SCR_06_0
#define GPIO_I_INPUT_06_0_SCRREG                        GPIO_I_SCR_06_0
#define GPIO_I_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_I_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_I_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_I_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_I_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_I_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_I_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_I_OUTPUT_CONTROL_06_0
#define GPIO_I_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x144cc)
#define GPIO_I_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_I_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_I_OUTPUT_CONTROL_06_0_SCR                  GPIO_I_SCR_06_0
#define GPIO_I_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_I_SCR_06_0
#define GPIO_I_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_I_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_I_OUTPUT_VALUE_06_0
#define GPIO_I_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x144d0)
#define GPIO_I_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_I_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_I_OUTPUT_VALUE_06_0_SCR                    GPIO_I_SCR_06_0
#define GPIO_I_OUTPUT_VALUE_06_0_SCRREG                         GPIO_I_SCR_06_0
#define GPIO_I_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_I_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_CLEAR_06_0
#define GPIO_I_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x144d4)
#define GPIO_I_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_I_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_I_INTERRUPT_CLEAR_06_0_SCR                         GPIO_I_SCR_06_0
#define GPIO_I_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_I_SCR_06_0
#define GPIO_I_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_I_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x144d8

// Reserved address 0x144dc

// Reserved address 0x144e0

// Reserved address 0x144e4

// Reserved address 0x144e8

// Reserved address 0x144ec

// Reserved address 0x144f0

// Reserved address 0x144f4

// Reserved address 0x144f8

// Reserved address 0x144fc

// Register GPIO_I_INTERRUPT_STATUS_G0_0
#define GPIO_I_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x14500)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_I_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G1_0
#define GPIO_I_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x14504)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_I_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G2_0
#define GPIO_I_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x14508)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_I_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G3_0
#define GPIO_I_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1450c)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_I_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G4_0
#define GPIO_I_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x14510)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_I_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G5_0
#define GPIO_I_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x14514)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_I_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G6_0
#define GPIO_I_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x14518)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_I_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_I_INTERRUPT_STATUS_G7_0
#define GPIO_I_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1451c)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_I_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_I_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_I_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_I_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_I_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x14520

// Reserved address 0x14524

// Reserved address 0x14528

// Reserved address 0x1452c

// Reserved address 0x14530

// Reserved address 0x14534

// Reserved address 0x14538

// Reserved address 0x1453c

// Reserved address 0x14540

// Reserved address 0x14544

// Reserved address 0x14548

// Reserved address 0x1454c

// Reserved address 0x14550

// Reserved address 0x14554

// Reserved address 0x14558

// Reserved address 0x1455c

// Reserved address 0x14560

// Reserved address 0x14564

// Reserved address 0x14568

// Reserved address 0x1456c

// Reserved address 0x14570

// Reserved address 0x14574

// Reserved address 0x14578

// Reserved address 0x1457c

// Reserved address 0x14580

// Reserved address 0x14584

// Reserved address 0x14588

// Reserved address 0x1458c

// Reserved address 0x14590

// Reserved address 0x14594

// Reserved address 0x14598

// Reserved address 0x1459c

// Reserved address 0x145a0

// Reserved address 0x145a4

// Reserved address 0x145a8

// Reserved address 0x145ac

// Reserved address 0x145b0

// Reserved address 0x145b4

// Reserved address 0x145b8

// Reserved address 0x145bc

// Reserved address 0x145c0

// Reserved address 0x145c4

// Reserved address 0x145c8

// Reserved address 0x145cc

// Reserved address 0x145d0

// Reserved address 0x145d4

// Reserved address 0x145d8

// Reserved address 0x145dc

// Reserved address 0x145e0

// Reserved address 0x145e4

// Reserved address 0x145e8

// Reserved address 0x145ec

// Reserved address 0x145f0

// Reserved address 0x145f4

// Reserved address 0x145f8

// Reserved address 0x145fc

// Register GPIO_J_ENABLE_CONFIG_00_0
#define GPIO_J_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15000)
#define GPIO_J_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_00_0_SCR                   GPIO_J_SCR_00_0
#define GPIO_J_ENABLE_CONFIG_00_0_SCRREG                        GPIO_J_SCR_00_0
#define GPIO_J_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_00_0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15004)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_J_SCR_00_0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_J_SCR_00_0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_00_0
#define GPIO_J_INPUT_00_0                       MK_ADDR_CONST(0x15008)
#define GPIO_J_INPUT_00_0_SECURE                        0x0
#define GPIO_J_INPUT_00_0_DUAL                  0x0
#define GPIO_J_INPUT_00_0_SCR                   GPIO_J_SCR_00_0
#define GPIO_J_INPUT_00_0_SCRREG                        GPIO_J_SCR_00_0
#define GPIO_J_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_00_0
#define GPIO_J_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1500c)
#define GPIO_J_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_00_0_SCR                  GPIO_J_SCR_00_0
#define GPIO_J_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_J_SCR_00_0
#define GPIO_J_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_00_0
#define GPIO_J_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15010)
#define GPIO_J_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_00_0_SCR                    GPIO_J_SCR_00_0
#define GPIO_J_OUTPUT_VALUE_00_0_SCRREG                         GPIO_J_SCR_00_0
#define GPIO_J_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_00_0
#define GPIO_J_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15014)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_00_0_SCR                         GPIO_J_SCR_00_0
#define GPIO_J_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_J_SCR_00_0
#define GPIO_J_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15018

// Reserved address 0x1501c

// Register GPIO_J_ENABLE_CONFIG_01_0
#define GPIO_J_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15020)
#define GPIO_J_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_01_0_SCR                   GPIO_J_SCR_01_0
#define GPIO_J_ENABLE_CONFIG_01_0_SCRREG                        GPIO_J_SCR_01_0
#define GPIO_J_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_01_0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15024)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_J_SCR_01_0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_J_SCR_01_0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_01_0
#define GPIO_J_INPUT_01_0                       MK_ADDR_CONST(0x15028)
#define GPIO_J_INPUT_01_0_SECURE                        0x0
#define GPIO_J_INPUT_01_0_DUAL                  0x0
#define GPIO_J_INPUT_01_0_SCR                   GPIO_J_SCR_01_0
#define GPIO_J_INPUT_01_0_SCRREG                        GPIO_J_SCR_01_0
#define GPIO_J_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_01_0
#define GPIO_J_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1502c)
#define GPIO_J_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_01_0_SCR                  GPIO_J_SCR_01_0
#define GPIO_J_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_J_SCR_01_0
#define GPIO_J_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_01_0
#define GPIO_J_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15030)
#define GPIO_J_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_01_0_SCR                    GPIO_J_SCR_01_0
#define GPIO_J_OUTPUT_VALUE_01_0_SCRREG                         GPIO_J_SCR_01_0
#define GPIO_J_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_01_0
#define GPIO_J_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15034)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_01_0_SCR                         GPIO_J_SCR_01_0
#define GPIO_J_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_J_SCR_01_0
#define GPIO_J_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15038

// Reserved address 0x1503c

// Register GPIO_J_ENABLE_CONFIG_02_0
#define GPIO_J_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15040)
#define GPIO_J_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_02_0_SCR                   GPIO_J_SCR_02_0
#define GPIO_J_ENABLE_CONFIG_02_0_SCRREG                        GPIO_J_SCR_02_0
#define GPIO_J_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_02_0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15044)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_J_SCR_02_0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_J_SCR_02_0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_02_0
#define GPIO_J_INPUT_02_0                       MK_ADDR_CONST(0x15048)
#define GPIO_J_INPUT_02_0_SECURE                        0x0
#define GPIO_J_INPUT_02_0_DUAL                  0x0
#define GPIO_J_INPUT_02_0_SCR                   GPIO_J_SCR_02_0
#define GPIO_J_INPUT_02_0_SCRREG                        GPIO_J_SCR_02_0
#define GPIO_J_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_02_0
#define GPIO_J_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1504c)
#define GPIO_J_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_02_0_SCR                  GPIO_J_SCR_02_0
#define GPIO_J_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_J_SCR_02_0
#define GPIO_J_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_02_0
#define GPIO_J_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15050)
#define GPIO_J_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_02_0_SCR                    GPIO_J_SCR_02_0
#define GPIO_J_OUTPUT_VALUE_02_0_SCRREG                         GPIO_J_SCR_02_0
#define GPIO_J_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_02_0
#define GPIO_J_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15054)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_02_0_SCR                         GPIO_J_SCR_02_0
#define GPIO_J_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_J_SCR_02_0
#define GPIO_J_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15058

// Reserved address 0x1505c

// Register GPIO_J_ENABLE_CONFIG_03_0
#define GPIO_J_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15060)
#define GPIO_J_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_03_0_SCR                   GPIO_J_SCR_03_0
#define GPIO_J_ENABLE_CONFIG_03_0_SCRREG                        GPIO_J_SCR_03_0
#define GPIO_J_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_03_0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15064)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_J_SCR_03_0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_J_SCR_03_0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_03_0
#define GPIO_J_INPUT_03_0                       MK_ADDR_CONST(0x15068)
#define GPIO_J_INPUT_03_0_SECURE                        0x0
#define GPIO_J_INPUT_03_0_DUAL                  0x0
#define GPIO_J_INPUT_03_0_SCR                   GPIO_J_SCR_03_0
#define GPIO_J_INPUT_03_0_SCRREG                        GPIO_J_SCR_03_0
#define GPIO_J_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_03_0
#define GPIO_J_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1506c)
#define GPIO_J_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_03_0_SCR                  GPIO_J_SCR_03_0
#define GPIO_J_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_J_SCR_03_0
#define GPIO_J_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_03_0
#define GPIO_J_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15070)
#define GPIO_J_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_03_0_SCR                    GPIO_J_SCR_03_0
#define GPIO_J_OUTPUT_VALUE_03_0_SCRREG                         GPIO_J_SCR_03_0
#define GPIO_J_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_03_0
#define GPIO_J_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15074)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_03_0_SCR                         GPIO_J_SCR_03_0
#define GPIO_J_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_J_SCR_03_0
#define GPIO_J_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15078

// Reserved address 0x1507c

// Register GPIO_J_ENABLE_CONFIG_04_0
#define GPIO_J_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x15080)
#define GPIO_J_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_04_0_SCR                   GPIO_J_SCR_04_0
#define GPIO_J_ENABLE_CONFIG_04_0_SCRREG                        GPIO_J_SCR_04_0
#define GPIO_J_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_04_0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x15084)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_J_SCR_04_0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_J_SCR_04_0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_04_0
#define GPIO_J_INPUT_04_0                       MK_ADDR_CONST(0x15088)
#define GPIO_J_INPUT_04_0_SECURE                        0x0
#define GPIO_J_INPUT_04_0_DUAL                  0x0
#define GPIO_J_INPUT_04_0_SCR                   GPIO_J_SCR_04_0
#define GPIO_J_INPUT_04_0_SCRREG                        GPIO_J_SCR_04_0
#define GPIO_J_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_04_0
#define GPIO_J_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1508c)
#define GPIO_J_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_04_0_SCR                  GPIO_J_SCR_04_0
#define GPIO_J_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_J_SCR_04_0
#define GPIO_J_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_04_0
#define GPIO_J_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x15090)
#define GPIO_J_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_04_0_SCR                    GPIO_J_SCR_04_0
#define GPIO_J_OUTPUT_VALUE_04_0_SCRREG                         GPIO_J_SCR_04_0
#define GPIO_J_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_04_0
#define GPIO_J_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x15094)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_04_0_SCR                         GPIO_J_SCR_04_0
#define GPIO_J_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_J_SCR_04_0
#define GPIO_J_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15098

// Reserved address 0x1509c

// Register GPIO_J_ENABLE_CONFIG_05_0
#define GPIO_J_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x150a0)
#define GPIO_J_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_J_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_J_ENABLE_CONFIG_05_0_SCR                   GPIO_J_SCR_05_0
#define GPIO_J_ENABLE_CONFIG_05_0_SCRREG                        GPIO_J_SCR_05_0
#define GPIO_J_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_J_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_J_DEBOUNCE_THRESHOLD_05_0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x150a4)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_J_SCR_05_0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_J_SCR_05_0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_INPUT_05_0
#define GPIO_J_INPUT_05_0                       MK_ADDR_CONST(0x150a8)
#define GPIO_J_INPUT_05_0_SECURE                        0x0
#define GPIO_J_INPUT_05_0_DUAL                  0x0
#define GPIO_J_INPUT_05_0_SCR                   GPIO_J_SCR_05_0
#define GPIO_J_INPUT_05_0_SCRREG                        GPIO_J_SCR_05_0
#define GPIO_J_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_J_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_J_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_J_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_J_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_J_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_J_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_J_OUTPUT_CONTROL_05_0
#define GPIO_J_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x150ac)
#define GPIO_J_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_J_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_J_OUTPUT_CONTROL_05_0_SCR                  GPIO_J_SCR_05_0
#define GPIO_J_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_J_SCR_05_0
#define GPIO_J_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_J_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_J_OUTPUT_VALUE_05_0
#define GPIO_J_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x150b0)
#define GPIO_J_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_J_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_J_OUTPUT_VALUE_05_0_SCR                    GPIO_J_SCR_05_0
#define GPIO_J_OUTPUT_VALUE_05_0_SCRREG                         GPIO_J_SCR_05_0
#define GPIO_J_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_J_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_CLEAR_05_0
#define GPIO_J_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x150b4)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_J_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_J_INTERRUPT_CLEAR_05_0_SCR                         GPIO_J_SCR_05_0
#define GPIO_J_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_J_SCR_05_0
#define GPIO_J_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_J_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x150b8

// Reserved address 0x150bc

// Reserved address 0x150c0

// Reserved address 0x150c4

// Reserved address 0x150c8

// Reserved address 0x150cc

// Reserved address 0x150d0

// Reserved address 0x150d4

// Reserved address 0x150d8

// Reserved address 0x150dc

// Reserved address 0x150e0

// Reserved address 0x150e4

// Reserved address 0x150e8

// Reserved address 0x150ec

// Reserved address 0x150f0

// Reserved address 0x150f4

// Reserved address 0x150f8

// Reserved address 0x150fc

// Register GPIO_J_INTERRUPT_STATUS_G0_0
#define GPIO_J_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15100)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_J_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G1_0
#define GPIO_J_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15104)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_J_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G2_0
#define GPIO_J_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15108)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_J_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G3_0
#define GPIO_J_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1510c)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_J_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G4_0
#define GPIO_J_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15110)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_J_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G5_0
#define GPIO_J_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15114)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_J_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G6_0
#define GPIO_J_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15118)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_J_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_J_INTERRUPT_STATUS_G7_0
#define GPIO_J_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1511c)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_J_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_J_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_J_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_J_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_J_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x15120

// Reserved address 0x15124

// Reserved address 0x15128

// Reserved address 0x1512c

// Reserved address 0x15130

// Reserved address 0x15134

// Reserved address 0x15138

// Reserved address 0x1513c

// Reserved address 0x15140

// Reserved address 0x15144

// Reserved address 0x15148

// Reserved address 0x1514c

// Reserved address 0x15150

// Reserved address 0x15154

// Reserved address 0x15158

// Reserved address 0x1515c

// Reserved address 0x15160

// Reserved address 0x15164

// Reserved address 0x15168

// Reserved address 0x1516c

// Reserved address 0x15170

// Reserved address 0x15174

// Reserved address 0x15178

// Reserved address 0x1517c

// Reserved address 0x15180

// Reserved address 0x15184

// Reserved address 0x15188

// Reserved address 0x1518c

// Reserved address 0x15190

// Reserved address 0x15194

// Reserved address 0x15198

// Reserved address 0x1519c

// Reserved address 0x151a0

// Reserved address 0x151a4

// Reserved address 0x151a8

// Reserved address 0x151ac

// Reserved address 0x151b0

// Reserved address 0x151b4

// Reserved address 0x151b8

// Reserved address 0x151bc

// Reserved address 0x151c0

// Reserved address 0x151c4

// Reserved address 0x151c8

// Reserved address 0x151cc

// Reserved address 0x151d0

// Reserved address 0x151d4

// Reserved address 0x151d8

// Reserved address 0x151dc

// Reserved address 0x151e0

// Reserved address 0x151e4

// Reserved address 0x151e8

// Reserved address 0x151ec

// Reserved address 0x151f0

// Reserved address 0x151f4

// Reserved address 0x151f8

// Reserved address 0x151fc

// Register GPIO_C_ENABLE_CONFIG_00_0
#define GPIO_C_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15200)
#define GPIO_C_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_00_0_SCR                   GPIO_C_SCR_00_0
#define GPIO_C_ENABLE_CONFIG_00_0_SCRREG                        GPIO_C_SCR_00_0
#define GPIO_C_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_00_0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15204)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_C_SCR_00_0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_C_SCR_00_0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_00_0
#define GPIO_C_INPUT_00_0                       MK_ADDR_CONST(0x15208)
#define GPIO_C_INPUT_00_0_SECURE                        0x0
#define GPIO_C_INPUT_00_0_DUAL                  0x0
#define GPIO_C_INPUT_00_0_SCR                   GPIO_C_SCR_00_0
#define GPIO_C_INPUT_00_0_SCRREG                        GPIO_C_SCR_00_0
#define GPIO_C_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_00_0
#define GPIO_C_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1520c)
#define GPIO_C_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_00_0_SCR                  GPIO_C_SCR_00_0
#define GPIO_C_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_C_SCR_00_0
#define GPIO_C_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_00_0
#define GPIO_C_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15210)
#define GPIO_C_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_00_0_SCR                    GPIO_C_SCR_00_0
#define GPIO_C_OUTPUT_VALUE_00_0_SCRREG                         GPIO_C_SCR_00_0
#define GPIO_C_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_00_0
#define GPIO_C_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15214)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_00_0_SCR                         GPIO_C_SCR_00_0
#define GPIO_C_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_C_SCR_00_0
#define GPIO_C_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15218

// Reserved address 0x1521c

// Register GPIO_C_ENABLE_CONFIG_01_0
#define GPIO_C_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15220)
#define GPIO_C_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_01_0_SCR                   GPIO_C_SCR_01_0
#define GPIO_C_ENABLE_CONFIG_01_0_SCRREG                        GPIO_C_SCR_01_0
#define GPIO_C_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_01_0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15224)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_C_SCR_01_0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_C_SCR_01_0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_01_0
#define GPIO_C_INPUT_01_0                       MK_ADDR_CONST(0x15228)
#define GPIO_C_INPUT_01_0_SECURE                        0x0
#define GPIO_C_INPUT_01_0_DUAL                  0x0
#define GPIO_C_INPUT_01_0_SCR                   GPIO_C_SCR_01_0
#define GPIO_C_INPUT_01_0_SCRREG                        GPIO_C_SCR_01_0
#define GPIO_C_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_01_0
#define GPIO_C_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1522c)
#define GPIO_C_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_01_0_SCR                  GPIO_C_SCR_01_0
#define GPIO_C_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_C_SCR_01_0
#define GPIO_C_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_01_0
#define GPIO_C_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15230)
#define GPIO_C_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_01_0_SCR                    GPIO_C_SCR_01_0
#define GPIO_C_OUTPUT_VALUE_01_0_SCRREG                         GPIO_C_SCR_01_0
#define GPIO_C_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_01_0
#define GPIO_C_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15234)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_01_0_SCR                         GPIO_C_SCR_01_0
#define GPIO_C_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_C_SCR_01_0
#define GPIO_C_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15238

// Reserved address 0x1523c

// Register GPIO_C_ENABLE_CONFIG_02_0
#define GPIO_C_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15240)
#define GPIO_C_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_02_0_SCR                   GPIO_C_SCR_02_0
#define GPIO_C_ENABLE_CONFIG_02_0_SCRREG                        GPIO_C_SCR_02_0
#define GPIO_C_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_02_0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15244)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_C_SCR_02_0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_C_SCR_02_0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_02_0
#define GPIO_C_INPUT_02_0                       MK_ADDR_CONST(0x15248)
#define GPIO_C_INPUT_02_0_SECURE                        0x0
#define GPIO_C_INPUT_02_0_DUAL                  0x0
#define GPIO_C_INPUT_02_0_SCR                   GPIO_C_SCR_02_0
#define GPIO_C_INPUT_02_0_SCRREG                        GPIO_C_SCR_02_0
#define GPIO_C_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_02_0
#define GPIO_C_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1524c)
#define GPIO_C_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_02_0_SCR                  GPIO_C_SCR_02_0
#define GPIO_C_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_C_SCR_02_0
#define GPIO_C_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_02_0
#define GPIO_C_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15250)
#define GPIO_C_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_02_0_SCR                    GPIO_C_SCR_02_0
#define GPIO_C_OUTPUT_VALUE_02_0_SCRREG                         GPIO_C_SCR_02_0
#define GPIO_C_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_02_0
#define GPIO_C_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15254)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_02_0_SCR                         GPIO_C_SCR_02_0
#define GPIO_C_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_C_SCR_02_0
#define GPIO_C_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15258

// Reserved address 0x1525c

// Register GPIO_C_ENABLE_CONFIG_03_0
#define GPIO_C_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15260)
#define GPIO_C_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_03_0_SCR                   GPIO_C_SCR_03_0
#define GPIO_C_ENABLE_CONFIG_03_0_SCRREG                        GPIO_C_SCR_03_0
#define GPIO_C_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_03_0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15264)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_C_SCR_03_0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_C_SCR_03_0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_03_0
#define GPIO_C_INPUT_03_0                       MK_ADDR_CONST(0x15268)
#define GPIO_C_INPUT_03_0_SECURE                        0x0
#define GPIO_C_INPUT_03_0_DUAL                  0x0
#define GPIO_C_INPUT_03_0_SCR                   GPIO_C_SCR_03_0
#define GPIO_C_INPUT_03_0_SCRREG                        GPIO_C_SCR_03_0
#define GPIO_C_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_03_0
#define GPIO_C_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1526c)
#define GPIO_C_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_03_0_SCR                  GPIO_C_SCR_03_0
#define GPIO_C_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_C_SCR_03_0
#define GPIO_C_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_03_0
#define GPIO_C_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15270)
#define GPIO_C_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_03_0_SCR                    GPIO_C_SCR_03_0
#define GPIO_C_OUTPUT_VALUE_03_0_SCRREG                         GPIO_C_SCR_03_0
#define GPIO_C_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_03_0
#define GPIO_C_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15274)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_03_0_SCR                         GPIO_C_SCR_03_0
#define GPIO_C_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_C_SCR_03_0
#define GPIO_C_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15278

// Reserved address 0x1527c

// Register GPIO_C_ENABLE_CONFIG_04_0
#define GPIO_C_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x15280)
#define GPIO_C_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_04_0_SCR                   GPIO_C_SCR_04_0
#define GPIO_C_ENABLE_CONFIG_04_0_SCRREG                        GPIO_C_SCR_04_0
#define GPIO_C_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_04_0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x15284)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_C_SCR_04_0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_C_SCR_04_0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_04_0
#define GPIO_C_INPUT_04_0                       MK_ADDR_CONST(0x15288)
#define GPIO_C_INPUT_04_0_SECURE                        0x0
#define GPIO_C_INPUT_04_0_DUAL                  0x0
#define GPIO_C_INPUT_04_0_SCR                   GPIO_C_SCR_04_0
#define GPIO_C_INPUT_04_0_SCRREG                        GPIO_C_SCR_04_0
#define GPIO_C_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_04_0
#define GPIO_C_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1528c)
#define GPIO_C_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_04_0_SCR                  GPIO_C_SCR_04_0
#define GPIO_C_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_C_SCR_04_0
#define GPIO_C_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_04_0
#define GPIO_C_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x15290)
#define GPIO_C_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_04_0_SCR                    GPIO_C_SCR_04_0
#define GPIO_C_OUTPUT_VALUE_04_0_SCRREG                         GPIO_C_SCR_04_0
#define GPIO_C_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_04_0
#define GPIO_C_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x15294)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_04_0_SCR                         GPIO_C_SCR_04_0
#define GPIO_C_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_C_SCR_04_0
#define GPIO_C_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15298

// Reserved address 0x1529c

// Register GPIO_C_ENABLE_CONFIG_05_0
#define GPIO_C_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x152a0)
#define GPIO_C_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_05_0_SCR                   GPIO_C_SCR_05_0
#define GPIO_C_ENABLE_CONFIG_05_0_SCRREG                        GPIO_C_SCR_05_0
#define GPIO_C_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_05_0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x152a4)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_C_SCR_05_0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_C_SCR_05_0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_05_0
#define GPIO_C_INPUT_05_0                       MK_ADDR_CONST(0x152a8)
#define GPIO_C_INPUT_05_0_SECURE                        0x0
#define GPIO_C_INPUT_05_0_DUAL                  0x0
#define GPIO_C_INPUT_05_0_SCR                   GPIO_C_SCR_05_0
#define GPIO_C_INPUT_05_0_SCRREG                        GPIO_C_SCR_05_0
#define GPIO_C_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_05_0
#define GPIO_C_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x152ac)
#define GPIO_C_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_05_0_SCR                  GPIO_C_SCR_05_0
#define GPIO_C_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_C_SCR_05_0
#define GPIO_C_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_05_0
#define GPIO_C_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x152b0)
#define GPIO_C_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_05_0_SCR                    GPIO_C_SCR_05_0
#define GPIO_C_OUTPUT_VALUE_05_0_SCRREG                         GPIO_C_SCR_05_0
#define GPIO_C_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_05_0
#define GPIO_C_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x152b4)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_05_0_SCR                         GPIO_C_SCR_05_0
#define GPIO_C_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_C_SCR_05_0
#define GPIO_C_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x152b8

// Reserved address 0x152bc

// Register GPIO_C_ENABLE_CONFIG_06_0
#define GPIO_C_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x152c0)
#define GPIO_C_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_06_0_SCR                   GPIO_C_SCR_06_0
#define GPIO_C_ENABLE_CONFIG_06_0_SCRREG                        GPIO_C_SCR_06_0
#define GPIO_C_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_06_0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x152c4)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_C_SCR_06_0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_C_SCR_06_0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_06_0
#define GPIO_C_INPUT_06_0                       MK_ADDR_CONST(0x152c8)
#define GPIO_C_INPUT_06_0_SECURE                        0x0
#define GPIO_C_INPUT_06_0_DUAL                  0x0
#define GPIO_C_INPUT_06_0_SCR                   GPIO_C_SCR_06_0
#define GPIO_C_INPUT_06_0_SCRREG                        GPIO_C_SCR_06_0
#define GPIO_C_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_06_0
#define GPIO_C_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x152cc)
#define GPIO_C_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_06_0_SCR                  GPIO_C_SCR_06_0
#define GPIO_C_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_C_SCR_06_0
#define GPIO_C_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_06_0
#define GPIO_C_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x152d0)
#define GPIO_C_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_06_0_SCR                    GPIO_C_SCR_06_0
#define GPIO_C_OUTPUT_VALUE_06_0_SCRREG                         GPIO_C_SCR_06_0
#define GPIO_C_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_06_0
#define GPIO_C_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x152d4)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_06_0_SCR                         GPIO_C_SCR_06_0
#define GPIO_C_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_C_SCR_06_0
#define GPIO_C_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x152d8

// Reserved address 0x152dc

// Register GPIO_C_ENABLE_CONFIG_07_0
#define GPIO_C_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x152e0)
#define GPIO_C_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_C_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_C_ENABLE_CONFIG_07_0_SCR                   GPIO_C_SCR_07_0
#define GPIO_C_ENABLE_CONFIG_07_0_SCRREG                        GPIO_C_SCR_07_0
#define GPIO_C_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_C_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_C_DEBOUNCE_THRESHOLD_07_0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x152e4)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_C_SCR_07_0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_C_SCR_07_0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_INPUT_07_0
#define GPIO_C_INPUT_07_0                       MK_ADDR_CONST(0x152e8)
#define GPIO_C_INPUT_07_0_SECURE                        0x0
#define GPIO_C_INPUT_07_0_DUAL                  0x0
#define GPIO_C_INPUT_07_0_SCR                   GPIO_C_SCR_07_0
#define GPIO_C_INPUT_07_0_SCRREG                        GPIO_C_SCR_07_0
#define GPIO_C_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_C_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_C_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_C_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_C_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_C_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_C_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_C_OUTPUT_CONTROL_07_0
#define GPIO_C_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x152ec)
#define GPIO_C_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_C_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_C_OUTPUT_CONTROL_07_0_SCR                  GPIO_C_SCR_07_0
#define GPIO_C_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_C_SCR_07_0
#define GPIO_C_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_C_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_C_OUTPUT_VALUE_07_0
#define GPIO_C_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x152f0)
#define GPIO_C_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_C_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_C_OUTPUT_VALUE_07_0_SCR                    GPIO_C_SCR_07_0
#define GPIO_C_OUTPUT_VALUE_07_0_SCRREG                         GPIO_C_SCR_07_0
#define GPIO_C_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_C_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_CLEAR_07_0
#define GPIO_C_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x152f4)
#define GPIO_C_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_C_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_C_INTERRUPT_CLEAR_07_0_SCR                         GPIO_C_SCR_07_0
#define GPIO_C_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_C_SCR_07_0
#define GPIO_C_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_C_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x152f8

// Reserved address 0x152fc

// Register GPIO_C_INTERRUPT_STATUS_G0_0
#define GPIO_C_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15300)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_C_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G1_0
#define GPIO_C_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15304)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_C_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G2_0
#define GPIO_C_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15308)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_C_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G3_0
#define GPIO_C_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1530c)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_C_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G4_0
#define GPIO_C_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15310)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_C_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G5_0
#define GPIO_C_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15314)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_C_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G6_0
#define GPIO_C_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15318)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_C_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_C_INTERRUPT_STATUS_G7_0
#define GPIO_C_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1531c)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_C_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_C_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_C_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_C_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_C_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x15320

// Reserved address 0x15324

// Reserved address 0x15328

// Reserved address 0x1532c

// Reserved address 0x15330

// Reserved address 0x15334

// Reserved address 0x15338

// Reserved address 0x1533c

// Reserved address 0x15340

// Reserved address 0x15344

// Reserved address 0x15348

// Reserved address 0x1534c

// Reserved address 0x15350

// Reserved address 0x15354

// Reserved address 0x15358

// Reserved address 0x1535c

// Reserved address 0x15360

// Reserved address 0x15364

// Reserved address 0x15368

// Reserved address 0x1536c

// Reserved address 0x15370

// Reserved address 0x15374

// Reserved address 0x15378

// Reserved address 0x1537c

// Reserved address 0x15380

// Reserved address 0x15384

// Reserved address 0x15388

// Reserved address 0x1538c

// Reserved address 0x15390

// Reserved address 0x15394

// Reserved address 0x15398

// Reserved address 0x1539c

// Reserved address 0x153a0

// Reserved address 0x153a4

// Reserved address 0x153a8

// Reserved address 0x153ac

// Reserved address 0x153b0

// Reserved address 0x153b4

// Reserved address 0x153b8

// Reserved address 0x153bc

// Reserved address 0x153c0

// Reserved address 0x153c4

// Reserved address 0x153c8

// Reserved address 0x153cc

// Reserved address 0x153d0

// Reserved address 0x153d4

// Reserved address 0x153d8

// Reserved address 0x153dc

// Reserved address 0x153e0

// Reserved address 0x153e4

// Reserved address 0x153e8

// Reserved address 0x153ec

// Reserved address 0x153f0

// Reserved address 0x153f4

// Reserved address 0x153f8

// Reserved address 0x153fc

// Register GPIO_D_ENABLE_CONFIG_00_0
#define GPIO_D_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15400)
#define GPIO_D_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_D_ENABLE_CONFIG_00_0_SCR                   GPIO_D_SCR_00_0
#define GPIO_D_ENABLE_CONFIG_00_0_SCRREG                        GPIO_D_SCR_00_0
#define GPIO_D_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_00_0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15404)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_D_SCR_00_0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_D_SCR_00_0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_D_INPUT_00_0
#define GPIO_D_INPUT_00_0                       MK_ADDR_CONST(0x15408)
#define GPIO_D_INPUT_00_0_SECURE                        0x0
#define GPIO_D_INPUT_00_0_DUAL                  0x0
#define GPIO_D_INPUT_00_0_SCR                   GPIO_D_SCR_00_0
#define GPIO_D_INPUT_00_0_SCRREG                        GPIO_D_SCR_00_0
#define GPIO_D_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_D_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_D_OUTPUT_CONTROL_00_0
#define GPIO_D_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1540c)
#define GPIO_D_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_D_OUTPUT_CONTROL_00_0_SCR                  GPIO_D_SCR_00_0
#define GPIO_D_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_D_SCR_00_0
#define GPIO_D_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_00_0
#define GPIO_D_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15410)
#define GPIO_D_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_D_OUTPUT_VALUE_00_0_SCR                    GPIO_D_SCR_00_0
#define GPIO_D_OUTPUT_VALUE_00_0_SCRREG                         GPIO_D_SCR_00_0
#define GPIO_D_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_CLEAR_00_0
#define GPIO_D_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15414)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_D_INTERRUPT_CLEAR_00_0_SCR                         GPIO_D_SCR_00_0
#define GPIO_D_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_D_SCR_00_0
#define GPIO_D_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15418

// Reserved address 0x1541c

// Register GPIO_D_ENABLE_CONFIG_01_0
#define GPIO_D_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15420)
#define GPIO_D_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_D_ENABLE_CONFIG_01_0_SCR                   GPIO_D_SCR_01_0
#define GPIO_D_ENABLE_CONFIG_01_0_SCRREG                        GPIO_D_SCR_01_0
#define GPIO_D_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_01_0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15424)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_D_SCR_01_0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_D_SCR_01_0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_D_INPUT_01_0
#define GPIO_D_INPUT_01_0                       MK_ADDR_CONST(0x15428)
#define GPIO_D_INPUT_01_0_SECURE                        0x0
#define GPIO_D_INPUT_01_0_DUAL                  0x0
#define GPIO_D_INPUT_01_0_SCR                   GPIO_D_SCR_01_0
#define GPIO_D_INPUT_01_0_SCRREG                        GPIO_D_SCR_01_0
#define GPIO_D_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_D_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_D_OUTPUT_CONTROL_01_0
#define GPIO_D_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1542c)
#define GPIO_D_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_D_OUTPUT_CONTROL_01_0_SCR                  GPIO_D_SCR_01_0
#define GPIO_D_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_D_SCR_01_0
#define GPIO_D_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_01_0
#define GPIO_D_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15430)
#define GPIO_D_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_D_OUTPUT_VALUE_01_0_SCR                    GPIO_D_SCR_01_0
#define GPIO_D_OUTPUT_VALUE_01_0_SCRREG                         GPIO_D_SCR_01_0
#define GPIO_D_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_CLEAR_01_0
#define GPIO_D_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15434)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_D_INTERRUPT_CLEAR_01_0_SCR                         GPIO_D_SCR_01_0
#define GPIO_D_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_D_SCR_01_0
#define GPIO_D_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15438

// Reserved address 0x1543c

// Register GPIO_D_ENABLE_CONFIG_02_0
#define GPIO_D_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15440)
#define GPIO_D_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_D_ENABLE_CONFIG_02_0_SCR                   GPIO_D_SCR_02_0
#define GPIO_D_ENABLE_CONFIG_02_0_SCRREG                        GPIO_D_SCR_02_0
#define GPIO_D_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_02_0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15444)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_D_SCR_02_0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_D_SCR_02_0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_D_INPUT_02_0
#define GPIO_D_INPUT_02_0                       MK_ADDR_CONST(0x15448)
#define GPIO_D_INPUT_02_0_SECURE                        0x0
#define GPIO_D_INPUT_02_0_DUAL                  0x0
#define GPIO_D_INPUT_02_0_SCR                   GPIO_D_SCR_02_0
#define GPIO_D_INPUT_02_0_SCRREG                        GPIO_D_SCR_02_0
#define GPIO_D_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_D_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_D_OUTPUT_CONTROL_02_0
#define GPIO_D_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1544c)
#define GPIO_D_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_D_OUTPUT_CONTROL_02_0_SCR                  GPIO_D_SCR_02_0
#define GPIO_D_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_D_SCR_02_0
#define GPIO_D_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_02_0
#define GPIO_D_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15450)
#define GPIO_D_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_D_OUTPUT_VALUE_02_0_SCR                    GPIO_D_SCR_02_0
#define GPIO_D_OUTPUT_VALUE_02_0_SCRREG                         GPIO_D_SCR_02_0
#define GPIO_D_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_CLEAR_02_0
#define GPIO_D_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15454)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_D_INTERRUPT_CLEAR_02_0_SCR                         GPIO_D_SCR_02_0
#define GPIO_D_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_D_SCR_02_0
#define GPIO_D_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15458

// Reserved address 0x1545c

// Register GPIO_D_ENABLE_CONFIG_03_0
#define GPIO_D_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15460)
#define GPIO_D_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_D_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_D_ENABLE_CONFIG_03_0_SCR                   GPIO_D_SCR_03_0
#define GPIO_D_ENABLE_CONFIG_03_0_SCRREG                        GPIO_D_SCR_03_0
#define GPIO_D_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_D_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_D_DEBOUNCE_THRESHOLD_03_0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15464)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_D_SCR_03_0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_D_SCR_03_0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_D_INPUT_03_0
#define GPIO_D_INPUT_03_0                       MK_ADDR_CONST(0x15468)
#define GPIO_D_INPUT_03_0_SECURE                        0x0
#define GPIO_D_INPUT_03_0_DUAL                  0x0
#define GPIO_D_INPUT_03_0_SCR                   GPIO_D_SCR_03_0
#define GPIO_D_INPUT_03_0_SCRREG                        GPIO_D_SCR_03_0
#define GPIO_D_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_D_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_D_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_D_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_D_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_D_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_D_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_D_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_D_OUTPUT_CONTROL_03_0
#define GPIO_D_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1546c)
#define GPIO_D_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_D_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_D_OUTPUT_CONTROL_03_0_SCR                  GPIO_D_SCR_03_0
#define GPIO_D_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_D_SCR_03_0
#define GPIO_D_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_D_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_D_OUTPUT_VALUE_03_0
#define GPIO_D_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15470)
#define GPIO_D_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_D_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_D_OUTPUT_VALUE_03_0_SCR                    GPIO_D_SCR_03_0
#define GPIO_D_OUTPUT_VALUE_03_0_SCRREG                         GPIO_D_SCR_03_0
#define GPIO_D_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_D_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_CLEAR_03_0
#define GPIO_D_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15474)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_D_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_D_INTERRUPT_CLEAR_03_0_SCR                         GPIO_D_SCR_03_0
#define GPIO_D_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_D_SCR_03_0
#define GPIO_D_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_D_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15478

// Reserved address 0x1547c

// Reserved address 0x15480

// Reserved address 0x15484

// Reserved address 0x15488

// Reserved address 0x1548c

// Reserved address 0x15490

// Reserved address 0x15494

// Reserved address 0x15498

// Reserved address 0x1549c

// Reserved address 0x154a0

// Reserved address 0x154a4

// Reserved address 0x154a8

// Reserved address 0x154ac

// Reserved address 0x154b0

// Reserved address 0x154b4

// Reserved address 0x154b8

// Reserved address 0x154bc

// Reserved address 0x154c0

// Reserved address 0x154c4

// Reserved address 0x154c8

// Reserved address 0x154cc

// Reserved address 0x154d0

// Reserved address 0x154d4

// Reserved address 0x154d8

// Reserved address 0x154dc

// Reserved address 0x154e0

// Reserved address 0x154e4

// Reserved address 0x154e8

// Reserved address 0x154ec

// Reserved address 0x154f0

// Reserved address 0x154f4

// Reserved address 0x154f8

// Reserved address 0x154fc

// Register GPIO_D_INTERRUPT_STATUS_G0_0
#define GPIO_D_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15500)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_D_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G1_0
#define GPIO_D_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15504)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_D_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G2_0
#define GPIO_D_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15508)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_D_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G3_0
#define GPIO_D_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1550c)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_D_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G4_0
#define GPIO_D_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15510)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_D_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G5_0
#define GPIO_D_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15514)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_D_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G6_0
#define GPIO_D_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15518)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_D_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_D_INTERRUPT_STATUS_G7_0
#define GPIO_D_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1551c)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_D_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_D_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_D_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_D_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_D_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x15520

// Reserved address 0x15524

// Reserved address 0x15528

// Reserved address 0x1552c

// Reserved address 0x15530

// Reserved address 0x15534

// Reserved address 0x15538

// Reserved address 0x1553c

// Reserved address 0x15540

// Reserved address 0x15544

// Reserved address 0x15548

// Reserved address 0x1554c

// Reserved address 0x15550

// Reserved address 0x15554

// Reserved address 0x15558

// Reserved address 0x1555c

// Reserved address 0x15560

// Reserved address 0x15564

// Reserved address 0x15568

// Reserved address 0x1556c

// Reserved address 0x15570

// Reserved address 0x15574

// Reserved address 0x15578

// Reserved address 0x1557c

// Reserved address 0x15580

// Reserved address 0x15584

// Reserved address 0x15588

// Reserved address 0x1558c

// Reserved address 0x15590

// Reserved address 0x15594

// Reserved address 0x15598

// Reserved address 0x1559c

// Reserved address 0x155a0

// Reserved address 0x155a4

// Reserved address 0x155a8

// Reserved address 0x155ac

// Reserved address 0x155b0

// Reserved address 0x155b4

// Reserved address 0x155b8

// Reserved address 0x155bc

// Reserved address 0x155c0

// Reserved address 0x155c4

// Reserved address 0x155c8

// Reserved address 0x155cc

// Reserved address 0x155d0

// Reserved address 0x155d4

// Reserved address 0x155d8

// Reserved address 0x155dc

// Reserved address 0x155e0

// Reserved address 0x155e4

// Reserved address 0x155e8

// Reserved address 0x155ec

// Reserved address 0x155f0

// Reserved address 0x155f4

// Reserved address 0x155f8

// Reserved address 0x155fc

// Register GPIO_E_ENABLE_CONFIG_00_0
#define GPIO_E_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15600)
#define GPIO_E_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_00_0_SCR                   GPIO_E_SCR_00_0
#define GPIO_E_ENABLE_CONFIG_00_0_SCRREG                        GPIO_E_SCR_00_0
#define GPIO_E_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_00_0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15604)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_E_SCR_00_0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_E_SCR_00_0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_00_0
#define GPIO_E_INPUT_00_0                       MK_ADDR_CONST(0x15608)
#define GPIO_E_INPUT_00_0_SECURE                        0x0
#define GPIO_E_INPUT_00_0_DUAL                  0x0
#define GPIO_E_INPUT_00_0_SCR                   GPIO_E_SCR_00_0
#define GPIO_E_INPUT_00_0_SCRREG                        GPIO_E_SCR_00_0
#define GPIO_E_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_00_0
#define GPIO_E_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1560c)
#define GPIO_E_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_00_0_SCR                  GPIO_E_SCR_00_0
#define GPIO_E_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_E_SCR_00_0
#define GPIO_E_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_00_0
#define GPIO_E_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15610)
#define GPIO_E_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_00_0_SCR                    GPIO_E_SCR_00_0
#define GPIO_E_OUTPUT_VALUE_00_0_SCRREG                         GPIO_E_SCR_00_0
#define GPIO_E_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_00_0
#define GPIO_E_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15614)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_00_0_SCR                         GPIO_E_SCR_00_0
#define GPIO_E_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_E_SCR_00_0
#define GPIO_E_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15618

// Reserved address 0x1561c

// Register GPIO_E_ENABLE_CONFIG_01_0
#define GPIO_E_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15620)
#define GPIO_E_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_01_0_SCR                   GPIO_E_SCR_01_0
#define GPIO_E_ENABLE_CONFIG_01_0_SCRREG                        GPIO_E_SCR_01_0
#define GPIO_E_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_01_0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15624)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_E_SCR_01_0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_E_SCR_01_0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_01_0
#define GPIO_E_INPUT_01_0                       MK_ADDR_CONST(0x15628)
#define GPIO_E_INPUT_01_0_SECURE                        0x0
#define GPIO_E_INPUT_01_0_DUAL                  0x0
#define GPIO_E_INPUT_01_0_SCR                   GPIO_E_SCR_01_0
#define GPIO_E_INPUT_01_0_SCRREG                        GPIO_E_SCR_01_0
#define GPIO_E_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_01_0
#define GPIO_E_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1562c)
#define GPIO_E_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_01_0_SCR                  GPIO_E_SCR_01_0
#define GPIO_E_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_E_SCR_01_0
#define GPIO_E_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_01_0
#define GPIO_E_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15630)
#define GPIO_E_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_01_0_SCR                    GPIO_E_SCR_01_0
#define GPIO_E_OUTPUT_VALUE_01_0_SCRREG                         GPIO_E_SCR_01_0
#define GPIO_E_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_01_0
#define GPIO_E_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15634)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_01_0_SCR                         GPIO_E_SCR_01_0
#define GPIO_E_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_E_SCR_01_0
#define GPIO_E_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15638

// Reserved address 0x1563c

// Register GPIO_E_ENABLE_CONFIG_02_0
#define GPIO_E_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15640)
#define GPIO_E_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_02_0_SCR                   GPIO_E_SCR_02_0
#define GPIO_E_ENABLE_CONFIG_02_0_SCRREG                        GPIO_E_SCR_02_0
#define GPIO_E_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_02_0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15644)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_E_SCR_02_0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_E_SCR_02_0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_02_0
#define GPIO_E_INPUT_02_0                       MK_ADDR_CONST(0x15648)
#define GPIO_E_INPUT_02_0_SECURE                        0x0
#define GPIO_E_INPUT_02_0_DUAL                  0x0
#define GPIO_E_INPUT_02_0_SCR                   GPIO_E_SCR_02_0
#define GPIO_E_INPUT_02_0_SCRREG                        GPIO_E_SCR_02_0
#define GPIO_E_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_02_0
#define GPIO_E_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1564c)
#define GPIO_E_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_02_0_SCR                  GPIO_E_SCR_02_0
#define GPIO_E_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_E_SCR_02_0
#define GPIO_E_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_02_0
#define GPIO_E_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15650)
#define GPIO_E_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_02_0_SCR                    GPIO_E_SCR_02_0
#define GPIO_E_OUTPUT_VALUE_02_0_SCRREG                         GPIO_E_SCR_02_0
#define GPIO_E_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_02_0
#define GPIO_E_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15654)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_02_0_SCR                         GPIO_E_SCR_02_0
#define GPIO_E_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_E_SCR_02_0
#define GPIO_E_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15658

// Reserved address 0x1565c

// Register GPIO_E_ENABLE_CONFIG_03_0
#define GPIO_E_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15660)
#define GPIO_E_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_03_0_SCR                   GPIO_E_SCR_03_0
#define GPIO_E_ENABLE_CONFIG_03_0_SCRREG                        GPIO_E_SCR_03_0
#define GPIO_E_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_03_0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15664)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_E_SCR_03_0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_E_SCR_03_0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_03_0
#define GPIO_E_INPUT_03_0                       MK_ADDR_CONST(0x15668)
#define GPIO_E_INPUT_03_0_SECURE                        0x0
#define GPIO_E_INPUT_03_0_DUAL                  0x0
#define GPIO_E_INPUT_03_0_SCR                   GPIO_E_SCR_03_0
#define GPIO_E_INPUT_03_0_SCRREG                        GPIO_E_SCR_03_0
#define GPIO_E_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_03_0
#define GPIO_E_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1566c)
#define GPIO_E_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_03_0_SCR                  GPIO_E_SCR_03_0
#define GPIO_E_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_E_SCR_03_0
#define GPIO_E_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_03_0
#define GPIO_E_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15670)
#define GPIO_E_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_03_0_SCR                    GPIO_E_SCR_03_0
#define GPIO_E_OUTPUT_VALUE_03_0_SCRREG                         GPIO_E_SCR_03_0
#define GPIO_E_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_03_0
#define GPIO_E_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15674)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_03_0_SCR                         GPIO_E_SCR_03_0
#define GPIO_E_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_E_SCR_03_0
#define GPIO_E_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15678

// Reserved address 0x1567c

// Register GPIO_E_ENABLE_CONFIG_04_0
#define GPIO_E_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x15680)
#define GPIO_E_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_04_0_SCR                   GPIO_E_SCR_04_0
#define GPIO_E_ENABLE_CONFIG_04_0_SCRREG                        GPIO_E_SCR_04_0
#define GPIO_E_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_04_0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x15684)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_E_SCR_04_0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_E_SCR_04_0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_04_0
#define GPIO_E_INPUT_04_0                       MK_ADDR_CONST(0x15688)
#define GPIO_E_INPUT_04_0_SECURE                        0x0
#define GPIO_E_INPUT_04_0_DUAL                  0x0
#define GPIO_E_INPUT_04_0_SCR                   GPIO_E_SCR_04_0
#define GPIO_E_INPUT_04_0_SCRREG                        GPIO_E_SCR_04_0
#define GPIO_E_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_04_0
#define GPIO_E_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1568c)
#define GPIO_E_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_04_0_SCR                  GPIO_E_SCR_04_0
#define GPIO_E_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_E_SCR_04_0
#define GPIO_E_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_04_0
#define GPIO_E_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x15690)
#define GPIO_E_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_04_0_SCR                    GPIO_E_SCR_04_0
#define GPIO_E_OUTPUT_VALUE_04_0_SCRREG                         GPIO_E_SCR_04_0
#define GPIO_E_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_04_0
#define GPIO_E_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x15694)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_04_0_SCR                         GPIO_E_SCR_04_0
#define GPIO_E_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_E_SCR_04_0
#define GPIO_E_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15698

// Reserved address 0x1569c

// Register GPIO_E_ENABLE_CONFIG_05_0
#define GPIO_E_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x156a0)
#define GPIO_E_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_05_0_SCR                   GPIO_E_SCR_05_0
#define GPIO_E_ENABLE_CONFIG_05_0_SCRREG                        GPIO_E_SCR_05_0
#define GPIO_E_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_05_0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x156a4)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_E_SCR_05_0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_E_SCR_05_0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_05_0
#define GPIO_E_INPUT_05_0                       MK_ADDR_CONST(0x156a8)
#define GPIO_E_INPUT_05_0_SECURE                        0x0
#define GPIO_E_INPUT_05_0_DUAL                  0x0
#define GPIO_E_INPUT_05_0_SCR                   GPIO_E_SCR_05_0
#define GPIO_E_INPUT_05_0_SCRREG                        GPIO_E_SCR_05_0
#define GPIO_E_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_05_0
#define GPIO_E_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x156ac)
#define GPIO_E_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_05_0_SCR                  GPIO_E_SCR_05_0
#define GPIO_E_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_E_SCR_05_0
#define GPIO_E_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_05_0
#define GPIO_E_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x156b0)
#define GPIO_E_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_05_0_SCR                    GPIO_E_SCR_05_0
#define GPIO_E_OUTPUT_VALUE_05_0_SCRREG                         GPIO_E_SCR_05_0
#define GPIO_E_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_05_0
#define GPIO_E_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x156b4)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_05_0_SCR                         GPIO_E_SCR_05_0
#define GPIO_E_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_E_SCR_05_0
#define GPIO_E_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x156b8

// Reserved address 0x156bc

// Register GPIO_E_ENABLE_CONFIG_06_0
#define GPIO_E_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x156c0)
#define GPIO_E_ENABLE_CONFIG_06_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_06_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_06_0_SCR                   GPIO_E_SCR_06_0
#define GPIO_E_ENABLE_CONFIG_06_0_SCRREG                        GPIO_E_SCR_06_0
#define GPIO_E_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_06_0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x156c4)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_E_SCR_06_0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_E_SCR_06_0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_06_0
#define GPIO_E_INPUT_06_0                       MK_ADDR_CONST(0x156c8)
#define GPIO_E_INPUT_06_0_SECURE                        0x0
#define GPIO_E_INPUT_06_0_DUAL                  0x0
#define GPIO_E_INPUT_06_0_SCR                   GPIO_E_SCR_06_0
#define GPIO_E_INPUT_06_0_SCRREG                        GPIO_E_SCR_06_0
#define GPIO_E_INPUT_06_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_06_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_06_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_06_0
#define GPIO_E_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x156cc)
#define GPIO_E_OUTPUT_CONTROL_06_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_06_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_06_0_SCR                  GPIO_E_SCR_06_0
#define GPIO_E_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_E_SCR_06_0
#define GPIO_E_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_06_0
#define GPIO_E_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x156d0)
#define GPIO_E_OUTPUT_VALUE_06_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_06_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_06_0_SCR                    GPIO_E_SCR_06_0
#define GPIO_E_OUTPUT_VALUE_06_0_SCRREG                         GPIO_E_SCR_06_0
#define GPIO_E_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_06_0
#define GPIO_E_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x156d4)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_06_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_06_0_SCR                         GPIO_E_SCR_06_0
#define GPIO_E_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_E_SCR_06_0
#define GPIO_E_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x156d8

// Reserved address 0x156dc

// Register GPIO_E_ENABLE_CONFIG_07_0
#define GPIO_E_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x156e0)
#define GPIO_E_ENABLE_CONFIG_07_0_SECURE                        0x0
#define GPIO_E_ENABLE_CONFIG_07_0_DUAL                  0x0
#define GPIO_E_ENABLE_CONFIG_07_0_SCR                   GPIO_E_SCR_07_0
#define GPIO_E_ENABLE_CONFIG_07_0_SCRREG                        GPIO_E_SCR_07_0
#define GPIO_E_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
#define GPIO_E_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_E_DEBOUNCE_THRESHOLD_07_0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x156e4)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_E_SCR_07_0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_E_SCR_07_0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_INPUT_07_0
#define GPIO_E_INPUT_07_0                       MK_ADDR_CONST(0x156e8)
#define GPIO_E_INPUT_07_0_SECURE                        0x0
#define GPIO_E_INPUT_07_0_DUAL                  0x0
#define GPIO_E_INPUT_07_0_SCR                   GPIO_E_SCR_07_0
#define GPIO_E_INPUT_07_0_SCRREG                        GPIO_E_SCR_07_0
#define GPIO_E_INPUT_07_0_WORD_COUNT                    0x1
#define GPIO_E_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_07_0_GPIO_IN_SHIFT)
#define GPIO_E_INPUT_07_0_GPIO_IN_RANGE                 0:0
#define GPIO_E_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_E_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_E_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_E_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_E_OUTPUT_CONTROL_07_0
#define GPIO_E_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x156ec)
#define GPIO_E_OUTPUT_CONTROL_07_0_SECURE                       0x0
#define GPIO_E_OUTPUT_CONTROL_07_0_DUAL                         0x0
#define GPIO_E_OUTPUT_CONTROL_07_0_SCR                  GPIO_E_SCR_07_0
#define GPIO_E_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_E_SCR_07_0
#define GPIO_E_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
#define GPIO_E_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_E_OUTPUT_VALUE_07_0
#define GPIO_E_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x156f0)
#define GPIO_E_OUTPUT_VALUE_07_0_SECURE                         0x0
#define GPIO_E_OUTPUT_VALUE_07_0_DUAL                   0x0
#define GPIO_E_OUTPUT_VALUE_07_0_SCR                    GPIO_E_SCR_07_0
#define GPIO_E_OUTPUT_VALUE_07_0_SCRREG                         GPIO_E_SCR_07_0
#define GPIO_E_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
#define GPIO_E_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_CLEAR_07_0
#define GPIO_E_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x156f4)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SECURE                      0x0
#define GPIO_E_INTERRUPT_CLEAR_07_0_DUAL                        0x0
#define GPIO_E_INTERRUPT_CLEAR_07_0_SCR                         GPIO_E_SCR_07_0
#define GPIO_E_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_E_SCR_07_0
#define GPIO_E_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
#define GPIO_E_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x156f8

// Reserved address 0x156fc

// Register GPIO_E_INTERRUPT_STATUS_G0_0
#define GPIO_E_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15700)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_E_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G1_0
#define GPIO_E_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15704)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_E_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G2_0
#define GPIO_E_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15708)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_E_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G3_0
#define GPIO_E_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1570c)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_E_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G4_0
#define GPIO_E_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15710)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_E_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G5_0
#define GPIO_E_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15714)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_E_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G6_0
#define GPIO_E_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15718)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_E_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_E_INTERRUPT_STATUS_G7_0
#define GPIO_E_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1571c)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_E_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_E_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_E_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_E_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_E_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x15720

// Reserved address 0x15724

// Reserved address 0x15728

// Reserved address 0x1572c

// Reserved address 0x15730

// Reserved address 0x15734

// Reserved address 0x15738

// Reserved address 0x1573c

// Reserved address 0x15740

// Reserved address 0x15744

// Reserved address 0x15748

// Reserved address 0x1574c

// Reserved address 0x15750

// Reserved address 0x15754

// Reserved address 0x15758

// Reserved address 0x1575c

// Reserved address 0x15760

// Reserved address 0x15764

// Reserved address 0x15768

// Reserved address 0x1576c

// Reserved address 0x15770

// Reserved address 0x15774

// Reserved address 0x15778

// Reserved address 0x1577c

// Reserved address 0x15780

// Reserved address 0x15784

// Reserved address 0x15788

// Reserved address 0x1578c

// Reserved address 0x15790

// Reserved address 0x15794

// Reserved address 0x15798

// Reserved address 0x1579c

// Reserved address 0x157a0

// Reserved address 0x157a4

// Reserved address 0x157a8

// Reserved address 0x157ac

// Reserved address 0x157b0

// Reserved address 0x157b4

// Reserved address 0x157b8

// Reserved address 0x157bc

// Reserved address 0x157c0

// Reserved address 0x157c4

// Reserved address 0x157c8

// Reserved address 0x157cc

// Reserved address 0x157d0

// Reserved address 0x157d4

// Reserved address 0x157d8

// Reserved address 0x157dc

// Reserved address 0x157e0

// Reserved address 0x157e4

// Reserved address 0x157e8

// Reserved address 0x157ec

// Reserved address 0x157f0

// Reserved address 0x157f4

// Reserved address 0x157f8

// Reserved address 0x157fc

// Register GPIO_F_ENABLE_CONFIG_00_0
#define GPIO_F_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15800)
#define GPIO_F_ENABLE_CONFIG_00_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_00_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_00_0_SCR                   GPIO_F_SCR_00_0
#define GPIO_F_ENABLE_CONFIG_00_0_SCRREG                        GPIO_F_SCR_00_0
#define GPIO_F_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_00_0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15804)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_F_SCR_00_0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_F_SCR_00_0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_00_0
#define GPIO_F_INPUT_00_0                       MK_ADDR_CONST(0x15808)
#define GPIO_F_INPUT_00_0_SECURE                        0x0
#define GPIO_F_INPUT_00_0_DUAL                  0x0
#define GPIO_F_INPUT_00_0_SCR                   GPIO_F_SCR_00_0
#define GPIO_F_INPUT_00_0_SCRREG                        GPIO_F_SCR_00_0
#define GPIO_F_INPUT_00_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_00_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_00_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_00_0
#define GPIO_F_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1580c)
#define GPIO_F_OUTPUT_CONTROL_00_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_00_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_00_0_SCR                  GPIO_F_SCR_00_0
#define GPIO_F_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_F_SCR_00_0
#define GPIO_F_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_00_0
#define GPIO_F_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15810)
#define GPIO_F_OUTPUT_VALUE_00_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_00_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_00_0_SCR                    GPIO_F_SCR_00_0
#define GPIO_F_OUTPUT_VALUE_00_0_SCRREG                         GPIO_F_SCR_00_0
#define GPIO_F_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_00_0
#define GPIO_F_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15814)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_00_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_00_0_SCR                         GPIO_F_SCR_00_0
#define GPIO_F_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_F_SCR_00_0
#define GPIO_F_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15818

// Reserved address 0x1581c

// Register GPIO_F_ENABLE_CONFIG_01_0
#define GPIO_F_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15820)
#define GPIO_F_ENABLE_CONFIG_01_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_01_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_01_0_SCR                   GPIO_F_SCR_01_0
#define GPIO_F_ENABLE_CONFIG_01_0_SCRREG                        GPIO_F_SCR_01_0
#define GPIO_F_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_01_0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15824)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_F_SCR_01_0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_F_SCR_01_0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_01_0
#define GPIO_F_INPUT_01_0                       MK_ADDR_CONST(0x15828)
#define GPIO_F_INPUT_01_0_SECURE                        0x0
#define GPIO_F_INPUT_01_0_DUAL                  0x0
#define GPIO_F_INPUT_01_0_SCR                   GPIO_F_SCR_01_0
#define GPIO_F_INPUT_01_0_SCRREG                        GPIO_F_SCR_01_0
#define GPIO_F_INPUT_01_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_01_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_01_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_01_0
#define GPIO_F_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1582c)
#define GPIO_F_OUTPUT_CONTROL_01_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_01_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_01_0_SCR                  GPIO_F_SCR_01_0
#define GPIO_F_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_F_SCR_01_0
#define GPIO_F_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_01_0
#define GPIO_F_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15830)
#define GPIO_F_OUTPUT_VALUE_01_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_01_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_01_0_SCR                    GPIO_F_SCR_01_0
#define GPIO_F_OUTPUT_VALUE_01_0_SCRREG                         GPIO_F_SCR_01_0
#define GPIO_F_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_01_0
#define GPIO_F_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15834)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_01_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_01_0_SCR                         GPIO_F_SCR_01_0
#define GPIO_F_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_F_SCR_01_0
#define GPIO_F_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15838

// Reserved address 0x1583c

// Register GPIO_F_ENABLE_CONFIG_02_0
#define GPIO_F_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15840)
#define GPIO_F_ENABLE_CONFIG_02_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_02_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_02_0_SCR                   GPIO_F_SCR_02_0
#define GPIO_F_ENABLE_CONFIG_02_0_SCRREG                        GPIO_F_SCR_02_0
#define GPIO_F_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_02_0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15844)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_F_SCR_02_0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_F_SCR_02_0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_02_0
#define GPIO_F_INPUT_02_0                       MK_ADDR_CONST(0x15848)
#define GPIO_F_INPUT_02_0_SECURE                        0x0
#define GPIO_F_INPUT_02_0_DUAL                  0x0
#define GPIO_F_INPUT_02_0_SCR                   GPIO_F_SCR_02_0
#define GPIO_F_INPUT_02_0_SCRREG                        GPIO_F_SCR_02_0
#define GPIO_F_INPUT_02_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_02_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_02_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_02_0
#define GPIO_F_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1584c)
#define GPIO_F_OUTPUT_CONTROL_02_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_02_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_02_0_SCR                  GPIO_F_SCR_02_0
#define GPIO_F_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_F_SCR_02_0
#define GPIO_F_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_02_0
#define GPIO_F_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15850)
#define GPIO_F_OUTPUT_VALUE_02_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_02_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_02_0_SCR                    GPIO_F_SCR_02_0
#define GPIO_F_OUTPUT_VALUE_02_0_SCRREG                         GPIO_F_SCR_02_0
#define GPIO_F_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_02_0
#define GPIO_F_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15854)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_02_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_02_0_SCR                         GPIO_F_SCR_02_0
#define GPIO_F_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_F_SCR_02_0
#define GPIO_F_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15858

// Reserved address 0x1585c

// Register GPIO_F_ENABLE_CONFIG_03_0
#define GPIO_F_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15860)
#define GPIO_F_ENABLE_CONFIG_03_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_03_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_03_0_SCR                   GPIO_F_SCR_03_0
#define GPIO_F_ENABLE_CONFIG_03_0_SCRREG                        GPIO_F_SCR_03_0
#define GPIO_F_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_03_0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15864)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_F_SCR_03_0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_F_SCR_03_0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_03_0
#define GPIO_F_INPUT_03_0                       MK_ADDR_CONST(0x15868)
#define GPIO_F_INPUT_03_0_SECURE                        0x0
#define GPIO_F_INPUT_03_0_DUAL                  0x0
#define GPIO_F_INPUT_03_0_SCR                   GPIO_F_SCR_03_0
#define GPIO_F_INPUT_03_0_SCRREG                        GPIO_F_SCR_03_0
#define GPIO_F_INPUT_03_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_03_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_03_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_03_0
#define GPIO_F_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1586c)
#define GPIO_F_OUTPUT_CONTROL_03_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_03_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_03_0_SCR                  GPIO_F_SCR_03_0
#define GPIO_F_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_F_SCR_03_0
#define GPIO_F_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_03_0
#define GPIO_F_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15870)
#define GPIO_F_OUTPUT_VALUE_03_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_03_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_03_0_SCR                    GPIO_F_SCR_03_0
#define GPIO_F_OUTPUT_VALUE_03_0_SCRREG                         GPIO_F_SCR_03_0
#define GPIO_F_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_03_0
#define GPIO_F_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15874)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_03_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_03_0_SCR                         GPIO_F_SCR_03_0
#define GPIO_F_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_F_SCR_03_0
#define GPIO_F_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15878

// Reserved address 0x1587c

// Register GPIO_F_ENABLE_CONFIG_04_0
#define GPIO_F_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x15880)
#define GPIO_F_ENABLE_CONFIG_04_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_04_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_04_0_SCR                   GPIO_F_SCR_04_0
#define GPIO_F_ENABLE_CONFIG_04_0_SCRREG                        GPIO_F_SCR_04_0
#define GPIO_F_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_04_0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x15884)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_F_SCR_04_0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_F_SCR_04_0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_04_0
#define GPIO_F_INPUT_04_0                       MK_ADDR_CONST(0x15888)
#define GPIO_F_INPUT_04_0_SECURE                        0x0
#define GPIO_F_INPUT_04_0_DUAL                  0x0
#define GPIO_F_INPUT_04_0_SCR                   GPIO_F_SCR_04_0
#define GPIO_F_INPUT_04_0_SCRREG                        GPIO_F_SCR_04_0
#define GPIO_F_INPUT_04_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_04_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_04_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_04_0
#define GPIO_F_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1588c)
#define GPIO_F_OUTPUT_CONTROL_04_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_04_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_04_0_SCR                  GPIO_F_SCR_04_0
#define GPIO_F_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_F_SCR_04_0
#define GPIO_F_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_04_0
#define GPIO_F_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x15890)
#define GPIO_F_OUTPUT_VALUE_04_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_04_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_04_0_SCR                    GPIO_F_SCR_04_0
#define GPIO_F_OUTPUT_VALUE_04_0_SCRREG                         GPIO_F_SCR_04_0
#define GPIO_F_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_04_0
#define GPIO_F_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x15894)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_04_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_04_0_SCR                         GPIO_F_SCR_04_0
#define GPIO_F_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_F_SCR_04_0
#define GPIO_F_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x15898

// Reserved address 0x1589c

// Register GPIO_F_ENABLE_CONFIG_05_0
#define GPIO_F_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x158a0)
#define GPIO_F_ENABLE_CONFIG_05_0_SECURE                        0x0
#define GPIO_F_ENABLE_CONFIG_05_0_DUAL                  0x0
#define GPIO_F_ENABLE_CONFIG_05_0_SCR                   GPIO_F_SCR_05_0
#define GPIO_F_ENABLE_CONFIG_05_0_SCRREG                        GPIO_F_SCR_05_0
#define GPIO_F_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
#define GPIO_F_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)

#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)

#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)


// Register GPIO_F_DEBOUNCE_THRESHOLD_05_0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x158a4)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_F_SCR_05_0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_F_SCR_05_0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_INPUT_05_0
#define GPIO_F_INPUT_05_0                       MK_ADDR_CONST(0x158a8)
#define GPIO_F_INPUT_05_0_SECURE                        0x0
#define GPIO_F_INPUT_05_0_DUAL                  0x0
#define GPIO_F_INPUT_05_0_SCR                   GPIO_F_SCR_05_0
#define GPIO_F_INPUT_05_0_SCRREG                        GPIO_F_SCR_05_0
#define GPIO_F_INPUT_05_0_WORD_COUNT                    0x1
#define GPIO_F_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_05_0_GPIO_IN_SHIFT)
#define GPIO_F_INPUT_05_0_GPIO_IN_RANGE                 0:0
#define GPIO_F_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
#define GPIO_F_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
#define GPIO_F_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
#define GPIO_F_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)


// Register GPIO_F_OUTPUT_CONTROL_05_0
#define GPIO_F_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x158ac)
#define GPIO_F_OUTPUT_CONTROL_05_0_SECURE                       0x0
#define GPIO_F_OUTPUT_CONTROL_05_0_DUAL                         0x0
#define GPIO_F_OUTPUT_CONTROL_05_0_SCR                  GPIO_F_SCR_05_0
#define GPIO_F_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_F_SCR_05_0
#define GPIO_F_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
#define GPIO_F_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)


// Register GPIO_F_OUTPUT_VALUE_05_0
#define GPIO_F_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x158b0)
#define GPIO_F_OUTPUT_VALUE_05_0_SECURE                         0x0
#define GPIO_F_OUTPUT_VALUE_05_0_DUAL                   0x0
#define GPIO_F_OUTPUT_VALUE_05_0_SCR                    GPIO_F_SCR_05_0
#define GPIO_F_OUTPUT_VALUE_05_0_SCRREG                         GPIO_F_SCR_05_0
#define GPIO_F_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
#define GPIO_F_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_CLEAR_05_0
#define GPIO_F_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x158b4)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SECURE                      0x0
#define GPIO_F_INTERRUPT_CLEAR_05_0_DUAL                        0x0
#define GPIO_F_INTERRUPT_CLEAR_05_0_SCR                         GPIO_F_SCR_05_0
#define GPIO_F_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_F_SCR_05_0
#define GPIO_F_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
#define GPIO_F_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)


// Reserved address 0x158b8

// Reserved address 0x158bc

// Reserved address 0x158c0

// Reserved address 0x158c4

// Reserved address 0x158c8

// Reserved address 0x158cc

// Reserved address 0x158d0

// Reserved address 0x158d4

// Reserved address 0x158d8

// Reserved address 0x158dc

// Reserved address 0x158e0

// Reserved address 0x158e4

// Reserved address 0x158e8

// Reserved address 0x158ec

// Reserved address 0x158f0

// Reserved address 0x158f4

// Reserved address 0x158f8

// Reserved address 0x158fc

// Register GPIO_F_INTERRUPT_STATUS_G0_0
#define GPIO_F_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15900)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G0_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G0_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G0_0_SCRREG                     0
#define GPIO_F_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G1_0
#define GPIO_F_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15904)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G1_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G1_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G1_0_SCRREG                     0
#define GPIO_F_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G2_0
#define GPIO_F_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15908)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G2_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G2_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G2_0_SCRREG                     0
#define GPIO_F_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G3_0
#define GPIO_F_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1590c)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G3_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G3_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G3_0_SCRREG                     0
#define GPIO_F_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G4_0
#define GPIO_F_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15910)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G4_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G4_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G4_0_SCRREG                     0
#define GPIO_F_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G5_0
#define GPIO_F_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15914)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G5_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G5_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G5_0_SCRREG                     0
#define GPIO_F_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G6_0
#define GPIO_F_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15918)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G6_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G6_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G6_0_SCRREG                     0
#define GPIO_F_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Register GPIO_F_INTERRUPT_STATUS_G7_0
#define GPIO_F_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1591c)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SECURE                     0x0
#define GPIO_F_INTERRUPT_STATUS_G7_0_DUAL                       0x0
#define GPIO_F_INTERRUPT_STATUS_G7_0_SCR                        0
#define GPIO_F_INTERRUPT_STATUS_G7_0_SCRREG                     0
#define GPIO_F_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
#define GPIO_F_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)


// Reserved address 0x15920

// Reserved address 0x15924

// Reserved address 0x15928

// Reserved address 0x1592c

// Reserved address 0x15930

// Reserved address 0x15934

// Reserved address 0x15938

// Reserved address 0x1593c

// Reserved address 0x15940

// Reserved address 0x15944

// Reserved address 0x15948

// Reserved address 0x1594c

// Reserved address 0x15950

// Reserved address 0x15954

// Reserved address 0x15958

// Reserved address 0x1595c

// Reserved address 0x15960

// Reserved address 0x15964

// Reserved address 0x15968

// Reserved address 0x1596c

// Reserved address 0x15970

// Reserved address 0x15974

// Reserved address 0x15978

// Reserved address 0x1597c

// Reserved address 0x15980

// Reserved address 0x15984

// Reserved address 0x15988

// Reserved address 0x1598c

// Reserved address 0x15990

// Reserved address 0x15994

// Reserved address 0x15998

// Reserved address 0x1599c

// Reserved address 0x159a0

// Reserved address 0x159a4

// Reserved address 0x159a8

// Reserved address 0x159ac

// Reserved address 0x159b0

// Reserved address 0x159b4

// Reserved address 0x159b8

// Reserved address 0x159bc

// Reserved address 0x159c0

// Reserved address 0x159c4

// Reserved address 0x159c8

// Reserved address 0x159cc

// Reserved address 0x159d0

// Reserved address 0x159d4

// Reserved address 0x159d8

// Reserved address 0x159dc

// Reserved address 0x159e0

// Reserved address 0x159e4

// Reserved address 0x159e8

// Reserved address 0x159ec

// Reserved address 0x159f0

// Reserved address 0x159f4

// Reserved address 0x159f8

// Reserved address 0x159fc

//
// REGISTER LIST
//
#define LIST_ARGPIO_REGS(_op_) \
_op_(GPIO_A_VM_00_0) \
_op_(GPIO_A_SCR_00_0) \
_op_(GPIO_A_VM_01_0) \
_op_(GPIO_A_SCR_01_0) \
_op_(GPIO_A_VM_02_0) \
_op_(GPIO_A_SCR_02_0) \
_op_(GPIO_A_VM_03_0) \
_op_(GPIO_A_SCR_03_0) \
_op_(GPIO_A_VM_04_0) \
_op_(GPIO_A_SCR_04_0) \
_op_(GPIO_A_VM_05_0) \
_op_(GPIO_A_SCR_05_0) \
_op_(GPIO_A_VM_06_0) \
_op_(GPIO_A_SCR_06_0) \
_op_(GPIO_A_VM_07_0) \
_op_(GPIO_A_SCR_07_0) \
_op_(GPIO_AC_VM_00_0) \
_op_(GPIO_AC_SCR_00_0) \
_op_(GPIO_AC_VM_01_0) \
_op_(GPIO_AC_SCR_01_0) \
_op_(GPIO_AC_VM_02_0) \
_op_(GPIO_AC_SCR_02_0) \
_op_(GPIO_AC_VM_03_0) \
_op_(GPIO_AC_SCR_03_0) \
_op_(GPIO_AC_VM_04_0) \
_op_(GPIO_AC_SCR_04_0) \
_op_(GPIO_AC_VM_05_0) \
_op_(GPIO_AC_SCR_05_0) \
_op_(GPIO_AC_VM_06_0) \
_op_(GPIO_AC_SCR_06_0) \
_op_(GPIO_AC_VM_07_0) \
_op_(GPIO_AC_SCR_07_0) \
_op_(GPIO_AD_VM_00_0) \
_op_(GPIO_AD_SCR_00_0) \
_op_(GPIO_AD_VM_01_0) \
_op_(GPIO_AD_SCR_01_0) \
_op_(GPIO_AD_VM_02_0) \
_op_(GPIO_AD_SCR_02_0) \
_op_(GPIO_AD_VM_03_0) \
_op_(GPIO_AD_SCR_03_0) \
_op_(GPIO_B_VM_00_0) \
_op_(GPIO_B_SCR_00_0) \
_op_(GPIO_CTL0_VM_SCR_0) \
_op_(GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL0_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL0_SCR_0) \
_op_(GPIO_CTL0_ICG_EN_OVERRIDE_0) \
_op_(GPIO_A_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_A_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_AC_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_AC_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_AC_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_AC_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_AC_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_AC_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_AC_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_AC_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_AD_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_AD_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_AD_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_AD_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_AD_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_AD_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_AD_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_AD_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_B_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL0_SPARE_0) \
_op_(GPIO_X_VM_00_0) \
_op_(GPIO_X_SCR_00_0) \
_op_(GPIO_X_VM_01_0) \
_op_(GPIO_X_SCR_01_0) \
_op_(GPIO_X_VM_02_0) \
_op_(GPIO_X_SCR_02_0) \
_op_(GPIO_X_VM_03_0) \
_op_(GPIO_X_SCR_03_0) \
_op_(GPIO_X_VM_04_0) \
_op_(GPIO_X_SCR_04_0) \
_op_(GPIO_X_VM_05_0) \
_op_(GPIO_X_SCR_05_0) \
_op_(GPIO_X_VM_06_0) \
_op_(GPIO_X_SCR_06_0) \
_op_(GPIO_X_VM_07_0) \
_op_(GPIO_X_SCR_07_0) \
_op_(GPIO_Y_VM_00_0) \
_op_(GPIO_Y_SCR_00_0) \
_op_(GPIO_Y_VM_01_0) \
_op_(GPIO_Y_SCR_01_0) \
_op_(GPIO_Y_VM_02_0) \
_op_(GPIO_Y_SCR_02_0) \
_op_(GPIO_Y_VM_03_0) \
_op_(GPIO_Y_SCR_03_0) \
_op_(GPIO_Y_VM_04_0) \
_op_(GPIO_Y_SCR_04_0) \
_op_(GPIO_Y_VM_05_0) \
_op_(GPIO_Y_SCR_05_0) \
_op_(GPIO_Y_VM_06_0) \
_op_(GPIO_Y_SCR_06_0) \
_op_(GPIO_Y_VM_07_0) \
_op_(GPIO_Y_SCR_07_0) \
_op_(GPIO_Z_VM_00_0) \
_op_(GPIO_Z_SCR_00_0) \
_op_(GPIO_Z_VM_01_0) \
_op_(GPIO_Z_SCR_01_0) \
_op_(GPIO_Z_VM_02_0) \
_op_(GPIO_Z_SCR_02_0) \
_op_(GPIO_Z_VM_03_0) \
_op_(GPIO_Z_SCR_03_0) \
_op_(GPIO_Z_VM_04_0) \
_op_(GPIO_Z_SCR_04_0) \
_op_(GPIO_Z_VM_05_0) \
_op_(GPIO_Z_SCR_05_0) \
_op_(GPIO_Z_VM_06_0) \
_op_(GPIO_Z_SCR_06_0) \
_op_(GPIO_Z_VM_07_0) \
_op_(GPIO_Z_SCR_07_0) \
_op_(GPIO_CTL1_VM_SCR_0) \
_op_(GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL1_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL1_SCR_0) \
_op_(GPIO_CTL1_ICG_EN_OVERRIDE_0) \
_op_(GPIO_X_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_X_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_Y_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_Z_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL1_SPARE_0) \
_op_(GPIO_M_VM_00_0) \
_op_(GPIO_M_SCR_00_0) \
_op_(GPIO_M_VM_01_0) \
_op_(GPIO_M_SCR_01_0) \
_op_(GPIO_M_VM_02_0) \
_op_(GPIO_M_SCR_02_0) \
_op_(GPIO_M_VM_03_0) \
_op_(GPIO_M_SCR_03_0) \
_op_(GPIO_M_VM_04_0) \
_op_(GPIO_M_SCR_04_0) \
_op_(GPIO_M_VM_05_0) \
_op_(GPIO_M_SCR_05_0) \
_op_(GPIO_M_VM_06_0) \
_op_(GPIO_M_SCR_06_0) \
_op_(GPIO_M_VM_07_0) \
_op_(GPIO_M_SCR_07_0) \
_op_(GPIO_N_VM_00_0) \
_op_(GPIO_N_SCR_00_0) \
_op_(GPIO_N_VM_01_0) \
_op_(GPIO_N_SCR_01_0) \
_op_(GPIO_N_VM_02_0) \
_op_(GPIO_N_SCR_02_0) \
_op_(GPIO_N_VM_03_0) \
_op_(GPIO_N_SCR_03_0) \
_op_(GPIO_N_VM_04_0) \
_op_(GPIO_N_SCR_04_0) \
_op_(GPIO_N_VM_05_0) \
_op_(GPIO_N_SCR_05_0) \
_op_(GPIO_N_VM_06_0) \
_op_(GPIO_N_SCR_06_0) \
_op_(GPIO_N_VM_07_0) \
_op_(GPIO_N_SCR_07_0) \
_op_(GPIO_P_VM_00_0) \
_op_(GPIO_P_SCR_00_0) \
_op_(GPIO_P_VM_01_0) \
_op_(GPIO_P_SCR_01_0) \
_op_(GPIO_P_VM_02_0) \
_op_(GPIO_P_SCR_02_0) \
_op_(GPIO_P_VM_03_0) \
_op_(GPIO_P_SCR_03_0) \
_op_(GPIO_P_VM_04_0) \
_op_(GPIO_P_SCR_04_0) \
_op_(GPIO_P_VM_05_0) \
_op_(GPIO_P_SCR_05_0) \
_op_(GPIO_P_VM_06_0) \
_op_(GPIO_P_SCR_06_0) \
_op_(GPIO_P_VM_07_0) \
_op_(GPIO_P_SCR_07_0) \
_op_(GPIO_Q_VM_00_0) \
_op_(GPIO_Q_SCR_00_0) \
_op_(GPIO_Q_VM_01_0) \
_op_(GPIO_Q_SCR_01_0) \
_op_(GPIO_Q_VM_02_0) \
_op_(GPIO_Q_SCR_02_0) \
_op_(GPIO_Q_VM_03_0) \
_op_(GPIO_Q_SCR_03_0) \
_op_(GPIO_Q_VM_04_0) \
_op_(GPIO_Q_SCR_04_0) \
_op_(GPIO_Q_VM_05_0) \
_op_(GPIO_Q_SCR_05_0) \
_op_(GPIO_Q_VM_06_0) \
_op_(GPIO_Q_SCR_06_0) \
_op_(GPIO_Q_VM_07_0) \
_op_(GPIO_Q_SCR_07_0) \
_op_(GPIO_R_VM_00_0) \
_op_(GPIO_R_SCR_00_0) \
_op_(GPIO_R_VM_01_0) \
_op_(GPIO_R_SCR_01_0) \
_op_(GPIO_R_VM_02_0) \
_op_(GPIO_R_SCR_02_0) \
_op_(GPIO_R_VM_03_0) \
_op_(GPIO_R_SCR_03_0) \
_op_(GPIO_R_VM_04_0) \
_op_(GPIO_R_SCR_04_0) \
_op_(GPIO_R_VM_05_0) \
_op_(GPIO_R_SCR_05_0) \
_op_(GPIO_CTL2_VM_SCR_0) \
_op_(GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL2_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL2_SCR_0) \
_op_(GPIO_CTL2_ICG_EN_OVERRIDE_0) \
_op_(GPIO_M_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_M_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_N_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_P_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_Q_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_R_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL2_SPARE_0) \
_op_(GPIO_K_VM_00_0) \
_op_(GPIO_K_SCR_00_0) \
_op_(GPIO_K_VM_01_0) \
_op_(GPIO_K_SCR_01_0) \
_op_(GPIO_K_VM_02_0) \
_op_(GPIO_K_SCR_02_0) \
_op_(GPIO_K_VM_03_0) \
_op_(GPIO_K_SCR_03_0) \
_op_(GPIO_K_VM_04_0) \
_op_(GPIO_K_SCR_04_0) \
_op_(GPIO_K_VM_05_0) \
_op_(GPIO_K_SCR_05_0) \
_op_(GPIO_K_VM_06_0) \
_op_(GPIO_K_SCR_06_0) \
_op_(GPIO_K_VM_07_0) \
_op_(GPIO_K_SCR_07_0) \
_op_(GPIO_L_VM_00_0) \
_op_(GPIO_L_SCR_00_0) \
_op_(GPIO_L_VM_01_0) \
_op_(GPIO_L_SCR_01_0) \
_op_(GPIO_L_VM_02_0) \
_op_(GPIO_L_SCR_02_0) \
_op_(GPIO_L_VM_03_0) \
_op_(GPIO_L_SCR_03_0) \
_op_(GPIO_AG_VM_00_0) \
_op_(GPIO_AG_SCR_00_0) \
_op_(GPIO_AG_VM_01_0) \
_op_(GPIO_AG_SCR_01_0) \
_op_(GPIO_AG_VM_02_0) \
_op_(GPIO_AG_SCR_02_0) \
_op_(GPIO_AG_VM_03_0) \
_op_(GPIO_AG_SCR_03_0) \
_op_(GPIO_AG_VM_04_0) \
_op_(GPIO_AG_SCR_04_0) \
_op_(GPIO_AG_VM_05_0) \
_op_(GPIO_AG_SCR_05_0) \
_op_(GPIO_AG_VM_06_0) \
_op_(GPIO_AG_SCR_06_0) \
_op_(GPIO_AG_VM_07_0) \
_op_(GPIO_AG_SCR_07_0) \
_op_(GPIO_AE_VM_00_0) \
_op_(GPIO_AE_SCR_00_0) \
_op_(GPIO_AE_VM_01_0) \
_op_(GPIO_AE_SCR_01_0) \
_op_(GPIO_AF_VM_00_0) \
_op_(GPIO_AF_SCR_00_0) \
_op_(GPIO_AF_VM_01_0) \
_op_(GPIO_AF_SCR_01_0) \
_op_(GPIO_AF_VM_02_0) \
_op_(GPIO_AF_SCR_02_0) \
_op_(GPIO_AF_VM_03_0) \
_op_(GPIO_AF_SCR_03_0) \
_op_(GPIO_CTL3_VM_SCR_0) \
_op_(GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL3_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL3_SCR_0) \
_op_(GPIO_CTL3_ICG_EN_OVERRIDE_0) \
_op_(GPIO_K_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_K_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_L_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_AG_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_AG_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_AG_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_AG_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_AG_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_AG_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_AG_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_AG_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_AE_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_AE_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_AE_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_AE_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_AE_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_AE_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_AE_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_AE_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_AF_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_AF_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_AF_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_AF_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_AF_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_AF_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_AF_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_AF_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL3_SPARE_0) \
_op_(GPIO_G_VM_00_0) \
_op_(GPIO_G_SCR_00_0) \
_op_(GPIO_G_VM_01_0) \
_op_(GPIO_G_SCR_01_0) \
_op_(GPIO_G_VM_02_0) \
_op_(GPIO_G_SCR_02_0) \
_op_(GPIO_G_VM_03_0) \
_op_(GPIO_G_SCR_03_0) \
_op_(GPIO_G_VM_04_0) \
_op_(GPIO_G_SCR_04_0) \
_op_(GPIO_G_VM_05_0) \
_op_(GPIO_G_SCR_05_0) \
_op_(GPIO_G_VM_06_0) \
_op_(GPIO_G_SCR_06_0) \
_op_(GPIO_G_VM_07_0) \
_op_(GPIO_G_SCR_07_0) \
_op_(GPIO_H_VM_00_0) \
_op_(GPIO_H_SCR_00_0) \
_op_(GPIO_H_VM_01_0) \
_op_(GPIO_H_SCR_01_0) \
_op_(GPIO_H_VM_02_0) \
_op_(GPIO_H_SCR_02_0) \
_op_(GPIO_H_VM_03_0) \
_op_(GPIO_H_SCR_03_0) \
_op_(GPIO_H_VM_04_0) \
_op_(GPIO_H_SCR_04_0) \
_op_(GPIO_H_VM_05_0) \
_op_(GPIO_H_SCR_05_0) \
_op_(GPIO_H_VM_06_0) \
_op_(GPIO_H_SCR_06_0) \
_op_(GPIO_H_VM_07_0) \
_op_(GPIO_H_SCR_07_0) \
_op_(GPIO_I_VM_00_0) \
_op_(GPIO_I_SCR_00_0) \
_op_(GPIO_I_VM_01_0) \
_op_(GPIO_I_SCR_01_0) \
_op_(GPIO_I_VM_02_0) \
_op_(GPIO_I_SCR_02_0) \
_op_(GPIO_I_VM_03_0) \
_op_(GPIO_I_SCR_03_0) \
_op_(GPIO_I_VM_04_0) \
_op_(GPIO_I_SCR_04_0) \
_op_(GPIO_I_VM_05_0) \
_op_(GPIO_I_SCR_05_0) \
_op_(GPIO_I_VM_06_0) \
_op_(GPIO_I_SCR_06_0) \
_op_(GPIO_CTL4_VM_SCR_0) \
_op_(GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL4_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL4_SCR_0) \
_op_(GPIO_CTL4_ICG_EN_OVERRIDE_0) \
_op_(GPIO_G_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_G_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_H_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_I_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL4_SPARE_0) \
_op_(GPIO_J_VM_00_0) \
_op_(GPIO_J_SCR_00_0) \
_op_(GPIO_J_VM_01_0) \
_op_(GPIO_J_SCR_01_0) \
_op_(GPIO_J_VM_02_0) \
_op_(GPIO_J_SCR_02_0) \
_op_(GPIO_J_VM_03_0) \
_op_(GPIO_J_SCR_03_0) \
_op_(GPIO_J_VM_04_0) \
_op_(GPIO_J_SCR_04_0) \
_op_(GPIO_J_VM_05_0) \
_op_(GPIO_J_SCR_05_0) \
_op_(GPIO_C_VM_00_0) \
_op_(GPIO_C_SCR_00_0) \
_op_(GPIO_C_VM_01_0) \
_op_(GPIO_C_SCR_01_0) \
_op_(GPIO_C_VM_02_0) \
_op_(GPIO_C_SCR_02_0) \
_op_(GPIO_C_VM_03_0) \
_op_(GPIO_C_SCR_03_0) \
_op_(GPIO_C_VM_04_0) \
_op_(GPIO_C_SCR_04_0) \
_op_(GPIO_C_VM_05_0) \
_op_(GPIO_C_SCR_05_0) \
_op_(GPIO_C_VM_06_0) \
_op_(GPIO_C_SCR_06_0) \
_op_(GPIO_C_VM_07_0) \
_op_(GPIO_C_SCR_07_0) \
_op_(GPIO_D_VM_00_0) \
_op_(GPIO_D_SCR_00_0) \
_op_(GPIO_D_VM_01_0) \
_op_(GPIO_D_SCR_01_0) \
_op_(GPIO_D_VM_02_0) \
_op_(GPIO_D_SCR_02_0) \
_op_(GPIO_D_VM_03_0) \
_op_(GPIO_D_SCR_03_0) \
_op_(GPIO_E_VM_00_0) \
_op_(GPIO_E_SCR_00_0) \
_op_(GPIO_E_VM_01_0) \
_op_(GPIO_E_SCR_01_0) \
_op_(GPIO_E_VM_02_0) \
_op_(GPIO_E_SCR_02_0) \
_op_(GPIO_E_VM_03_0) \
_op_(GPIO_E_SCR_03_0) \
_op_(GPIO_E_VM_04_0) \
_op_(GPIO_E_SCR_04_0) \
_op_(GPIO_E_VM_05_0) \
_op_(GPIO_E_SCR_05_0) \
_op_(GPIO_E_VM_06_0) \
_op_(GPIO_E_SCR_06_0) \
_op_(GPIO_E_VM_07_0) \
_op_(GPIO_E_SCR_07_0) \
_op_(GPIO_F_VM_00_0) \
_op_(GPIO_F_SCR_00_0) \
_op_(GPIO_F_VM_01_0) \
_op_(GPIO_F_SCR_01_0) \
_op_(GPIO_F_VM_02_0) \
_op_(GPIO_F_SCR_02_0) \
_op_(GPIO_F_VM_03_0) \
_op_(GPIO_F_SCR_03_0) \
_op_(GPIO_F_VM_04_0) \
_op_(GPIO_F_SCR_04_0) \
_op_(GPIO_F_VM_05_0) \
_op_(GPIO_F_SCR_05_0) \
_op_(GPIO_CTL5_VM_SCR_0) \
_op_(GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0) \
_op_(GPIO_CTL5_INTERRUPT_STATUS_VM_0) \
_op_(GPIO_CTL5_SCR_0) \
_op_(GPIO_CTL5_ICG_EN_OVERRIDE_0) \
_op_(GPIO_J_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_J_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_C_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_D_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_E_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT0_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT1_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT2_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT3_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT4_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT5_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT6_ROUTE_MAPPING_0) \
_op_(GPIO_F_INT7_ROUTE_MAPPING_0) \
_op_(GPIO_CTL5_SPARE_0) \
_op_(GPIO_A_ENABLE_CONFIG_00_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_A_INPUT_00_0) \
_op_(GPIO_A_OUTPUT_CONTROL_00_0) \
_op_(GPIO_A_OUTPUT_VALUE_00_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_A_ENABLE_CONFIG_01_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_A_INPUT_01_0) \
_op_(GPIO_A_OUTPUT_CONTROL_01_0) \
_op_(GPIO_A_OUTPUT_VALUE_01_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_A_ENABLE_CONFIG_02_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_A_INPUT_02_0) \
_op_(GPIO_A_OUTPUT_CONTROL_02_0) \
_op_(GPIO_A_OUTPUT_VALUE_02_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_A_ENABLE_CONFIG_03_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_A_INPUT_03_0) \
_op_(GPIO_A_OUTPUT_CONTROL_03_0) \
_op_(GPIO_A_OUTPUT_VALUE_03_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_A_ENABLE_CONFIG_04_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_A_INPUT_04_0) \
_op_(GPIO_A_OUTPUT_CONTROL_04_0) \
_op_(GPIO_A_OUTPUT_VALUE_04_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_A_ENABLE_CONFIG_05_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_A_INPUT_05_0) \
_op_(GPIO_A_OUTPUT_CONTROL_05_0) \
_op_(GPIO_A_OUTPUT_VALUE_05_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_A_ENABLE_CONFIG_06_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_A_INPUT_06_0) \
_op_(GPIO_A_OUTPUT_CONTROL_06_0) \
_op_(GPIO_A_OUTPUT_VALUE_06_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_A_ENABLE_CONFIG_07_0) \
_op_(GPIO_A_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_A_INPUT_07_0) \
_op_(GPIO_A_OUTPUT_CONTROL_07_0) \
_op_(GPIO_A_OUTPUT_VALUE_07_0) \
_op_(GPIO_A_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_A_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_AC_ENABLE_CONFIG_00_0) \
_op_(GPIO_AC_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_AC_INPUT_00_0) \
_op_(GPIO_AC_OUTPUT_CONTROL_00_0) \
_op_(GPIO_AC_OUTPUT_VALUE_00_0) \
_op_(GPIO_AC_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_AC_ENABLE_CONFIG_01_0) \
_op_(GPIO_AC_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_AC_INPUT_01_0) \
_op_(GPIO_AC_OUTPUT_CONTROL_01_0) \
_op_(GPIO_AC_OUTPUT_VALUE_01_0) \
_op_(GPIO_AC_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_AC_ENABLE_CONFIG_02_0) \
_op_(GPIO_AC_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_AC_INPUT_02_0) \
_op_(GPIO_AC_OUTPUT_CONTROL_02_0) \
_op_(GPIO_AC_OUTPUT_VALUE_02_0) \
_op_(GPIO_AC_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_AC_ENABLE_CONFIG_03_0) \
_op_(GPIO_AC_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_AC_INPUT_03_0) \
_op_(GPIO_AC_OUTPUT_CONTROL_03_0) \
_op_(GPIO_AC_OUTPUT_VALUE_03_0) \
_op_(GPIO_AC_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_AC_ENABLE_CONFIG_04_0) \
_op_(GPIO_AC_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_AC_INPUT_04_0) \
_op_(GPIO_AC_OUTPUT_CONTROL_04_0) \
_op_(GPIO_AC_OUTPUT_VALUE_04_0) \
_op_(GPIO_AC_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_AC_ENABLE_CONFIG_05_0) \
_op_(GPIO_AC_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_AC_INPUT_05_0) \
_op_(GPIO_AC_OUTPUT_CONTROL_05_0) \
_op_(GPIO_AC_OUTPUT_VALUE_05_0) \
_op_(GPIO_AC_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_AC_ENABLE_CONFIG_06_0) \
_op_(GPIO_AC_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_AC_INPUT_06_0) \
_op_(GPIO_AC_OUTPUT_CONTROL_06_0) \
_op_(GPIO_AC_OUTPUT_VALUE_06_0) \
_op_(GPIO_AC_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_AC_ENABLE_CONFIG_07_0) \
_op_(GPIO_AC_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_AC_INPUT_07_0) \
_op_(GPIO_AC_OUTPUT_CONTROL_07_0) \
_op_(GPIO_AC_OUTPUT_VALUE_07_0) \
_op_(GPIO_AC_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_AC_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_AC_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_AC_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_AC_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_AC_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_AC_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_AC_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_AC_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_AD_ENABLE_CONFIG_00_0) \
_op_(GPIO_AD_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_AD_INPUT_00_0) \
_op_(GPIO_AD_OUTPUT_CONTROL_00_0) \
_op_(GPIO_AD_OUTPUT_VALUE_00_0) \
_op_(GPIO_AD_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_AD_ENABLE_CONFIG_01_0) \
_op_(GPIO_AD_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_AD_INPUT_01_0) \
_op_(GPIO_AD_OUTPUT_CONTROL_01_0) \
_op_(GPIO_AD_OUTPUT_VALUE_01_0) \
_op_(GPIO_AD_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_AD_ENABLE_CONFIG_02_0) \
_op_(GPIO_AD_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_AD_INPUT_02_0) \
_op_(GPIO_AD_OUTPUT_CONTROL_02_0) \
_op_(GPIO_AD_OUTPUT_VALUE_02_0) \
_op_(GPIO_AD_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_AD_ENABLE_CONFIG_03_0) \
_op_(GPIO_AD_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_AD_INPUT_03_0) \
_op_(GPIO_AD_OUTPUT_CONTROL_03_0) \
_op_(GPIO_AD_OUTPUT_VALUE_03_0) \
_op_(GPIO_AD_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_AD_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_AD_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_AD_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_AD_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_AD_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_AD_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_AD_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_AD_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_B_ENABLE_CONFIG_00_0) \
_op_(GPIO_B_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_B_INPUT_00_0) \
_op_(GPIO_B_OUTPUT_CONTROL_00_0) \
_op_(GPIO_B_OUTPUT_VALUE_00_0) \
_op_(GPIO_B_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_B_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_X_ENABLE_CONFIG_00_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_X_INPUT_00_0) \
_op_(GPIO_X_OUTPUT_CONTROL_00_0) \
_op_(GPIO_X_OUTPUT_VALUE_00_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_X_ENABLE_CONFIG_01_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_X_INPUT_01_0) \
_op_(GPIO_X_OUTPUT_CONTROL_01_0) \
_op_(GPIO_X_OUTPUT_VALUE_01_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_X_ENABLE_CONFIG_02_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_X_INPUT_02_0) \
_op_(GPIO_X_OUTPUT_CONTROL_02_0) \
_op_(GPIO_X_OUTPUT_VALUE_02_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_X_ENABLE_CONFIG_03_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_X_INPUT_03_0) \
_op_(GPIO_X_OUTPUT_CONTROL_03_0) \
_op_(GPIO_X_OUTPUT_VALUE_03_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_X_ENABLE_CONFIG_04_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_X_INPUT_04_0) \
_op_(GPIO_X_OUTPUT_CONTROL_04_0) \
_op_(GPIO_X_OUTPUT_VALUE_04_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_X_ENABLE_CONFIG_05_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_X_INPUT_05_0) \
_op_(GPIO_X_OUTPUT_CONTROL_05_0) \
_op_(GPIO_X_OUTPUT_VALUE_05_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_X_ENABLE_CONFIG_06_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_X_INPUT_06_0) \
_op_(GPIO_X_OUTPUT_CONTROL_06_0) \
_op_(GPIO_X_OUTPUT_VALUE_06_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_X_ENABLE_CONFIG_07_0) \
_op_(GPIO_X_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_X_INPUT_07_0) \
_op_(GPIO_X_OUTPUT_CONTROL_07_0) \
_op_(GPIO_X_OUTPUT_VALUE_07_0) \
_op_(GPIO_X_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_X_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_Y_ENABLE_CONFIG_00_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_Y_INPUT_00_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_00_0) \
_op_(GPIO_Y_OUTPUT_VALUE_00_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_Y_ENABLE_CONFIG_01_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_Y_INPUT_01_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_01_0) \
_op_(GPIO_Y_OUTPUT_VALUE_01_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_Y_ENABLE_CONFIG_02_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_Y_INPUT_02_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_02_0) \
_op_(GPIO_Y_OUTPUT_VALUE_02_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_Y_ENABLE_CONFIG_03_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_Y_INPUT_03_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_03_0) \
_op_(GPIO_Y_OUTPUT_VALUE_03_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_Y_ENABLE_CONFIG_04_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_Y_INPUT_04_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_04_0) \
_op_(GPIO_Y_OUTPUT_VALUE_04_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_Y_ENABLE_CONFIG_05_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_Y_INPUT_05_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_05_0) \
_op_(GPIO_Y_OUTPUT_VALUE_05_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_Y_ENABLE_CONFIG_06_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_Y_INPUT_06_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_06_0) \
_op_(GPIO_Y_OUTPUT_VALUE_06_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_Y_ENABLE_CONFIG_07_0) \
_op_(GPIO_Y_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_Y_INPUT_07_0) \
_op_(GPIO_Y_OUTPUT_CONTROL_07_0) \
_op_(GPIO_Y_OUTPUT_VALUE_07_0) \
_op_(GPIO_Y_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_Y_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_Z_ENABLE_CONFIG_00_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_Z_INPUT_00_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_00_0) \
_op_(GPIO_Z_OUTPUT_VALUE_00_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_Z_ENABLE_CONFIG_01_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_Z_INPUT_01_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_01_0) \
_op_(GPIO_Z_OUTPUT_VALUE_01_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_Z_ENABLE_CONFIG_02_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_Z_INPUT_02_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_02_0) \
_op_(GPIO_Z_OUTPUT_VALUE_02_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_Z_ENABLE_CONFIG_03_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_Z_INPUT_03_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_03_0) \
_op_(GPIO_Z_OUTPUT_VALUE_03_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_Z_ENABLE_CONFIG_04_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_Z_INPUT_04_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_04_0) \
_op_(GPIO_Z_OUTPUT_VALUE_04_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_Z_ENABLE_CONFIG_05_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_Z_INPUT_05_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_05_0) \
_op_(GPIO_Z_OUTPUT_VALUE_05_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_Z_ENABLE_CONFIG_06_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_Z_INPUT_06_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_06_0) \
_op_(GPIO_Z_OUTPUT_VALUE_06_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_Z_ENABLE_CONFIG_07_0) \
_op_(GPIO_Z_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_Z_INPUT_07_0) \
_op_(GPIO_Z_OUTPUT_CONTROL_07_0) \
_op_(GPIO_Z_OUTPUT_VALUE_07_0) \
_op_(GPIO_Z_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_Z_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_M_ENABLE_CONFIG_00_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_M_INPUT_00_0) \
_op_(GPIO_M_OUTPUT_CONTROL_00_0) \
_op_(GPIO_M_OUTPUT_VALUE_00_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_M_ENABLE_CONFIG_01_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_M_INPUT_01_0) \
_op_(GPIO_M_OUTPUT_CONTROL_01_0) \
_op_(GPIO_M_OUTPUT_VALUE_01_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_M_ENABLE_CONFIG_02_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_M_INPUT_02_0) \
_op_(GPIO_M_OUTPUT_CONTROL_02_0) \
_op_(GPIO_M_OUTPUT_VALUE_02_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_M_ENABLE_CONFIG_03_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_M_INPUT_03_0) \
_op_(GPIO_M_OUTPUT_CONTROL_03_0) \
_op_(GPIO_M_OUTPUT_VALUE_03_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_M_ENABLE_CONFIG_04_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_M_INPUT_04_0) \
_op_(GPIO_M_OUTPUT_CONTROL_04_0) \
_op_(GPIO_M_OUTPUT_VALUE_04_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_M_ENABLE_CONFIG_05_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_M_INPUT_05_0) \
_op_(GPIO_M_OUTPUT_CONTROL_05_0) \
_op_(GPIO_M_OUTPUT_VALUE_05_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_M_ENABLE_CONFIG_06_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_M_INPUT_06_0) \
_op_(GPIO_M_OUTPUT_CONTROL_06_0) \
_op_(GPIO_M_OUTPUT_VALUE_06_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_M_ENABLE_CONFIG_07_0) \
_op_(GPIO_M_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_M_INPUT_07_0) \
_op_(GPIO_M_OUTPUT_CONTROL_07_0) \
_op_(GPIO_M_OUTPUT_VALUE_07_0) \
_op_(GPIO_M_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_M_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_N_ENABLE_CONFIG_00_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_N_INPUT_00_0) \
_op_(GPIO_N_OUTPUT_CONTROL_00_0) \
_op_(GPIO_N_OUTPUT_VALUE_00_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_N_ENABLE_CONFIG_01_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_N_INPUT_01_0) \
_op_(GPIO_N_OUTPUT_CONTROL_01_0) \
_op_(GPIO_N_OUTPUT_VALUE_01_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_N_ENABLE_CONFIG_02_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_N_INPUT_02_0) \
_op_(GPIO_N_OUTPUT_CONTROL_02_0) \
_op_(GPIO_N_OUTPUT_VALUE_02_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_N_ENABLE_CONFIG_03_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_N_INPUT_03_0) \
_op_(GPIO_N_OUTPUT_CONTROL_03_0) \
_op_(GPIO_N_OUTPUT_VALUE_03_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_N_ENABLE_CONFIG_04_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_N_INPUT_04_0) \
_op_(GPIO_N_OUTPUT_CONTROL_04_0) \
_op_(GPIO_N_OUTPUT_VALUE_04_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_N_ENABLE_CONFIG_05_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_N_INPUT_05_0) \
_op_(GPIO_N_OUTPUT_CONTROL_05_0) \
_op_(GPIO_N_OUTPUT_VALUE_05_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_N_ENABLE_CONFIG_06_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_N_INPUT_06_0) \
_op_(GPIO_N_OUTPUT_CONTROL_06_0) \
_op_(GPIO_N_OUTPUT_VALUE_06_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_N_ENABLE_CONFIG_07_0) \
_op_(GPIO_N_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_N_INPUT_07_0) \
_op_(GPIO_N_OUTPUT_CONTROL_07_0) \
_op_(GPIO_N_OUTPUT_VALUE_07_0) \
_op_(GPIO_N_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_N_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_P_ENABLE_CONFIG_00_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_P_INPUT_00_0) \
_op_(GPIO_P_OUTPUT_CONTROL_00_0) \
_op_(GPIO_P_OUTPUT_VALUE_00_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_P_ENABLE_CONFIG_01_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_P_INPUT_01_0) \
_op_(GPIO_P_OUTPUT_CONTROL_01_0) \
_op_(GPIO_P_OUTPUT_VALUE_01_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_P_ENABLE_CONFIG_02_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_P_INPUT_02_0) \
_op_(GPIO_P_OUTPUT_CONTROL_02_0) \
_op_(GPIO_P_OUTPUT_VALUE_02_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_P_ENABLE_CONFIG_03_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_P_INPUT_03_0) \
_op_(GPIO_P_OUTPUT_CONTROL_03_0) \
_op_(GPIO_P_OUTPUT_VALUE_03_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_P_ENABLE_CONFIG_04_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_P_INPUT_04_0) \
_op_(GPIO_P_OUTPUT_CONTROL_04_0) \
_op_(GPIO_P_OUTPUT_VALUE_04_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_P_ENABLE_CONFIG_05_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_P_INPUT_05_0) \
_op_(GPIO_P_OUTPUT_CONTROL_05_0) \
_op_(GPIO_P_OUTPUT_VALUE_05_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_P_ENABLE_CONFIG_06_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_P_INPUT_06_0) \
_op_(GPIO_P_OUTPUT_CONTROL_06_0) \
_op_(GPIO_P_OUTPUT_VALUE_06_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_P_ENABLE_CONFIG_07_0) \
_op_(GPIO_P_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_P_INPUT_07_0) \
_op_(GPIO_P_OUTPUT_CONTROL_07_0) \
_op_(GPIO_P_OUTPUT_VALUE_07_0) \
_op_(GPIO_P_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_P_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_Q_ENABLE_CONFIG_00_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_Q_INPUT_00_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_00_0) \
_op_(GPIO_Q_OUTPUT_VALUE_00_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_Q_ENABLE_CONFIG_01_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_Q_INPUT_01_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_01_0) \
_op_(GPIO_Q_OUTPUT_VALUE_01_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_Q_ENABLE_CONFIG_02_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_Q_INPUT_02_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_02_0) \
_op_(GPIO_Q_OUTPUT_VALUE_02_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_Q_ENABLE_CONFIG_03_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_Q_INPUT_03_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_03_0) \
_op_(GPIO_Q_OUTPUT_VALUE_03_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_Q_ENABLE_CONFIG_04_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_Q_INPUT_04_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_04_0) \
_op_(GPIO_Q_OUTPUT_VALUE_04_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_Q_ENABLE_CONFIG_05_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_Q_INPUT_05_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_05_0) \
_op_(GPIO_Q_OUTPUT_VALUE_05_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_Q_ENABLE_CONFIG_06_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_Q_INPUT_06_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_06_0) \
_op_(GPIO_Q_OUTPUT_VALUE_06_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_Q_ENABLE_CONFIG_07_0) \
_op_(GPIO_Q_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_Q_INPUT_07_0) \
_op_(GPIO_Q_OUTPUT_CONTROL_07_0) \
_op_(GPIO_Q_OUTPUT_VALUE_07_0) \
_op_(GPIO_Q_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_Q_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_R_ENABLE_CONFIG_00_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_R_INPUT_00_0) \
_op_(GPIO_R_OUTPUT_CONTROL_00_0) \
_op_(GPIO_R_OUTPUT_VALUE_00_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_R_ENABLE_CONFIG_01_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_R_INPUT_01_0) \
_op_(GPIO_R_OUTPUT_CONTROL_01_0) \
_op_(GPIO_R_OUTPUT_VALUE_01_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_R_ENABLE_CONFIG_02_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_R_INPUT_02_0) \
_op_(GPIO_R_OUTPUT_CONTROL_02_0) \
_op_(GPIO_R_OUTPUT_VALUE_02_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_R_ENABLE_CONFIG_03_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_R_INPUT_03_0) \
_op_(GPIO_R_OUTPUT_CONTROL_03_0) \
_op_(GPIO_R_OUTPUT_VALUE_03_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_R_ENABLE_CONFIG_04_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_R_INPUT_04_0) \
_op_(GPIO_R_OUTPUT_CONTROL_04_0) \
_op_(GPIO_R_OUTPUT_VALUE_04_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_R_ENABLE_CONFIG_05_0) \
_op_(GPIO_R_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_R_INPUT_05_0) \
_op_(GPIO_R_OUTPUT_CONTROL_05_0) \
_op_(GPIO_R_OUTPUT_VALUE_05_0) \
_op_(GPIO_R_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_R_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_K_ENABLE_CONFIG_00_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_K_INPUT_00_0) \
_op_(GPIO_K_OUTPUT_CONTROL_00_0) \
_op_(GPIO_K_OUTPUT_VALUE_00_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_K_ENABLE_CONFIG_01_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_K_INPUT_01_0) \
_op_(GPIO_K_OUTPUT_CONTROL_01_0) \
_op_(GPIO_K_OUTPUT_VALUE_01_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_K_ENABLE_CONFIG_02_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_K_INPUT_02_0) \
_op_(GPIO_K_OUTPUT_CONTROL_02_0) \
_op_(GPIO_K_OUTPUT_VALUE_02_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_K_ENABLE_CONFIG_03_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_K_INPUT_03_0) \
_op_(GPIO_K_OUTPUT_CONTROL_03_0) \
_op_(GPIO_K_OUTPUT_VALUE_03_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_K_ENABLE_CONFIG_04_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_K_INPUT_04_0) \
_op_(GPIO_K_OUTPUT_CONTROL_04_0) \
_op_(GPIO_K_OUTPUT_VALUE_04_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_K_ENABLE_CONFIG_05_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_K_INPUT_05_0) \
_op_(GPIO_K_OUTPUT_CONTROL_05_0) \
_op_(GPIO_K_OUTPUT_VALUE_05_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_K_ENABLE_CONFIG_06_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_K_INPUT_06_0) \
_op_(GPIO_K_OUTPUT_CONTROL_06_0) \
_op_(GPIO_K_OUTPUT_VALUE_06_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_K_ENABLE_CONFIG_07_0) \
_op_(GPIO_K_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_K_INPUT_07_0) \
_op_(GPIO_K_OUTPUT_CONTROL_07_0) \
_op_(GPIO_K_OUTPUT_VALUE_07_0) \
_op_(GPIO_K_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_K_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_L_ENABLE_CONFIG_00_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_L_INPUT_00_0) \
_op_(GPIO_L_OUTPUT_CONTROL_00_0) \
_op_(GPIO_L_OUTPUT_VALUE_00_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_L_ENABLE_CONFIG_01_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_L_INPUT_01_0) \
_op_(GPIO_L_OUTPUT_CONTROL_01_0) \
_op_(GPIO_L_OUTPUT_VALUE_01_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_L_ENABLE_CONFIG_02_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_L_INPUT_02_0) \
_op_(GPIO_L_OUTPUT_CONTROL_02_0) \
_op_(GPIO_L_OUTPUT_VALUE_02_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_L_ENABLE_CONFIG_03_0) \
_op_(GPIO_L_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_L_INPUT_03_0) \
_op_(GPIO_L_OUTPUT_CONTROL_03_0) \
_op_(GPIO_L_OUTPUT_VALUE_03_0) \
_op_(GPIO_L_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_L_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_AG_ENABLE_CONFIG_00_0) \
_op_(GPIO_AG_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_AG_INPUT_00_0) \
_op_(GPIO_AG_OUTPUT_CONTROL_00_0) \
_op_(GPIO_AG_OUTPUT_VALUE_00_0) \
_op_(GPIO_AG_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_AG_ENABLE_CONFIG_01_0) \
_op_(GPIO_AG_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_AG_INPUT_01_0) \
_op_(GPIO_AG_OUTPUT_CONTROL_01_0) \
_op_(GPIO_AG_OUTPUT_VALUE_01_0) \
_op_(GPIO_AG_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_AG_ENABLE_CONFIG_02_0) \
_op_(GPIO_AG_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_AG_INPUT_02_0) \
_op_(GPIO_AG_OUTPUT_CONTROL_02_0) \
_op_(GPIO_AG_OUTPUT_VALUE_02_0) \
_op_(GPIO_AG_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_AG_ENABLE_CONFIG_03_0) \
_op_(GPIO_AG_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_AG_INPUT_03_0) \
_op_(GPIO_AG_OUTPUT_CONTROL_03_0) \
_op_(GPIO_AG_OUTPUT_VALUE_03_0) \
_op_(GPIO_AG_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_AG_ENABLE_CONFIG_04_0) \
_op_(GPIO_AG_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_AG_INPUT_04_0) \
_op_(GPIO_AG_OUTPUT_CONTROL_04_0) \
_op_(GPIO_AG_OUTPUT_VALUE_04_0) \
_op_(GPIO_AG_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_AG_ENABLE_CONFIG_05_0) \
_op_(GPIO_AG_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_AG_INPUT_05_0) \
_op_(GPIO_AG_OUTPUT_CONTROL_05_0) \
_op_(GPIO_AG_OUTPUT_VALUE_05_0) \
_op_(GPIO_AG_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_AG_ENABLE_CONFIG_06_0) \
_op_(GPIO_AG_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_AG_INPUT_06_0) \
_op_(GPIO_AG_OUTPUT_CONTROL_06_0) \
_op_(GPIO_AG_OUTPUT_VALUE_06_0) \
_op_(GPIO_AG_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_AG_ENABLE_CONFIG_07_0) \
_op_(GPIO_AG_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_AG_INPUT_07_0) \
_op_(GPIO_AG_OUTPUT_CONTROL_07_0) \
_op_(GPIO_AG_OUTPUT_VALUE_07_0) \
_op_(GPIO_AG_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_AG_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_AG_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_AG_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_AG_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_AG_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_AG_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_AG_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_AG_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_AE_ENABLE_CONFIG_00_0) \
_op_(GPIO_AE_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_AE_INPUT_00_0) \
_op_(GPIO_AE_OUTPUT_CONTROL_00_0) \
_op_(GPIO_AE_OUTPUT_VALUE_00_0) \
_op_(GPIO_AE_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_AE_ENABLE_CONFIG_01_0) \
_op_(GPIO_AE_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_AE_INPUT_01_0) \
_op_(GPIO_AE_OUTPUT_CONTROL_01_0) \
_op_(GPIO_AE_OUTPUT_VALUE_01_0) \
_op_(GPIO_AE_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_AE_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_AE_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_AE_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_AE_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_AE_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_AE_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_AE_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_AE_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_AF_ENABLE_CONFIG_00_0) \
_op_(GPIO_AF_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_AF_INPUT_00_0) \
_op_(GPIO_AF_OUTPUT_CONTROL_00_0) \
_op_(GPIO_AF_OUTPUT_VALUE_00_0) \
_op_(GPIO_AF_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_AF_ENABLE_CONFIG_01_0) \
_op_(GPIO_AF_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_AF_INPUT_01_0) \
_op_(GPIO_AF_OUTPUT_CONTROL_01_0) \
_op_(GPIO_AF_OUTPUT_VALUE_01_0) \
_op_(GPIO_AF_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_AF_ENABLE_CONFIG_02_0) \
_op_(GPIO_AF_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_AF_INPUT_02_0) \
_op_(GPIO_AF_OUTPUT_CONTROL_02_0) \
_op_(GPIO_AF_OUTPUT_VALUE_02_0) \
_op_(GPIO_AF_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_AF_ENABLE_CONFIG_03_0) \
_op_(GPIO_AF_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_AF_INPUT_03_0) \
_op_(GPIO_AF_OUTPUT_CONTROL_03_0) \
_op_(GPIO_AF_OUTPUT_VALUE_03_0) \
_op_(GPIO_AF_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_AF_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_AF_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_AF_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_AF_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_AF_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_AF_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_AF_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_AF_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_G_ENABLE_CONFIG_00_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_G_INPUT_00_0) \
_op_(GPIO_G_OUTPUT_CONTROL_00_0) \
_op_(GPIO_G_OUTPUT_VALUE_00_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_G_ENABLE_CONFIG_01_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_G_INPUT_01_0) \
_op_(GPIO_G_OUTPUT_CONTROL_01_0) \
_op_(GPIO_G_OUTPUT_VALUE_01_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_G_ENABLE_CONFIG_02_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_G_INPUT_02_0) \
_op_(GPIO_G_OUTPUT_CONTROL_02_0) \
_op_(GPIO_G_OUTPUT_VALUE_02_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_G_ENABLE_CONFIG_03_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_G_INPUT_03_0) \
_op_(GPIO_G_OUTPUT_CONTROL_03_0) \
_op_(GPIO_G_OUTPUT_VALUE_03_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_G_ENABLE_CONFIG_04_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_G_INPUT_04_0) \
_op_(GPIO_G_OUTPUT_CONTROL_04_0) \
_op_(GPIO_G_OUTPUT_VALUE_04_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_G_ENABLE_CONFIG_05_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_G_INPUT_05_0) \
_op_(GPIO_G_OUTPUT_CONTROL_05_0) \
_op_(GPIO_G_OUTPUT_VALUE_05_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_G_ENABLE_CONFIG_06_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_G_INPUT_06_0) \
_op_(GPIO_G_OUTPUT_CONTROL_06_0) \
_op_(GPIO_G_OUTPUT_VALUE_06_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_G_ENABLE_CONFIG_07_0) \
_op_(GPIO_G_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_G_INPUT_07_0) \
_op_(GPIO_G_OUTPUT_CONTROL_07_0) \
_op_(GPIO_G_OUTPUT_VALUE_07_0) \
_op_(GPIO_G_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_G_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_H_ENABLE_CONFIG_00_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_H_INPUT_00_0) \
_op_(GPIO_H_OUTPUT_CONTROL_00_0) \
_op_(GPIO_H_OUTPUT_VALUE_00_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_H_ENABLE_CONFIG_01_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_H_INPUT_01_0) \
_op_(GPIO_H_OUTPUT_CONTROL_01_0) \
_op_(GPIO_H_OUTPUT_VALUE_01_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_H_ENABLE_CONFIG_02_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_H_INPUT_02_0) \
_op_(GPIO_H_OUTPUT_CONTROL_02_0) \
_op_(GPIO_H_OUTPUT_VALUE_02_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_H_ENABLE_CONFIG_03_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_H_INPUT_03_0) \
_op_(GPIO_H_OUTPUT_CONTROL_03_0) \
_op_(GPIO_H_OUTPUT_VALUE_03_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_H_ENABLE_CONFIG_04_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_H_INPUT_04_0) \
_op_(GPIO_H_OUTPUT_CONTROL_04_0) \
_op_(GPIO_H_OUTPUT_VALUE_04_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_H_ENABLE_CONFIG_05_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_H_INPUT_05_0) \
_op_(GPIO_H_OUTPUT_CONTROL_05_0) \
_op_(GPIO_H_OUTPUT_VALUE_05_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_H_ENABLE_CONFIG_06_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_H_INPUT_06_0) \
_op_(GPIO_H_OUTPUT_CONTROL_06_0) \
_op_(GPIO_H_OUTPUT_VALUE_06_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_H_ENABLE_CONFIG_07_0) \
_op_(GPIO_H_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_H_INPUT_07_0) \
_op_(GPIO_H_OUTPUT_CONTROL_07_0) \
_op_(GPIO_H_OUTPUT_VALUE_07_0) \
_op_(GPIO_H_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_H_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_I_ENABLE_CONFIG_00_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_I_INPUT_00_0) \
_op_(GPIO_I_OUTPUT_CONTROL_00_0) \
_op_(GPIO_I_OUTPUT_VALUE_00_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_I_ENABLE_CONFIG_01_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_I_INPUT_01_0) \
_op_(GPIO_I_OUTPUT_CONTROL_01_0) \
_op_(GPIO_I_OUTPUT_VALUE_01_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_I_ENABLE_CONFIG_02_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_I_INPUT_02_0) \
_op_(GPIO_I_OUTPUT_CONTROL_02_0) \
_op_(GPIO_I_OUTPUT_VALUE_02_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_I_ENABLE_CONFIG_03_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_I_INPUT_03_0) \
_op_(GPIO_I_OUTPUT_CONTROL_03_0) \
_op_(GPIO_I_OUTPUT_VALUE_03_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_I_ENABLE_CONFIG_04_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_I_INPUT_04_0) \
_op_(GPIO_I_OUTPUT_CONTROL_04_0) \
_op_(GPIO_I_OUTPUT_VALUE_04_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_I_ENABLE_CONFIG_05_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_I_INPUT_05_0) \
_op_(GPIO_I_OUTPUT_CONTROL_05_0) \
_op_(GPIO_I_OUTPUT_VALUE_05_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_I_ENABLE_CONFIG_06_0) \
_op_(GPIO_I_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_I_INPUT_06_0) \
_op_(GPIO_I_OUTPUT_CONTROL_06_0) \
_op_(GPIO_I_OUTPUT_VALUE_06_0) \
_op_(GPIO_I_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_I_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_J_ENABLE_CONFIG_00_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_J_INPUT_00_0) \
_op_(GPIO_J_OUTPUT_CONTROL_00_0) \
_op_(GPIO_J_OUTPUT_VALUE_00_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_J_ENABLE_CONFIG_01_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_J_INPUT_01_0) \
_op_(GPIO_J_OUTPUT_CONTROL_01_0) \
_op_(GPIO_J_OUTPUT_VALUE_01_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_J_ENABLE_CONFIG_02_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_J_INPUT_02_0) \
_op_(GPIO_J_OUTPUT_CONTROL_02_0) \
_op_(GPIO_J_OUTPUT_VALUE_02_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_J_ENABLE_CONFIG_03_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_J_INPUT_03_0) \
_op_(GPIO_J_OUTPUT_CONTROL_03_0) \
_op_(GPIO_J_OUTPUT_VALUE_03_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_J_ENABLE_CONFIG_04_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_J_INPUT_04_0) \
_op_(GPIO_J_OUTPUT_CONTROL_04_0) \
_op_(GPIO_J_OUTPUT_VALUE_04_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_J_ENABLE_CONFIG_05_0) \
_op_(GPIO_J_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_J_INPUT_05_0) \
_op_(GPIO_J_OUTPUT_CONTROL_05_0) \
_op_(GPIO_J_OUTPUT_VALUE_05_0) \
_op_(GPIO_J_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_J_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_C_ENABLE_CONFIG_00_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_C_INPUT_00_0) \
_op_(GPIO_C_OUTPUT_CONTROL_00_0) \
_op_(GPIO_C_OUTPUT_VALUE_00_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_C_ENABLE_CONFIG_01_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_C_INPUT_01_0) \
_op_(GPIO_C_OUTPUT_CONTROL_01_0) \
_op_(GPIO_C_OUTPUT_VALUE_01_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_C_ENABLE_CONFIG_02_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_C_INPUT_02_0) \
_op_(GPIO_C_OUTPUT_CONTROL_02_0) \
_op_(GPIO_C_OUTPUT_VALUE_02_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_C_ENABLE_CONFIG_03_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_C_INPUT_03_0) \
_op_(GPIO_C_OUTPUT_CONTROL_03_0) \
_op_(GPIO_C_OUTPUT_VALUE_03_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_C_ENABLE_CONFIG_04_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_C_INPUT_04_0) \
_op_(GPIO_C_OUTPUT_CONTROL_04_0) \
_op_(GPIO_C_OUTPUT_VALUE_04_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_C_ENABLE_CONFIG_05_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_C_INPUT_05_0) \
_op_(GPIO_C_OUTPUT_CONTROL_05_0) \
_op_(GPIO_C_OUTPUT_VALUE_05_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_C_ENABLE_CONFIG_06_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_C_INPUT_06_0) \
_op_(GPIO_C_OUTPUT_CONTROL_06_0) \
_op_(GPIO_C_OUTPUT_VALUE_06_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_C_ENABLE_CONFIG_07_0) \
_op_(GPIO_C_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_C_INPUT_07_0) \
_op_(GPIO_C_OUTPUT_CONTROL_07_0) \
_op_(GPIO_C_OUTPUT_VALUE_07_0) \
_op_(GPIO_C_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_C_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_D_ENABLE_CONFIG_00_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_D_INPUT_00_0) \
_op_(GPIO_D_OUTPUT_CONTROL_00_0) \
_op_(GPIO_D_OUTPUT_VALUE_00_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_D_ENABLE_CONFIG_01_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_D_INPUT_01_0) \
_op_(GPIO_D_OUTPUT_CONTROL_01_0) \
_op_(GPIO_D_OUTPUT_VALUE_01_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_D_ENABLE_CONFIG_02_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_D_INPUT_02_0) \
_op_(GPIO_D_OUTPUT_CONTROL_02_0) \
_op_(GPIO_D_OUTPUT_VALUE_02_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_D_ENABLE_CONFIG_03_0) \
_op_(GPIO_D_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_D_INPUT_03_0) \
_op_(GPIO_D_OUTPUT_CONTROL_03_0) \
_op_(GPIO_D_OUTPUT_VALUE_03_0) \
_op_(GPIO_D_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_D_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_E_ENABLE_CONFIG_00_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_E_INPUT_00_0) \
_op_(GPIO_E_OUTPUT_CONTROL_00_0) \
_op_(GPIO_E_OUTPUT_VALUE_00_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_E_ENABLE_CONFIG_01_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_E_INPUT_01_0) \
_op_(GPIO_E_OUTPUT_CONTROL_01_0) \
_op_(GPIO_E_OUTPUT_VALUE_01_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_E_ENABLE_CONFIG_02_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_E_INPUT_02_0) \
_op_(GPIO_E_OUTPUT_CONTROL_02_0) \
_op_(GPIO_E_OUTPUT_VALUE_02_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_E_ENABLE_CONFIG_03_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_E_INPUT_03_0) \
_op_(GPIO_E_OUTPUT_CONTROL_03_0) \
_op_(GPIO_E_OUTPUT_VALUE_03_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_E_ENABLE_CONFIG_04_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_E_INPUT_04_0) \
_op_(GPIO_E_OUTPUT_CONTROL_04_0) \
_op_(GPIO_E_OUTPUT_VALUE_04_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_E_ENABLE_CONFIG_05_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_E_INPUT_05_0) \
_op_(GPIO_E_OUTPUT_CONTROL_05_0) \
_op_(GPIO_E_OUTPUT_VALUE_05_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_E_ENABLE_CONFIG_06_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_06_0) \
_op_(GPIO_E_INPUT_06_0) \
_op_(GPIO_E_OUTPUT_CONTROL_06_0) \
_op_(GPIO_E_OUTPUT_VALUE_06_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_06_0) \
_op_(GPIO_E_ENABLE_CONFIG_07_0) \
_op_(GPIO_E_DEBOUNCE_THRESHOLD_07_0) \
_op_(GPIO_E_INPUT_07_0) \
_op_(GPIO_E_OUTPUT_CONTROL_07_0) \
_op_(GPIO_E_OUTPUT_VALUE_07_0) \
_op_(GPIO_E_INTERRUPT_CLEAR_07_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_E_INTERRUPT_STATUS_G7_0) \
_op_(GPIO_F_ENABLE_CONFIG_00_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_00_0) \
_op_(GPIO_F_INPUT_00_0) \
_op_(GPIO_F_OUTPUT_CONTROL_00_0) \
_op_(GPIO_F_OUTPUT_VALUE_00_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_00_0) \
_op_(GPIO_F_ENABLE_CONFIG_01_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_01_0) \
_op_(GPIO_F_INPUT_01_0) \
_op_(GPIO_F_OUTPUT_CONTROL_01_0) \
_op_(GPIO_F_OUTPUT_VALUE_01_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_01_0) \
_op_(GPIO_F_ENABLE_CONFIG_02_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_02_0) \
_op_(GPIO_F_INPUT_02_0) \
_op_(GPIO_F_OUTPUT_CONTROL_02_0) \
_op_(GPIO_F_OUTPUT_VALUE_02_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_02_0) \
_op_(GPIO_F_ENABLE_CONFIG_03_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_03_0) \
_op_(GPIO_F_INPUT_03_0) \
_op_(GPIO_F_OUTPUT_CONTROL_03_0) \
_op_(GPIO_F_OUTPUT_VALUE_03_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_03_0) \
_op_(GPIO_F_ENABLE_CONFIG_04_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_04_0) \
_op_(GPIO_F_INPUT_04_0) \
_op_(GPIO_F_OUTPUT_CONTROL_04_0) \
_op_(GPIO_F_OUTPUT_VALUE_04_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_04_0) \
_op_(GPIO_F_ENABLE_CONFIG_05_0) \
_op_(GPIO_F_DEBOUNCE_THRESHOLD_05_0) \
_op_(GPIO_F_INPUT_05_0) \
_op_(GPIO_F_OUTPUT_CONTROL_05_0) \
_op_(GPIO_F_OUTPUT_VALUE_05_0) \
_op_(GPIO_F_INTERRUPT_CLEAR_05_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G0_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G1_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G2_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G3_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G4_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G5_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G6_0) \
_op_(GPIO_F_INTERRUPT_STATUS_G7_0)


//
// ADDRESS SPACES
//

#define BASE_ADDRESS_GPIO       0x00000000

//
// ARGPIO REGISTER BANKS
//

#define GPIO0_FIRST_REG 0x0000 // GPIO_A_VM_00_0
#define GPIO0_LAST_REG 0x009c // GPIO_AD_SCR_03_0
#define GPIO1_FIRST_REG 0x00c0 // GPIO_B_VM_00_0
#define GPIO1_LAST_REG 0x00c4 // GPIO_B_SCR_00_0
#define GPIO2_FIRST_REG 0x0800 // GPIO_CTL0_VM_SCR_0
#define GPIO2_LAST_REG 0x0894 // GPIO_CTL0_SPARE_0
#define GPIO3_FIRST_REG 0x1000 // GPIO_X_VM_00_0
#define GPIO3_LAST_REG 0x10bc // GPIO_Z_SCR_07_0
#define GPIO4_FIRST_REG 0x1800 // GPIO_CTL1_VM_SCR_0
#define GPIO4_LAST_REG 0x1874 // GPIO_CTL1_SPARE_0
#define GPIO5_FIRST_REG 0x2000 // GPIO_M_VM_00_0
#define GPIO5_LAST_REG 0x212c // GPIO_R_SCR_05_0
#define GPIO6_FIRST_REG 0x2800 // GPIO_CTL2_VM_SCR_0
#define GPIO6_LAST_REG 0x28b4 // GPIO_CTL2_SPARE_0
#define GPIO7_FIRST_REG 0x3000 // GPIO_K_VM_00_0
#define GPIO7_LAST_REG 0x305c // GPIO_L_SCR_03_0
#define GPIO8_FIRST_REG 0x3080 // GPIO_AG_VM_00_0
#define GPIO8_LAST_REG 0x30cc // GPIO_AE_SCR_01_0
#define GPIO9_FIRST_REG 0x3100 // GPIO_AF_VM_00_0
#define GPIO9_LAST_REG 0x311c // GPIO_AF_SCR_03_0
#define GPIO10_FIRST_REG 0x3800 // GPIO_CTL3_VM_SCR_0
#define GPIO10_LAST_REG 0x38b4 // GPIO_CTL3_SPARE_0
#define GPIO11_FIRST_REG 0x4000 // GPIO_G_VM_00_0
#define GPIO11_LAST_REG 0x40b4 // GPIO_I_SCR_06_0
#define GPIO12_FIRST_REG 0x4800 // GPIO_CTL4_VM_SCR_0
#define GPIO12_LAST_REG 0x4874 // GPIO_CTL4_SPARE_0
#define GPIO13_FIRST_REG 0x5000 // GPIO_J_VM_00_0
#define GPIO13_LAST_REG 0x502c // GPIO_J_SCR_05_0
#define GPIO14_FIRST_REG 0x5040 // GPIO_C_VM_00_0
#define GPIO14_LAST_REG 0x509c // GPIO_D_SCR_03_0
#define GPIO15_FIRST_REG 0x50c0 // GPIO_E_VM_00_0
#define GPIO15_LAST_REG 0x512c // GPIO_F_SCR_05_0
#define GPIO16_FIRST_REG 0x5800 // GPIO_CTL5_VM_SCR_0
#define GPIO16_LAST_REG 0x58b4 // GPIO_CTL5_SPARE_0
#define GPIO17_FIRST_REG 0x10000 // GPIO_A_ENABLE_CONFIG_00_0
#define GPIO17_LAST_REG 0x10014 // GPIO_A_INTERRUPT_CLEAR_00_0
#define GPIO18_FIRST_REG 0x10020 // GPIO_A_ENABLE_CONFIG_01_0
#define GPIO18_LAST_REG 0x10034 // GPIO_A_INTERRUPT_CLEAR_01_0
#define GPIO19_FIRST_REG 0x10040 // GPIO_A_ENABLE_CONFIG_02_0
#define GPIO19_LAST_REG 0x10054 // GPIO_A_INTERRUPT_CLEAR_02_0
#define GPIO20_FIRST_REG 0x10060 // GPIO_A_ENABLE_CONFIG_03_0
#define GPIO20_LAST_REG 0x10074 // GPIO_A_INTERRUPT_CLEAR_03_0
#define GPIO21_FIRST_REG 0x10080 // GPIO_A_ENABLE_CONFIG_04_0
#define GPIO21_LAST_REG 0x10094 // GPIO_A_INTERRUPT_CLEAR_04_0
#define GPIO22_FIRST_REG 0x100a0 // GPIO_A_ENABLE_CONFIG_05_0
#define GPIO22_LAST_REG 0x100b4 // GPIO_A_INTERRUPT_CLEAR_05_0
#define GPIO23_FIRST_REG 0x100c0 // GPIO_A_ENABLE_CONFIG_06_0
#define GPIO23_LAST_REG 0x100d4 // GPIO_A_INTERRUPT_CLEAR_06_0
#define GPIO24_FIRST_REG 0x100e0 // GPIO_A_ENABLE_CONFIG_07_0
#define GPIO24_LAST_REG 0x100f4 // GPIO_A_INTERRUPT_CLEAR_07_0
#define GPIO25_FIRST_REG 0x10100 // GPIO_A_INTERRUPT_STATUS_G0_0
#define GPIO25_LAST_REG 0x1011c // GPIO_A_INTERRUPT_STATUS_G7_0
#define GPIO26_FIRST_REG 0x10200 // GPIO_AC_ENABLE_CONFIG_00_0
#define GPIO26_LAST_REG 0x10214 // GPIO_AC_INTERRUPT_CLEAR_00_0
#define GPIO27_FIRST_REG 0x10220 // GPIO_AC_ENABLE_CONFIG_01_0
#define GPIO27_LAST_REG 0x10234 // GPIO_AC_INTERRUPT_CLEAR_01_0
#define GPIO28_FIRST_REG 0x10240 // GPIO_AC_ENABLE_CONFIG_02_0
#define GPIO28_LAST_REG 0x10254 // GPIO_AC_INTERRUPT_CLEAR_02_0
#define GPIO29_FIRST_REG 0x10260 // GPIO_AC_ENABLE_CONFIG_03_0
#define GPIO29_LAST_REG 0x10274 // GPIO_AC_INTERRUPT_CLEAR_03_0
#define GPIO30_FIRST_REG 0x10280 // GPIO_AC_ENABLE_CONFIG_04_0
#define GPIO30_LAST_REG 0x10294 // GPIO_AC_INTERRUPT_CLEAR_04_0
#define GPIO31_FIRST_REG 0x102a0 // GPIO_AC_ENABLE_CONFIG_05_0
#define GPIO31_LAST_REG 0x102b4 // GPIO_AC_INTERRUPT_CLEAR_05_0
#define GPIO32_FIRST_REG 0x102c0 // GPIO_AC_ENABLE_CONFIG_06_0
#define GPIO32_LAST_REG 0x102d4 // GPIO_AC_INTERRUPT_CLEAR_06_0
#define GPIO33_FIRST_REG 0x102e0 // GPIO_AC_ENABLE_CONFIG_07_0
#define GPIO33_LAST_REG 0x102f4 // GPIO_AC_INTERRUPT_CLEAR_07_0
#define GPIO34_FIRST_REG 0x10300 // GPIO_AC_INTERRUPT_STATUS_G0_0
#define GPIO34_LAST_REG 0x1031c // GPIO_AC_INTERRUPT_STATUS_G7_0
#define GPIO35_FIRST_REG 0x10400 // GPIO_AD_ENABLE_CONFIG_00_0
#define GPIO35_LAST_REG 0x10414 // GPIO_AD_INTERRUPT_CLEAR_00_0
#define GPIO36_FIRST_REG 0x10420 // GPIO_AD_ENABLE_CONFIG_01_0
#define GPIO36_LAST_REG 0x10434 // GPIO_AD_INTERRUPT_CLEAR_01_0
#define GPIO37_FIRST_REG 0x10440 // GPIO_AD_ENABLE_CONFIG_02_0
#define GPIO37_LAST_REG 0x10454 // GPIO_AD_INTERRUPT_CLEAR_02_0
#define GPIO38_FIRST_REG 0x10460 // GPIO_AD_ENABLE_CONFIG_03_0
#define GPIO38_LAST_REG 0x10474 // GPIO_AD_INTERRUPT_CLEAR_03_0
#define GPIO39_FIRST_REG 0x10500 // GPIO_AD_INTERRUPT_STATUS_G0_0
#define GPIO39_LAST_REG 0x1051c // GPIO_AD_INTERRUPT_STATUS_G7_0
#define GPIO40_FIRST_REG 0x10600 // GPIO_B_ENABLE_CONFIG_00_0
#define GPIO40_LAST_REG 0x10614 // GPIO_B_INTERRUPT_CLEAR_00_0
#define GPIO41_FIRST_REG 0x10700 // GPIO_B_INTERRUPT_STATUS_G0_0
#define GPIO41_LAST_REG 0x1071c // GPIO_B_INTERRUPT_STATUS_G7_0
#define GPIO42_FIRST_REG 0x11000 // GPIO_X_ENABLE_CONFIG_00_0
#define GPIO42_LAST_REG 0x11014 // GPIO_X_INTERRUPT_CLEAR_00_0
#define GPIO43_FIRST_REG 0x11020 // GPIO_X_ENABLE_CONFIG_01_0
#define GPIO43_LAST_REG 0x11034 // GPIO_X_INTERRUPT_CLEAR_01_0
#define GPIO44_FIRST_REG 0x11040 // GPIO_X_ENABLE_CONFIG_02_0
#define GPIO44_LAST_REG 0x11054 // GPIO_X_INTERRUPT_CLEAR_02_0
#define GPIO45_FIRST_REG 0x11060 // GPIO_X_ENABLE_CONFIG_03_0
#define GPIO45_LAST_REG 0x11074 // GPIO_X_INTERRUPT_CLEAR_03_0
#define GPIO46_FIRST_REG 0x11080 // GPIO_X_ENABLE_CONFIG_04_0
#define GPIO46_LAST_REG 0x11094 // GPIO_X_INTERRUPT_CLEAR_04_0
#define GPIO47_FIRST_REG 0x110a0 // GPIO_X_ENABLE_CONFIG_05_0
#define GPIO47_LAST_REG 0x110b4 // GPIO_X_INTERRUPT_CLEAR_05_0
#define GPIO48_FIRST_REG 0x110c0 // GPIO_X_ENABLE_CONFIG_06_0
#define GPIO48_LAST_REG 0x110d4 // GPIO_X_INTERRUPT_CLEAR_06_0
#define GPIO49_FIRST_REG 0x110e0 // GPIO_X_ENABLE_CONFIG_07_0
#define GPIO49_LAST_REG 0x110f4 // GPIO_X_INTERRUPT_CLEAR_07_0
#define GPIO50_FIRST_REG 0x11100 // GPIO_X_INTERRUPT_STATUS_G0_0
#define GPIO50_LAST_REG 0x1111c // GPIO_X_INTERRUPT_STATUS_G7_0
#define GPIO51_FIRST_REG 0x11200 // GPIO_Y_ENABLE_CONFIG_00_0
#define GPIO51_LAST_REG 0x11214 // GPIO_Y_INTERRUPT_CLEAR_00_0
#define GPIO52_FIRST_REG 0x11220 // GPIO_Y_ENABLE_CONFIG_01_0
#define GPIO52_LAST_REG 0x11234 // GPIO_Y_INTERRUPT_CLEAR_01_0
#define GPIO53_FIRST_REG 0x11240 // GPIO_Y_ENABLE_CONFIG_02_0
#define GPIO53_LAST_REG 0x11254 // GPIO_Y_INTERRUPT_CLEAR_02_0
#define GPIO54_FIRST_REG 0x11260 // GPIO_Y_ENABLE_CONFIG_03_0
#define GPIO54_LAST_REG 0x11274 // GPIO_Y_INTERRUPT_CLEAR_03_0
#define GPIO55_FIRST_REG 0x11280 // GPIO_Y_ENABLE_CONFIG_04_0
#define GPIO55_LAST_REG 0x11294 // GPIO_Y_INTERRUPT_CLEAR_04_0
#define GPIO56_FIRST_REG 0x112a0 // GPIO_Y_ENABLE_CONFIG_05_0
#define GPIO56_LAST_REG 0x112b4 // GPIO_Y_INTERRUPT_CLEAR_05_0
#define GPIO57_FIRST_REG 0x112c0 // GPIO_Y_ENABLE_CONFIG_06_0
#define GPIO57_LAST_REG 0x112d4 // GPIO_Y_INTERRUPT_CLEAR_06_0
#define GPIO58_FIRST_REG 0x112e0 // GPIO_Y_ENABLE_CONFIG_07_0
#define GPIO58_LAST_REG 0x112f4 // GPIO_Y_INTERRUPT_CLEAR_07_0
#define GPIO59_FIRST_REG 0x11300 // GPIO_Y_INTERRUPT_STATUS_G0_0
#define GPIO59_LAST_REG 0x1131c // GPIO_Y_INTERRUPT_STATUS_G7_0
#define GPIO60_FIRST_REG 0x11400 // GPIO_Z_ENABLE_CONFIG_00_0
#define GPIO60_LAST_REG 0x11414 // GPIO_Z_INTERRUPT_CLEAR_00_0
#define GPIO61_FIRST_REG 0x11420 // GPIO_Z_ENABLE_CONFIG_01_0
#define GPIO61_LAST_REG 0x11434 // GPIO_Z_INTERRUPT_CLEAR_01_0
#define GPIO62_FIRST_REG 0x11440 // GPIO_Z_ENABLE_CONFIG_02_0
#define GPIO62_LAST_REG 0x11454 // GPIO_Z_INTERRUPT_CLEAR_02_0
#define GPIO63_FIRST_REG 0x11460 // GPIO_Z_ENABLE_CONFIG_03_0
#define GPIO63_LAST_REG 0x11474 // GPIO_Z_INTERRUPT_CLEAR_03_0
#define GPIO64_FIRST_REG 0x11480 // GPIO_Z_ENABLE_CONFIG_04_0
#define GPIO64_LAST_REG 0x11494 // GPIO_Z_INTERRUPT_CLEAR_04_0
#define GPIO65_FIRST_REG 0x114a0 // GPIO_Z_ENABLE_CONFIG_05_0
#define GPIO65_LAST_REG 0x114b4 // GPIO_Z_INTERRUPT_CLEAR_05_0
#define GPIO66_FIRST_REG 0x114c0 // GPIO_Z_ENABLE_CONFIG_06_0
#define GPIO66_LAST_REG 0x114d4 // GPIO_Z_INTERRUPT_CLEAR_06_0
#define GPIO67_FIRST_REG 0x114e0 // GPIO_Z_ENABLE_CONFIG_07_0
#define GPIO67_LAST_REG 0x114f4 // GPIO_Z_INTERRUPT_CLEAR_07_0
#define GPIO68_FIRST_REG 0x11500 // GPIO_Z_INTERRUPT_STATUS_G0_0
#define GPIO68_LAST_REG 0x1151c // GPIO_Z_INTERRUPT_STATUS_G7_0
#define GPIO69_FIRST_REG 0x12000 // GPIO_M_ENABLE_CONFIG_00_0
#define GPIO69_LAST_REG 0x12014 // GPIO_M_INTERRUPT_CLEAR_00_0
#define GPIO70_FIRST_REG 0x12020 // GPIO_M_ENABLE_CONFIG_01_0
#define GPIO70_LAST_REG 0x12034 // GPIO_M_INTERRUPT_CLEAR_01_0
#define GPIO71_FIRST_REG 0x12040 // GPIO_M_ENABLE_CONFIG_02_0
#define GPIO71_LAST_REG 0x12054 // GPIO_M_INTERRUPT_CLEAR_02_0
#define GPIO72_FIRST_REG 0x12060 // GPIO_M_ENABLE_CONFIG_03_0
#define GPIO72_LAST_REG 0x12074 // GPIO_M_INTERRUPT_CLEAR_03_0
#define GPIO73_FIRST_REG 0x12080 // GPIO_M_ENABLE_CONFIG_04_0
#define GPIO73_LAST_REG 0x12094 // GPIO_M_INTERRUPT_CLEAR_04_0
#define GPIO74_FIRST_REG 0x120a0 // GPIO_M_ENABLE_CONFIG_05_0
#define GPIO74_LAST_REG 0x120b4 // GPIO_M_INTERRUPT_CLEAR_05_0
#define GPIO75_FIRST_REG 0x120c0 // GPIO_M_ENABLE_CONFIG_06_0
#define GPIO75_LAST_REG 0x120d4 // GPIO_M_INTERRUPT_CLEAR_06_0
#define GPIO76_FIRST_REG 0x120e0 // GPIO_M_ENABLE_CONFIG_07_0
#define GPIO76_LAST_REG 0x120f4 // GPIO_M_INTERRUPT_CLEAR_07_0
#define GPIO77_FIRST_REG 0x12100 // GPIO_M_INTERRUPT_STATUS_G0_0
#define GPIO77_LAST_REG 0x1211c // GPIO_M_INTERRUPT_STATUS_G7_0
#define GPIO78_FIRST_REG 0x12200 // GPIO_N_ENABLE_CONFIG_00_0
#define GPIO78_LAST_REG 0x12214 // GPIO_N_INTERRUPT_CLEAR_00_0
#define GPIO79_FIRST_REG 0x12220 // GPIO_N_ENABLE_CONFIG_01_0
#define GPIO79_LAST_REG 0x12234 // GPIO_N_INTERRUPT_CLEAR_01_0
#define GPIO80_FIRST_REG 0x12240 // GPIO_N_ENABLE_CONFIG_02_0
#define GPIO80_LAST_REG 0x12254 // GPIO_N_INTERRUPT_CLEAR_02_0
#define GPIO81_FIRST_REG 0x12260 // GPIO_N_ENABLE_CONFIG_03_0
#define GPIO81_LAST_REG 0x12274 // GPIO_N_INTERRUPT_CLEAR_03_0
#define GPIO82_FIRST_REG 0x12280 // GPIO_N_ENABLE_CONFIG_04_0
#define GPIO82_LAST_REG 0x12294 // GPIO_N_INTERRUPT_CLEAR_04_0
#define GPIO83_FIRST_REG 0x122a0 // GPIO_N_ENABLE_CONFIG_05_0
#define GPIO83_LAST_REG 0x122b4 // GPIO_N_INTERRUPT_CLEAR_05_0
#define GPIO84_FIRST_REG 0x122c0 // GPIO_N_ENABLE_CONFIG_06_0
#define GPIO84_LAST_REG 0x122d4 // GPIO_N_INTERRUPT_CLEAR_06_0
#define GPIO85_FIRST_REG 0x122e0 // GPIO_N_ENABLE_CONFIG_07_0
#define GPIO85_LAST_REG 0x122f4 // GPIO_N_INTERRUPT_CLEAR_07_0
#define GPIO86_FIRST_REG 0x12300 // GPIO_N_INTERRUPT_STATUS_G0_0
#define GPIO86_LAST_REG 0x1231c // GPIO_N_INTERRUPT_STATUS_G7_0
#define GPIO87_FIRST_REG 0x12400 // GPIO_P_ENABLE_CONFIG_00_0
#define GPIO87_LAST_REG 0x12414 // GPIO_P_INTERRUPT_CLEAR_00_0
#define GPIO88_FIRST_REG 0x12420 // GPIO_P_ENABLE_CONFIG_01_0
#define GPIO88_LAST_REG 0x12434 // GPIO_P_INTERRUPT_CLEAR_01_0
#define GPIO89_FIRST_REG 0x12440 // GPIO_P_ENABLE_CONFIG_02_0
#define GPIO89_LAST_REG 0x12454 // GPIO_P_INTERRUPT_CLEAR_02_0
#define GPIO90_FIRST_REG 0x12460 // GPIO_P_ENABLE_CONFIG_03_0
#define GPIO90_LAST_REG 0x12474 // GPIO_P_INTERRUPT_CLEAR_03_0
#define GPIO91_FIRST_REG 0x12480 // GPIO_P_ENABLE_CONFIG_04_0
#define GPIO91_LAST_REG 0x12494 // GPIO_P_INTERRUPT_CLEAR_04_0
#define GPIO92_FIRST_REG 0x124a0 // GPIO_P_ENABLE_CONFIG_05_0
#define GPIO92_LAST_REG 0x124b4 // GPIO_P_INTERRUPT_CLEAR_05_0
#define GPIO93_FIRST_REG 0x124c0 // GPIO_P_ENABLE_CONFIG_06_0
#define GPIO93_LAST_REG 0x124d4 // GPIO_P_INTERRUPT_CLEAR_06_0
#define GPIO94_FIRST_REG 0x124e0 // GPIO_P_ENABLE_CONFIG_07_0
#define GPIO94_LAST_REG 0x124f4 // GPIO_P_INTERRUPT_CLEAR_07_0
#define GPIO95_FIRST_REG 0x12500 // GPIO_P_INTERRUPT_STATUS_G0_0
#define GPIO95_LAST_REG 0x1251c // GPIO_P_INTERRUPT_STATUS_G7_0
#define GPIO96_FIRST_REG 0x12600 // GPIO_Q_ENABLE_CONFIG_00_0
#define GPIO96_LAST_REG 0x12614 // GPIO_Q_INTERRUPT_CLEAR_00_0
#define GPIO97_FIRST_REG 0x12620 // GPIO_Q_ENABLE_CONFIG_01_0
#define GPIO97_LAST_REG 0x12634 // GPIO_Q_INTERRUPT_CLEAR_01_0
#define GPIO98_FIRST_REG 0x12640 // GPIO_Q_ENABLE_CONFIG_02_0
#define GPIO98_LAST_REG 0x12654 // GPIO_Q_INTERRUPT_CLEAR_02_0
#define GPIO99_FIRST_REG 0x12660 // GPIO_Q_ENABLE_CONFIG_03_0
#define GPIO99_LAST_REG 0x12674 // GPIO_Q_INTERRUPT_CLEAR_03_0
#define GPIO100_FIRST_REG 0x12680 // GPIO_Q_ENABLE_CONFIG_04_0
#define GPIO100_LAST_REG 0x12694 // GPIO_Q_INTERRUPT_CLEAR_04_0
#define GPIO101_FIRST_REG 0x126a0 // GPIO_Q_ENABLE_CONFIG_05_0
#define GPIO101_LAST_REG 0x126b4 // GPIO_Q_INTERRUPT_CLEAR_05_0
#define GPIO102_FIRST_REG 0x126c0 // GPIO_Q_ENABLE_CONFIG_06_0
#define GPIO102_LAST_REG 0x126d4 // GPIO_Q_INTERRUPT_CLEAR_06_0
#define GPIO103_FIRST_REG 0x126e0 // GPIO_Q_ENABLE_CONFIG_07_0
#define GPIO103_LAST_REG 0x126f4 // GPIO_Q_INTERRUPT_CLEAR_07_0
#define GPIO104_FIRST_REG 0x12700 // GPIO_Q_INTERRUPT_STATUS_G0_0
#define GPIO104_LAST_REG 0x1271c // GPIO_Q_INTERRUPT_STATUS_G7_0
#define GPIO105_FIRST_REG 0x12800 // GPIO_R_ENABLE_CONFIG_00_0
#define GPIO105_LAST_REG 0x12814 // GPIO_R_INTERRUPT_CLEAR_00_0
#define GPIO106_FIRST_REG 0x12820 // GPIO_R_ENABLE_CONFIG_01_0
#define GPIO106_LAST_REG 0x12834 // GPIO_R_INTERRUPT_CLEAR_01_0
#define GPIO107_FIRST_REG 0x12840 // GPIO_R_ENABLE_CONFIG_02_0
#define GPIO107_LAST_REG 0x12854 // GPIO_R_INTERRUPT_CLEAR_02_0
#define GPIO108_FIRST_REG 0x12860 // GPIO_R_ENABLE_CONFIG_03_0
#define GPIO108_LAST_REG 0x12874 // GPIO_R_INTERRUPT_CLEAR_03_0
#define GPIO109_FIRST_REG 0x12880 // GPIO_R_ENABLE_CONFIG_04_0
#define GPIO109_LAST_REG 0x12894 // GPIO_R_INTERRUPT_CLEAR_04_0
#define GPIO110_FIRST_REG 0x128a0 // GPIO_R_ENABLE_CONFIG_05_0
#define GPIO110_LAST_REG 0x128b4 // GPIO_R_INTERRUPT_CLEAR_05_0
#define GPIO111_FIRST_REG 0x12900 // GPIO_R_INTERRUPT_STATUS_G0_0
#define GPIO111_LAST_REG 0x1291c // GPIO_R_INTERRUPT_STATUS_G7_0
#define GPIO112_FIRST_REG 0x13000 // GPIO_K_ENABLE_CONFIG_00_0
#define GPIO112_LAST_REG 0x13014 // GPIO_K_INTERRUPT_CLEAR_00_0
#define GPIO113_FIRST_REG 0x13020 // GPIO_K_ENABLE_CONFIG_01_0
#define GPIO113_LAST_REG 0x13034 // GPIO_K_INTERRUPT_CLEAR_01_0
#define GPIO114_FIRST_REG 0x13040 // GPIO_K_ENABLE_CONFIG_02_0
#define GPIO114_LAST_REG 0x13054 // GPIO_K_INTERRUPT_CLEAR_02_0
#define GPIO115_FIRST_REG 0x13060 // GPIO_K_ENABLE_CONFIG_03_0
#define GPIO115_LAST_REG 0x13074 // GPIO_K_INTERRUPT_CLEAR_03_0
#define GPIO116_FIRST_REG 0x13080 // GPIO_K_ENABLE_CONFIG_04_0
#define GPIO116_LAST_REG 0x13094 // GPIO_K_INTERRUPT_CLEAR_04_0
#define GPIO117_FIRST_REG 0x130a0 // GPIO_K_ENABLE_CONFIG_05_0
#define GPIO117_LAST_REG 0x130b4 // GPIO_K_INTERRUPT_CLEAR_05_0
#define GPIO118_FIRST_REG 0x130c0 // GPIO_K_ENABLE_CONFIG_06_0
#define GPIO118_LAST_REG 0x130d4 // GPIO_K_INTERRUPT_CLEAR_06_0
#define GPIO119_FIRST_REG 0x130e0 // GPIO_K_ENABLE_CONFIG_07_0
#define GPIO119_LAST_REG 0x130f4 // GPIO_K_INTERRUPT_CLEAR_07_0
#define GPIO120_FIRST_REG 0x13100 // GPIO_K_INTERRUPT_STATUS_G0_0
#define GPIO120_LAST_REG 0x1311c // GPIO_K_INTERRUPT_STATUS_G7_0
#define GPIO121_FIRST_REG 0x13200 // GPIO_L_ENABLE_CONFIG_00_0
#define GPIO121_LAST_REG 0x13214 // GPIO_L_INTERRUPT_CLEAR_00_0
#define GPIO122_FIRST_REG 0x13220 // GPIO_L_ENABLE_CONFIG_01_0
#define GPIO122_LAST_REG 0x13234 // GPIO_L_INTERRUPT_CLEAR_01_0
#define GPIO123_FIRST_REG 0x13240 // GPIO_L_ENABLE_CONFIG_02_0
#define GPIO123_LAST_REG 0x13254 // GPIO_L_INTERRUPT_CLEAR_02_0
#define GPIO124_FIRST_REG 0x13260 // GPIO_L_ENABLE_CONFIG_03_0
#define GPIO124_LAST_REG 0x13274 // GPIO_L_INTERRUPT_CLEAR_03_0
#define GPIO125_FIRST_REG 0x13300 // GPIO_L_INTERRUPT_STATUS_G0_0
#define GPIO125_LAST_REG 0x1331c // GPIO_L_INTERRUPT_STATUS_G7_0
#define GPIO126_FIRST_REG 0x13400 // GPIO_AG_ENABLE_CONFIG_00_0
#define GPIO126_LAST_REG 0x13414 // GPIO_AG_INTERRUPT_CLEAR_00_0
#define GPIO127_FIRST_REG 0x13420 // GPIO_AG_ENABLE_CONFIG_01_0
#define GPIO127_LAST_REG 0x13434 // GPIO_AG_INTERRUPT_CLEAR_01_0
#define GPIO128_FIRST_REG 0x13440 // GPIO_AG_ENABLE_CONFIG_02_0
#define GPIO128_LAST_REG 0x13454 // GPIO_AG_INTERRUPT_CLEAR_02_0
#define GPIO129_FIRST_REG 0x13460 // GPIO_AG_ENABLE_CONFIG_03_0
#define GPIO129_LAST_REG 0x13474 // GPIO_AG_INTERRUPT_CLEAR_03_0
#define GPIO130_FIRST_REG 0x13480 // GPIO_AG_ENABLE_CONFIG_04_0
#define GPIO130_LAST_REG 0x13494 // GPIO_AG_INTERRUPT_CLEAR_04_0
#define GPIO131_FIRST_REG 0x134a0 // GPIO_AG_ENABLE_CONFIG_05_0
#define GPIO131_LAST_REG 0x134b4 // GPIO_AG_INTERRUPT_CLEAR_05_0
#define GPIO132_FIRST_REG 0x134c0 // GPIO_AG_ENABLE_CONFIG_06_0
#define GPIO132_LAST_REG 0x134d4 // GPIO_AG_INTERRUPT_CLEAR_06_0
#define GPIO133_FIRST_REG 0x134e0 // GPIO_AG_ENABLE_CONFIG_07_0
#define GPIO133_LAST_REG 0x134f4 // GPIO_AG_INTERRUPT_CLEAR_07_0
#define GPIO134_FIRST_REG 0x13500 // GPIO_AG_INTERRUPT_STATUS_G0_0
#define GPIO134_LAST_REG 0x1351c // GPIO_AG_INTERRUPT_STATUS_G7_0
#define GPIO135_FIRST_REG 0x13600 // GPIO_AE_ENABLE_CONFIG_00_0
#define GPIO135_LAST_REG 0x13614 // GPIO_AE_INTERRUPT_CLEAR_00_0
#define GPIO136_FIRST_REG 0x13620 // GPIO_AE_ENABLE_CONFIG_01_0
#define GPIO136_LAST_REG 0x13634 // GPIO_AE_INTERRUPT_CLEAR_01_0
#define GPIO137_FIRST_REG 0x13700 // GPIO_AE_INTERRUPT_STATUS_G0_0
#define GPIO137_LAST_REG 0x1371c // GPIO_AE_INTERRUPT_STATUS_G7_0
#define GPIO138_FIRST_REG 0x13800 // GPIO_AF_ENABLE_CONFIG_00_0
#define GPIO138_LAST_REG 0x13814 // GPIO_AF_INTERRUPT_CLEAR_00_0
#define GPIO139_FIRST_REG 0x13820 // GPIO_AF_ENABLE_CONFIG_01_0
#define GPIO139_LAST_REG 0x13834 // GPIO_AF_INTERRUPT_CLEAR_01_0
#define GPIO140_FIRST_REG 0x13840 // GPIO_AF_ENABLE_CONFIG_02_0
#define GPIO140_LAST_REG 0x13854 // GPIO_AF_INTERRUPT_CLEAR_02_0
#define GPIO141_FIRST_REG 0x13860 // GPIO_AF_ENABLE_CONFIG_03_0
#define GPIO141_LAST_REG 0x13874 // GPIO_AF_INTERRUPT_CLEAR_03_0
#define GPIO142_FIRST_REG 0x13900 // GPIO_AF_INTERRUPT_STATUS_G0_0
#define GPIO142_LAST_REG 0x1391c // GPIO_AF_INTERRUPT_STATUS_G7_0
#define GPIO143_FIRST_REG 0x14000 // GPIO_G_ENABLE_CONFIG_00_0
#define GPIO143_LAST_REG 0x14014 // GPIO_G_INTERRUPT_CLEAR_00_0
#define GPIO144_FIRST_REG 0x14020 // GPIO_G_ENABLE_CONFIG_01_0
#define GPIO144_LAST_REG 0x14034 // GPIO_G_INTERRUPT_CLEAR_01_0
#define GPIO145_FIRST_REG 0x14040 // GPIO_G_ENABLE_CONFIG_02_0
#define GPIO145_LAST_REG 0x14054 // GPIO_G_INTERRUPT_CLEAR_02_0
#define GPIO146_FIRST_REG 0x14060 // GPIO_G_ENABLE_CONFIG_03_0
#define GPIO146_LAST_REG 0x14074 // GPIO_G_INTERRUPT_CLEAR_03_0
#define GPIO147_FIRST_REG 0x14080 // GPIO_G_ENABLE_CONFIG_04_0
#define GPIO147_LAST_REG 0x14094 // GPIO_G_INTERRUPT_CLEAR_04_0
#define GPIO148_FIRST_REG 0x140a0 // GPIO_G_ENABLE_CONFIG_05_0
#define GPIO148_LAST_REG 0x140b4 // GPIO_G_INTERRUPT_CLEAR_05_0
#define GPIO149_FIRST_REG 0x140c0 // GPIO_G_ENABLE_CONFIG_06_0
#define GPIO149_LAST_REG 0x140d4 // GPIO_G_INTERRUPT_CLEAR_06_0
#define GPIO150_FIRST_REG 0x140e0 // GPIO_G_ENABLE_CONFIG_07_0
#define GPIO150_LAST_REG 0x140f4 // GPIO_G_INTERRUPT_CLEAR_07_0
#define GPIO151_FIRST_REG 0x14100 // GPIO_G_INTERRUPT_STATUS_G0_0
#define GPIO151_LAST_REG 0x1411c // GPIO_G_INTERRUPT_STATUS_G7_0
#define GPIO152_FIRST_REG 0x14200 // GPIO_H_ENABLE_CONFIG_00_0
#define GPIO152_LAST_REG 0x14214 // GPIO_H_INTERRUPT_CLEAR_00_0
#define GPIO153_FIRST_REG 0x14220 // GPIO_H_ENABLE_CONFIG_01_0
#define GPIO153_LAST_REG 0x14234 // GPIO_H_INTERRUPT_CLEAR_01_0
#define GPIO154_FIRST_REG 0x14240 // GPIO_H_ENABLE_CONFIG_02_0
#define GPIO154_LAST_REG 0x14254 // GPIO_H_INTERRUPT_CLEAR_02_0
#define GPIO155_FIRST_REG 0x14260 // GPIO_H_ENABLE_CONFIG_03_0
#define GPIO155_LAST_REG 0x14274 // GPIO_H_INTERRUPT_CLEAR_03_0
#define GPIO156_FIRST_REG 0x14280 // GPIO_H_ENABLE_CONFIG_04_0
#define GPIO156_LAST_REG 0x14294 // GPIO_H_INTERRUPT_CLEAR_04_0
#define GPIO157_FIRST_REG 0x142a0 // GPIO_H_ENABLE_CONFIG_05_0
#define GPIO157_LAST_REG 0x142b4 // GPIO_H_INTERRUPT_CLEAR_05_0
#define GPIO158_FIRST_REG 0x142c0 // GPIO_H_ENABLE_CONFIG_06_0
#define GPIO158_LAST_REG 0x142d4 // GPIO_H_INTERRUPT_CLEAR_06_0
#define GPIO159_FIRST_REG 0x142e0 // GPIO_H_ENABLE_CONFIG_07_0
#define GPIO159_LAST_REG 0x142f4 // GPIO_H_INTERRUPT_CLEAR_07_0
#define GPIO160_FIRST_REG 0x14300 // GPIO_H_INTERRUPT_STATUS_G0_0
#define GPIO160_LAST_REG 0x1431c // GPIO_H_INTERRUPT_STATUS_G7_0
#define GPIO161_FIRST_REG 0x14400 // GPIO_I_ENABLE_CONFIG_00_0
#define GPIO161_LAST_REG 0x14414 // GPIO_I_INTERRUPT_CLEAR_00_0
#define GPIO162_FIRST_REG 0x14420 // GPIO_I_ENABLE_CONFIG_01_0
#define GPIO162_LAST_REG 0x14434 // GPIO_I_INTERRUPT_CLEAR_01_0
#define GPIO163_FIRST_REG 0x14440 // GPIO_I_ENABLE_CONFIG_02_0
#define GPIO163_LAST_REG 0x14454 // GPIO_I_INTERRUPT_CLEAR_02_0
#define GPIO164_FIRST_REG 0x14460 // GPIO_I_ENABLE_CONFIG_03_0
#define GPIO164_LAST_REG 0x14474 // GPIO_I_INTERRUPT_CLEAR_03_0
#define GPIO165_FIRST_REG 0x14480 // GPIO_I_ENABLE_CONFIG_04_0
#define GPIO165_LAST_REG 0x14494 // GPIO_I_INTERRUPT_CLEAR_04_0
#define GPIO166_FIRST_REG 0x144a0 // GPIO_I_ENABLE_CONFIG_05_0
#define GPIO166_LAST_REG 0x144b4 // GPIO_I_INTERRUPT_CLEAR_05_0
#define GPIO167_FIRST_REG 0x144c0 // GPIO_I_ENABLE_CONFIG_06_0
#define GPIO167_LAST_REG 0x144d4 // GPIO_I_INTERRUPT_CLEAR_06_0
#define GPIO168_FIRST_REG 0x14500 // GPIO_I_INTERRUPT_STATUS_G0_0
#define GPIO168_LAST_REG 0x1451c // GPIO_I_INTERRUPT_STATUS_G7_0
#define GPIO169_FIRST_REG 0x15000 // GPIO_J_ENABLE_CONFIG_00_0
#define GPIO169_LAST_REG 0x15014 // GPIO_J_INTERRUPT_CLEAR_00_0
#define GPIO170_FIRST_REG 0x15020 // GPIO_J_ENABLE_CONFIG_01_0
#define GPIO170_LAST_REG 0x15034 // GPIO_J_INTERRUPT_CLEAR_01_0
#define GPIO171_FIRST_REG 0x15040 // GPIO_J_ENABLE_CONFIG_02_0
#define GPIO171_LAST_REG 0x15054 // GPIO_J_INTERRUPT_CLEAR_02_0
#define GPIO172_FIRST_REG 0x15060 // GPIO_J_ENABLE_CONFIG_03_0
#define GPIO172_LAST_REG 0x15074 // GPIO_J_INTERRUPT_CLEAR_03_0
#define GPIO173_FIRST_REG 0x15080 // GPIO_J_ENABLE_CONFIG_04_0
#define GPIO173_LAST_REG 0x15094 // GPIO_J_INTERRUPT_CLEAR_04_0
#define GPIO174_FIRST_REG 0x150a0 // GPIO_J_ENABLE_CONFIG_05_0
#define GPIO174_LAST_REG 0x150b4 // GPIO_J_INTERRUPT_CLEAR_05_0
#define GPIO175_FIRST_REG 0x15100 // GPIO_J_INTERRUPT_STATUS_G0_0
#define GPIO175_LAST_REG 0x1511c // GPIO_J_INTERRUPT_STATUS_G7_0
#define GPIO176_FIRST_REG 0x15200 // GPIO_C_ENABLE_CONFIG_00_0
#define GPIO176_LAST_REG 0x15214 // GPIO_C_INTERRUPT_CLEAR_00_0
#define GPIO177_FIRST_REG 0x15220 // GPIO_C_ENABLE_CONFIG_01_0
#define GPIO177_LAST_REG 0x15234 // GPIO_C_INTERRUPT_CLEAR_01_0
#define GPIO178_FIRST_REG 0x15240 // GPIO_C_ENABLE_CONFIG_02_0
#define GPIO178_LAST_REG 0x15254 // GPIO_C_INTERRUPT_CLEAR_02_0
#define GPIO179_FIRST_REG 0x15260 // GPIO_C_ENABLE_CONFIG_03_0
#define GPIO179_LAST_REG 0x15274 // GPIO_C_INTERRUPT_CLEAR_03_0
#define GPIO180_FIRST_REG 0x15280 // GPIO_C_ENABLE_CONFIG_04_0
#define GPIO180_LAST_REG 0x15294 // GPIO_C_INTERRUPT_CLEAR_04_0
#define GPIO181_FIRST_REG 0x152a0 // GPIO_C_ENABLE_CONFIG_05_0
#define GPIO181_LAST_REG 0x152b4 // GPIO_C_INTERRUPT_CLEAR_05_0
#define GPIO182_FIRST_REG 0x152c0 // GPIO_C_ENABLE_CONFIG_06_0
#define GPIO182_LAST_REG 0x152d4 // GPIO_C_INTERRUPT_CLEAR_06_0
#define GPIO183_FIRST_REG 0x152e0 // GPIO_C_ENABLE_CONFIG_07_0
#define GPIO183_LAST_REG 0x152f4 // GPIO_C_INTERRUPT_CLEAR_07_0
#define GPIO184_FIRST_REG 0x15300 // GPIO_C_INTERRUPT_STATUS_G0_0
#define GPIO184_LAST_REG 0x1531c // GPIO_C_INTERRUPT_STATUS_G7_0
#define GPIO185_FIRST_REG 0x15400 // GPIO_D_ENABLE_CONFIG_00_0
#define GPIO185_LAST_REG 0x15414 // GPIO_D_INTERRUPT_CLEAR_00_0
#define GPIO186_FIRST_REG 0x15420 // GPIO_D_ENABLE_CONFIG_01_0
#define GPIO186_LAST_REG 0x15434 // GPIO_D_INTERRUPT_CLEAR_01_0
#define GPIO187_FIRST_REG 0x15440 // GPIO_D_ENABLE_CONFIG_02_0
#define GPIO187_LAST_REG 0x15454 // GPIO_D_INTERRUPT_CLEAR_02_0
#define GPIO188_FIRST_REG 0x15460 // GPIO_D_ENABLE_CONFIG_03_0
#define GPIO188_LAST_REG 0x15474 // GPIO_D_INTERRUPT_CLEAR_03_0
#define GPIO189_FIRST_REG 0x15500 // GPIO_D_INTERRUPT_STATUS_G0_0
#define GPIO189_LAST_REG 0x1551c // GPIO_D_INTERRUPT_STATUS_G7_0
#define GPIO190_FIRST_REG 0x15600 // GPIO_E_ENABLE_CONFIG_00_0
#define GPIO190_LAST_REG 0x15614 // GPIO_E_INTERRUPT_CLEAR_00_0
#define GPIO191_FIRST_REG 0x15620 // GPIO_E_ENABLE_CONFIG_01_0
#define GPIO191_LAST_REG 0x15634 // GPIO_E_INTERRUPT_CLEAR_01_0
#define GPIO192_FIRST_REG 0x15640 // GPIO_E_ENABLE_CONFIG_02_0
#define GPIO192_LAST_REG 0x15654 // GPIO_E_INTERRUPT_CLEAR_02_0
#define GPIO193_FIRST_REG 0x15660 // GPIO_E_ENABLE_CONFIG_03_0
#define GPIO193_LAST_REG 0x15674 // GPIO_E_INTERRUPT_CLEAR_03_0
#define GPIO194_FIRST_REG 0x15680 // GPIO_E_ENABLE_CONFIG_04_0
#define GPIO194_LAST_REG 0x15694 // GPIO_E_INTERRUPT_CLEAR_04_0
#define GPIO195_FIRST_REG 0x156a0 // GPIO_E_ENABLE_CONFIG_05_0
#define GPIO195_LAST_REG 0x156b4 // GPIO_E_INTERRUPT_CLEAR_05_0
#define GPIO196_FIRST_REG 0x156c0 // GPIO_E_ENABLE_CONFIG_06_0
#define GPIO196_LAST_REG 0x156d4 // GPIO_E_INTERRUPT_CLEAR_06_0
#define GPIO197_FIRST_REG 0x156e0 // GPIO_E_ENABLE_CONFIG_07_0
#define GPIO197_LAST_REG 0x156f4 // GPIO_E_INTERRUPT_CLEAR_07_0
#define GPIO198_FIRST_REG 0x15700 // GPIO_E_INTERRUPT_STATUS_G0_0
#define GPIO198_LAST_REG 0x1571c // GPIO_E_INTERRUPT_STATUS_G7_0
#define GPIO199_FIRST_REG 0x15800 // GPIO_F_ENABLE_CONFIG_00_0
#define GPIO199_LAST_REG 0x15814 // GPIO_F_INTERRUPT_CLEAR_00_0
#define GPIO200_FIRST_REG 0x15820 // GPIO_F_ENABLE_CONFIG_01_0
#define GPIO200_LAST_REG 0x15834 // GPIO_F_INTERRUPT_CLEAR_01_0
#define GPIO201_FIRST_REG 0x15840 // GPIO_F_ENABLE_CONFIG_02_0
#define GPIO201_LAST_REG 0x15854 // GPIO_F_INTERRUPT_CLEAR_02_0
#define GPIO202_FIRST_REG 0x15860 // GPIO_F_ENABLE_CONFIG_03_0
#define GPIO202_LAST_REG 0x15874 // GPIO_F_INTERRUPT_CLEAR_03_0
#define GPIO203_FIRST_REG 0x15880 // GPIO_F_ENABLE_CONFIG_04_0
#define GPIO203_LAST_REG 0x15894 // GPIO_F_INTERRUPT_CLEAR_04_0
#define GPIO204_FIRST_REG 0x158a0 // GPIO_F_ENABLE_CONFIG_05_0
#define GPIO204_LAST_REG 0x158b4 // GPIO_F_INTERRUPT_CLEAR_05_0
#define GPIO205_FIRST_REG 0x15900 // GPIO_F_INTERRUPT_STATUS_G0_0
#define GPIO205_LAST_REG 0x1591c // GPIO_F_INTERRUPT_STATUS_G7_0

// To satisfy various compilers and platforms,
// we let users control the types and syntax of certain constants, using macros.
#ifndef MK_SHIFT_CONST
  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST
  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ENUM_CONST
  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_ADDR_CONST
  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST
  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
#endif
#ifndef MK_SHIFT_CONST_64
  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_MASK_CONST_64
  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ENUM_CONST_64
  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
#endif
#ifndef MK_ADDR_CONST_64
  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
#endif
#ifndef MK_FIELD_CONST_64
  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
#endif

#endif // ifndef ARGPIO_H_INC
